By John Blyler
Power continues to be a challenge in the design of System-on-Chips (SoCs) for the mobile handheld space. Consumers want ever-increasing compute capabilities to quickly handle new handset functionality as well as perform traditional PC applications. To meet these needs, chip designers must continue to push the performance envelope with a variety of low-to-high end processing cores while maintaining the same power budget as earlier generation handhelds.

As if that wasn’t challenging enough, designers must also pay attention to the thermal envelope limit. Why has thermal become so important? First, a handheld device can’t become too hot to hold. Second, uncontrolled or unplanned thermal affects could force the handheld device to throttle down on performance to prevent overheating of the circuitry. Both are “no-no’s” from a consumer use perspective.

Figure 1: The increasing power gap highlights the growing importance of battery and thermal constraints in system chip design. (Source: Apache Design)

Balancing the competing performance-power-thermal requirements necessitates a system-level approach to design. But the balance has shifted in recent years as power concerns now seem to dominate over performance issues. “In my opinion, power is leading performance, especially since the thermal limit has become a challenge,” explained Charles Matar, vice president of engineering at Qualcomm, during a recent keynote at the Ansys-Apache Design “Dimensions of Electronic Design” seminar.

To really manage power usage, battery life and thermal envelope limits, one must design for multiple performance nodes. These modes, in turn, are based upon the software application that is running and other workload concerns, such as connectivity. Dealing with the integration of both hardware and software (firmware, RTOS and OS) subsystems mandates a full system-level approach. But full system power modeling tools have lagged behind performance-focused modeling.

Software compilers for heterogeneous-core chips with many ARM processors, GPUs, DSPs, and other cores are not optimized for the system. This creates software executables that are not workload optimized across all the processing units, observed Simon Bloch, an adviser in the Advanced Systems Engineering Lab at Samsung.

“EDA tool companies continue to improve their offerings but are still designing for performance—their number one priority,” said Matar. He cited place and route (P&R) tools as an example, where algorithms that focus on component placement need to be more thermally and power-aware.

Bloch agreed, noting that the electronic system-level (ESL) and SystemC community had standards for modeling performance, but there were no standards that exist for modeling power.

But the development of high-level ESL and TLM power modeling tools face at least one major challenge. Many believe there needs to be more industry focus on system-level power models and standards that reach well beyond the existing chip-level power standards. To achieve this goal, all of the SoC industry fabless intellectual property (IP) vendors must work together with foundation IP providers to develop standards for both power and thermal modeling.

Developing these system-level models and standards would also address the growing issue of overdesign. Generous design margins are often the result of engineers working in silos. “As design teams are spread across companies and continents, designers may not be able to share the same information,” explained Aveek Sarkar, vice president of product engineering and customer support at Apache Design. “If you are designing the IP, you may not be aware how the IP is being used at the full chip level. So you tend to over-compensate, over-design to protect yourself for the entire system. That leads to increased cost and power usage.”

Matar ended his keynote presentation by talking about new technology trends in mobile SoC design, including heterogeneous computing, 3D-ICs with through-silicon vias (TSVs) and finFet transistor structures.

Heterogeneous computing refers to a variety of low-, medium- and high-performance processing cores on the same SoC, sometimes referred to as small and big cores. Heterogeneous also including different types of cores, from general-purpose (GP) to graphic computing units (GPUs) and application-specific processors. The availability of these different processing engines means that chip designers can offload tasks to the appropriate processor to optimize power and performance. But these offloads must work closely with the high-level operating system (HLOS) so the software programmer can take full advantage of the available compute power. Naturally, all of this requires good hardware and software system-modeling tools.

As with any new technology, 3D-ICs with TSVs still face yield, cost, and thermal challenges, noted Matar. He observed that TSVs will be especially helpful for performance and power management in the graphics and memory areas.

New process technology such as finFet transistor structures will allow designers to continue to benefit from voltage scaling at lower process nodes. 3D structures are a shift in paradigm from a transistor perspective that should provide the same or higher performance level as today’s planar technology but at lower power (voltage).

Figure 2: Decreasing noise margins at lower process nodes will pose a challenge for finFet device designers. (Source: Apache Design)

Still, finFet structures won’t be without their tradeoffs. For example, supply voltage scaling for finFets will range from 700 to 800 mV by next year. “But the supply noise due to switching currents on the SoC will continue to rise,” said Sarkar. “So these two trends of high frequency devices at low power will play against each other.”

Regardless of the latest technology trends, the broader view afforded by a system-level approach will be needed in mobile handset and most other electronic system designs. Sarkar made this point by citing a customer design that involved and SoC application processor. The customer integrated the SoC into a package—all designed by the same company. The chip-package system was designed to work at 2GHz, which it did. But when the chip-package was sent to the end customer it failed. Why? The end customer incorporated the chip-package subsystem into a low-cost board and the voltage dropped by 300 mV, which resulted in the chip performance dropping to 1.2GHz.

The need for a system-level model that incorporates power, thermal and performance awareness is becoming critical in the mobile handheld, as well as the general electronic markets. Both speakers from Qualcomm and Ansys-Apache Design shared their perspectives, from SoC to larger electronic systems, as to why this trend will continue. Hopefully, the EDA tools industry and power standards organizations are listening.

Tags: 3D IC, Ansys, Apache Design, finFETS, Qualcomm, Samsung, TSVs

This entry was posted on Thursday, October 25th, 2012 at 12:01 am and is filed under Top Stories. You can follow any responses to this entry through the RSS 2.0 feed. You can leave a response, or trackback from your own site.