Gate-Level Simulation Methodology
Verification at 40nm and below requires complex timing checks, long runtimes, large amounts of memory, and apps to handle design-for-test and low-power considerations. It is critical that teams begin gate-level simulation (GLS) as early in the design cycle as possible, that the simulator run in high-performance mode, and that a proven simulation methodology be in place. This white paper explores new simulator use models and methodologies that boost GLS productivity, including extraction via static timing analysis and linting. Using these approaches, designers can focus on verifying real gate-level issues rather than waste expensive simulation cycles on re-verifying working circuits.
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