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ESL Market Potential

By Gabe Moretti

In preparing for my first panel discussion on ESL (see I spoke with Gary Smith to get his views on this segment of the EDA market.  As usual Gary was very helpful, so if I misunderstood it is completely my fault.  First the bad news: there are still no standards systems architects can rely upon.  This means that during product implementation the characteristics of the architectural design are derived in a subjective manner.  Designers implement what they understand, not necessarily what is intended.

This lack of standards could also be good news, since our industry has been quite attentive to such requirements, and certainly has the proven expertise to develop effective standards.  The experience gained by architects and designers can be used by standards developers.  We now not only understand what is required but have a better idea of what might work and what does not work.

Of course Accellera has developed standards that are useful in system level development, SystemVerilog, VMM, UVM, and IP-XACT.  But, and this is Gary’s point, they address development and verification, not architectural design.  Although there have been attempts to develop an architecture description language, those initiatives are still by en large academic exercises.

On the positive note, ESL is growing, may be not as aggressively as once thought from a financial point of view, but its methods are based on solid and proven grounds and offer much room for expansion.  The revenue hockey stick phenomenon predicted a couple of years ago did not materialize.  But revenue from ESL tools is steadily growing and shows a definite positive trend.  Platform based design, according to Gary is now an established methodology and it has made possible the implementation of very complex systems while cutting development costs, some time up to 44%.  Platform based design requires both certified IP blocks and verified firmware.  Accellera is dedicating significant energy to IP issues and its work is well accepted by IP vendors.

During the discussion on ESL the panelists were very focused on the software side of the problem when it comes to verification.  Virtual prototyping and system emulation offer significant growth opportunities in EDA.  Jon MacDonald of Mentor observed that “there is a strong need for each tool to have the ability to interact with representations from other design spaces.  Engineering disciplines have been compartmentalized for a long time to address significant issues in system complexity.  Each discipline needs development tools focused on reducing the complexity of that domain.”

Gary Smith also reinforced the observation made by Frank Schrrmeister of Cadence:

“Fact is that the core customers of EDA – the semiconductor houses – have taken on over the last two decades huge amounts of additional expertise as part of their developments. Where a set of drivers and a partnership with operating system vendors may have been enough 15 years ago, today the same vendors have to provide chips with reference ports of Android, Linux, Chrome OS and Windows Mobile just to win the socket. We all have to learn and deal with the aspects of those adjacent markets as they increasingly simply become a “must Deal with” for existing EDA customers.”

Gary pointed out that the role of the semiconductors companies has changed.  The foundries have taken on an increasing role in providing IP products constituting entire subsystems that include both hardware and software components.  This change is not an overt decision on the part of foundries to change their business model.  It is, instead, the natural result of process requirements.  Processes below 45 nm require cells that are very foundry specific and have indigenous software drivers, often to address power consumption requirements.

What came out of the panel is that the electronics part of a large heterogeneous system still plays the most important role.  The electronics subsystem is fundamental to the construction of the internet of things, certainly the most promising architecture of the near and more distant future.  The strategic item in designing a heterogeneous system is the communication of information from the non-electronic subsystem to the computational part.  This is the area that offers significant growth potential for EDA companies, together with the expansion in embedded software development and verification.

During the panel discussion Bill Neifert of Carbon observed that “like it or not, software can have a significant impact on the behavior of the system. Far too often, hardware decisions are made with no real data from the software team and software teams are forced to live with decisions the hardware team made without their input.”

And Brett Cline, of Forte added: “Integrating non-electronic components could help more accurately model the system prior to construction with obvious benefits. There are plenty of tools and technologies available to help model the non-electronic portions of a system. At some point, the tool flow becomes extremely complex and modeling the entire system becomes prohibitively expensive or difficult. Should EDA companies choose to tackle this problem, the getting the tool flow and integration will be paramount to being successful.”

Virtual prototyping needs to expand its role.  From an almost exclusively software verification tool it must grow to properly support “what-if” analysis to efficiently allow architects to trade-off hardware/software combinations in order to identify the optimum architecture.  This is particularly important when dealing with power consumption issues.

Of course, without cost and time constrints, architects could experiment with a number of different architectural solutions using present tools.  But such scenario is not practical even in the academic world, let alone in the commercial one.  The creation of algorithms and computational architectures that allow modeling of complex systems in a practical manner is a challenge as well as an opportunity for EDA.

Electronics companies have been developing embedded software, called firmware, at least since the introduction of the programmable calculator in 1970.  As the IP blocks have grown to become real subsystems, they incorporate firmware.  Thus companies like ARM and NVIDIA are selling IP products that contains significant amount of firmware.  The certification of these subsystems for each process node from the various foundries is becoming a necessary part of their commercialization.

Finally we must realize that expanding the role of ESL tools within a design will be critical in lowering the cost of backend work.  Optimization of the layout of a chip can be simplified by a clean architectural design that avoids many of the problems inherent with an inefficient and crowed layout.

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