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Blog Review October 10 2013

By Caroline Hayes

At the TSMC Open Innovation Platform (TSMC OIP) Ecosystem Forum, Richard Goering hears that 16mm FinFET design and 3D ICs are moving closer to volume production. Dr Cliff Hou, vice president, R&D, TSMC warned that although EDA tools and flows have been qualified, foundation IP has been validated, and interface IP is under development, one tool does not guarantee success, calling for a “more rigorous validation methodology”.

Steve Favre was also at TSMC OIP, discussing 450nm wafers. He wondered why EUV (extreme ultra violet) patterning has become a gating item for the move to 450nm, and how are these two related? Money, as usual, is the answer, It would cost billions of dollars to build a 450nm wafer fab and billions to move to EUV – why pay twice?

Lakshmi Mandyam from ARM’s smart connected community reflects on her journey from the power-hungry, boot-up slow laptop to a touch-sensor, multi-screen tablet. She ends by marking the anniversary of her laptop-free life. Maybe she should start an LA (Laptop Anonymous) support group?

Chip Design’s John Byler cringes with embarrassment while following up a nanotechtechnology lead at IEF in Dublin, Ireland. The lapse of government funding is proclaimed on the National Institute of Standards and Technology, accounting for the website’s and its affiliated websites’ closure. He turns to the French for further research, over a croissant – naturellement.

Pity Brian Fuller, caught off-guard by the usually genial  analyst Gary Smith in an interview for Unhinged.  Smith urged EDA vendors to be bolder, pooh-poohed the idea of industry consolidation, held forth on the power of the press and then complimented John Cooley. What is the world coming to?

Michael Posner sounds the alarm that “My RTL is an alien”, neatly timed to coincide with a white paper by Synopsys which details ways to accelerate FPGA (field programmable gate array)-based prototyping. With over 70% of today’s ASICs and systems-on-chips (SoCs) being prototyped in an FPGA, designers are looking for ways to ease the creation of FPGA-based prototypes directly from the ASIC design source files.

Gabe Moretti is feeling nostalgic in preparation for the Back to the Future Dinner organized by the EDA Consortium at the Computer Museum, Mountain View, California, this month.

In this blog he remembers the early days of EDA, when it was called CAD (computer aided design) and ruylith cut by hand. Those were the days!

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