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Advanced ARM CoreLink System IP Components

By William Orme, Strategic Marketing Manager, ARM Ltd. and Nick Heaton, Senior Solutions Architect, Cadence

Finding the optimal configuration options that meet the requirements of a particular system requires complementary design tools to enable the designer to rapidly explore and correlate trade-offs in performance, power, and area (PPA). This paper describes the challenges confronting the designer and proposes a new tool leveraging ARM® and Cadence technology to overcome the challenges of today’s highly integrated, multi-processor system-on-chip (SoC) designs.

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