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Tackling Verification Challenges with Interconnect Validation Tool

By Hao Wen and Jianhong Chen, Spreadtrum and Dave Huang, Cadence

An interconnect, also referred to as a bus matrix or fabric, serves as the communication hub of multiple intellectual property (IP) cores inside a system on chip (SoC). As the capacity of today’s SoCs continues to increase dramatically, interconnect verification complexity also grows, considering the master/slave numbers, various protocols, different kinds of transactions, and multi-layered topology. The traditional ways of firing many direct tests, or applying a divide-and-conquer strategy, do not provide a holistic verification for SoC interconnects. A systematic approach must be adopted to tackle the challenge and make the process more efficient. In this paper, we discuss how we adopted Cadence® Verification IP for AMBA® Protocols and Cadence Interconnect Validator, an industry-leading tool for fabric verification. We convey how these tools helped us to improve verification efficiency, and we discuss a verification environment that we created with the Universal Verification Methodology (UVM).

http://www.cadence.com/rl/pages/default.aspx?k=&DA=All&PS=All&RT=White%20Paper

One Response to “Tackling Verification Challenges with Interconnect Validation Tool”

  1. IPad Air; Google Barge; Gary Smith Hospitalized (Great Reads 11-1-2013) - The Fuller View - Cadence Community Says:

    [...] Wen and Jianhong Chen of Spreadtrum and Dave Huang of Cadence, writing in Chip Design Magazine, describe a systematic approach to tackle the challenge and improve verification efficiency. They [...]

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