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Deeper Dive – IPextreme Blows Hot for ColdFire

By Caroline Hayes

There is a shift occurring in the semiconductor market, driven by the consumer space, believes Warren Savage, president and CEO, IPextreme. The IP provider has added the new ColdFire V1 platform to its portfolio. Savage describes the company as product-oriented, whose soft IP can be used with each, successive generation and can serve the ASSP (application specific standard product) or FPGA (field programmable gate array) markets.
To if to illustrate this versatility, this latest configurable platform is available to license now. It consists of a V1 core and pre-integrated subsystem of configurable peripherals. The peripherals can be configured in the platform or out of it and configuration is automatically handled by the company’s IP management platform, Xena.
“The semiconductor market is changing to diversification and specialization” Warren told ChipDesign, explaining the configurable options for the CPU (central processing unit) and the subsystem options. The ColdFire V1 platform has an enhanced MAC (multiple accumulate) engine, an industry-standard AMBA 3 AHB-Lite system bus interface for fast system integration, an improved hardware divider and cryptographic acceleration unit, all of which are optional.
The debug unit is also optional and has a single-wire debug interface and 64-entry trace buffer. HDL parameters can be adjusted so that only the hardware needed for a final implementation needs to be included after tradeoffs have been explored.
Configurability is conducted via the web in a Xena account. Xena was introduced two years ago and manages IP, royalties, export control, contracts, suppliers, device, bugs, tracking, deliverables, access control and support, under one database. There is also a helpdesk, contract terms and supplier management to assist SoC (system on chip) companies building embedded devices.
Developed for the embedded market, the platform implements commonly-required functions, such as interrupt control, DMA (direct memory access), GPIO (general purpose input/output) timers and serial interfaces. An AHB (advanced high performance bus) crossbar switch provides the system interconnect ad supports simultaneous AHB transfers between multiple masters and slaves, including those that are externally connected.
Among the on board peripherals there are several optional components. Savage identifies the industry’s move toward platform based design “as the norm,” explaining that it allows “not only hardware reuse but also to allow software reuse across multiple product lines to get embedded products to market faster”.

An optional RAM controller, supports tightly-coupled RAM random access memory) with a single-cycle access and is available up to 64kbyte. Other options are the ROM (read only memory) controller which can be up to 1024kbyte in size; an optional minibus controller which connector one or two memories or devices, which can be on- or off-chip. This allows for characteristics for each device, for example wait states, address set-up/ hold, data width and the choice of multiplexed or non-multiplexed mode. Also option is the DMA controller, the queued SPI (serial peripheral interface) module, which allows users to program a queue of up to 16 SPI transfers apt o nd to program baud rate before and after transfer delays, clock phase and polarity. Other options are the I2C interface module, supporting up to 3.4Mbit/s baud rates; up to three UARTs (universal asynchronous receiver/transmitters) and up to four DMA timer modules. Standard peripherals are the interrupt controller, which supports up to 30 peripheral interrupt requests and seven interrupt requests, and also supports low power mode wake-up. Also standard is the platform control, including a software watchdog timer, reset status, low-power control and core fault status registers.

Software controlled shutdown of specific clocks can support low power modes, by independent shutdown of peripheral clocks or shutdown of the CPU clock.

Debug support is available with a single-wire background debug mode interface, real-time debug and on-chip, 64-entry trace buffer.

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