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Research Review Nov.13

By Caroline Hayes, Senior Editor

Polymers snap to it, when triggered by light; algorithmic memory is developed for ASICs and SoCs; UDP/IP engines target Stratix V and Virtex 7 FPGAs and supercapacitors stretch their limits.

Maybe not faster than a beam of light, but influenced by it, researchers at the University of Pittsburgh Swanson School of Engineering found polymers that snap when triggered by a beam of light, converting light energy into mechanical action. It is like a venus fly trap, mused M Ravi Shankar, associate professor of industrial engineering, who conducted the research in collaboration with Timothy J White, Air Force Research Laboratory at Wright-Patteson Air Force Base and Matthew Smith, assistant professor; of engineering at Hope College, Holland, Michigan. (Early Edition of the Proceedings of the National Academy of Sciences – PNAS). Just as the underlying mechanism of a venus fly trap is slow, the unsuspecting prey is caught because it uses elastic instability, which snaps the trap shut – tight. The project examined polymeric materials’ actuation rates and output. A handheld laser provided the light for the polymers to generate power to convert the light into a mechanical action without a power source or wiring. Specific functions were pre-programmed into the material for it to be controlled by changing the character of the light. The technology could eliminate traditional machine components, and, speculates Dr Shankar, also develop biomedical devices that are adaptive and easily controlled.

STMicroelectronics and Memoir Systems have collaborated to create Algorithmic Memory Technology for embedded memories.
Integrated into ASICs (application-specific integrated circuits) and SoCs (systems on chips) manufactured in the former’s FD-SOI (fully-depleted silicon-on-insulator) process technology, they are able to exploit the process’ power and performance advantages and combine low soft error rate and ultra-low leakage currents, claims the company. This makes the memories particularly suitable for mission-critical applications, such as transportation, medical, and aerospace programs. Soft error rate is 50 to 100 times better than equivalent bulk technology, measured below 10FIT/Mbit (Failure-in-Time or failures per billion-chip hours). Devices produced in FD-SOI are also found to produce as much as 30% faster performance and as much as 30% greater energy efficiency when compared with the same products manufactured in bulk technology.
According to STMicroelectronics, FD-SOI process technology produces ASICs and SoCs that run faster and cooler than devices built from alternative process technologies, Adding third-party IP (intellectual property) from Memoir Systems demonstrates how simple porting is, says the company.
The European semiconductor supplier is the first to make FD-SOI process technology available. It extends and simplifies existing planar, bulk-silicon manufacturing; an FD-SOI transistor operates at higher frequencies than equivalent transistor manufactured using bulk CMOS because of improved transistor electrostatic characteristics and a shorter channel length, says the company.

Second-generation UDP/IP (user datagram protocol/internet protocol) off-load engines were demonstrated at the Low Latency Summit, NY, New York.
Digital Blocks, released the DB-UDP=IP-HFT IP core hardware stack / UDP Off-Load Engine (UOE) targeting Altera Stratix V and Xilinx Virtex 7 FPGAs on network adapter cards with one or more 10 / 40Gbit Ethernet network links. The engine targets trading systems with sub-microsecond packet transfers between network wire and host. The embedded DMAC (direct memory access controller) controls low-latency, parallel packet payload transfers between memory and the company’s UP/IP packet engines in, for example financial trading companies.

Researchers at the University of Delaware have developed a compact, stretchable, wire-shaped supercapacitor, based on continuous carbon nanotube fibers. Wire-shaped supercapacitors could use the advantages of recharging in seconds, a longer life span than conventional batteries and high reliability and robust storage, in wearable devices.
University of Delaware professors Tsu-Wei Chou and Bingqing Wei have developed the supercapacitor using prestraining-then-buckling to fabricate the wire-shaped supercapacitor using a Spandex fiber as the substrate, a polyvinyl alcohol-sulfuric acid gel as the solid electrolyte, and carbon nanotube fibers as the active electrodes.
When subjected to a tensile strain of 100% over 10,000 charge/discharge cycles, the carbon nanotube supercapacitor’s electrochemical performance improved to 108%, demonstrating its electrochemical stability.
Wei, explains that the network of individual carbon nanotubes and their bundles endow the fibers with the capacity to withstand large deformation without sacrificing electrical conductivity or mechanical and electrochemical properties.
The professors published their findings in Advanced Energy Materials. UD’s Tsu-Wei

Pictured: Tsu-Wei Chou (left) with visiting scholar, and first author on the report, Ping Xu. Photo – Ambre Alexander

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2 Responses to “Research Review Nov.13”

  1. Edward Thornton Says:

    Could you identify the author? It’s tough to understand if a Chip Design writer wrote this or a vendor wrote this. If a vendor, then was it pure editorial or was it a pay for play piece?

  2. jb Says:

    Hi Ed. This is an odd question. I thought you knew that all of the content on our “System Level Design” portal was written or developed by the editors. The daily stories, like research and news reviews, are a compilation of content from other sites which the editor filters and shapes. The feature stories, roundtables, videos and all the rest are written completely by the journalists.

    If you’re interested in contributing a well-written piece from one of your clients, then it’s best to contact me for a Chip Design magazine placement. Cheers. — John

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