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Deeper Dive – Dec. 05

By Caroline Hayes, Senior Editor

The twists and turns of FinFET

In an earlier Deeper Dive (Nov. 21) we looked at how TSMC’s 16nm FinFET reference design was encouraging harmony among teams, as they work together to verify designs and accommodate the three dimensional transistor structure. In this edition, members of the design community are asked about new challenges 16nm FinFET raises, such as double patterning and IP validation.

There are three key challenges for EDA tools, posed by 16nm FinFET, says Cadence’s Steve Carlson, director of marketing. Talking about the increased net resistance of wire delays, he is despondent, saying “Wire delays have been dominated by increased net resistance, and at 16nm, it’s only getting exponentially worse,” he begins. There are also new challenges, he continues, identifying pin access as a new critical design closure metric. There is a conundrum in the solution. “Double patterning techniques, critical to ultra-deep submicron fabrication – are leveraged to get the maximum possible density of tracks in lower metal layers,” he reasons, “But this makes it harder to undertake graceful via spacing and via cuts.”

On the extraction front, the challenges are to extend FinFET RC parasitic models to be closer to those extracted using a field solver, he continues, but the list does not end there. He also points out the analog waveform effects, due to extremely low VDD can cause problems for designers to achieve accurate timing and design closure. “There are new challenges for physical design and verification due to double patterning,” he adds, warming to the theme. He warns that the number of design rules are “exploding exponentially, as well as the number of parasitics”. For layout designers and manufacturing engineers this causes problems regarding DFM (design for manufacturing). He explains “Double patterning and FinFET devices affect several areas of signoff, including extracting, DFM and timing. It requires additional DFM lithography checks and planarization checks,” he concludes.

The list of challenges may be formidable, but it is not all downbeat. Carlson went on to explain how designers are adapting techniques, being inventive and benefitting from a choice of options to meet them.

First, the wire delays. In upper metal layers the wire delays can be up to 10 times less than those on the lower layers, which means that there is a significant timing gain from routing long or critical nets on the upper layers. A menu of wire thicknesses allows designers to pick the optimum thickness depending on where they are in the metal stack. “However,” warns Carlson, “there are limited routing resources on these upper metal layers, due to the presence of power or signal nets”. This can potentially cause congestion and possible routing issues if they are not dealt with.

Turning to pin access, the problem is that to via down to one pin can create a halo effect that locks pin access to the neighboring pin, he explains, making it extremely difficult to get the design to route. “The congestion can be low, but if your local pin density gets out of hand, the design won’t close, it won’t route. As a result, careful control of pin densities during cell placement, and global pin-access planning during detail routing can have a big impact on achievable design area.”
Other problem solving examples are to extend 2.5D models to be almost 2.9 “to be as accurate as a field solver,” says Carlson “and to keep runtime as low as possible compared to 28nm designs.” Bringing the RC of the FinFET into the designer’s platform as early as possible is also a sound measure, as RCs have twice the impact on delay at 16nm as they do at 20nm.

Double patterning is also touched on by Mentor’s Arvind Narayanan, product marketing manager Place & Route division. It is, he says a part of any design using FinFETs at 20nm or below. There are, he says extensive place and route layout restrictions at every stage of the flow, including placement, routing and optimization. “There are extensive place and route layout rules that tools must honor,” he says, naming fin grid alignment for standard cells and macros during placement, Vt min-area spacing rules, continuous OD rules and source-drain abutment rules. “These spacing rules are imposed by the process requirements and directly impact the placement and optimization engines in the router.” Naturally, the place and route extraction engine must be able to accurately model the 3D parasitic requirements of FinFETs but, warns Narayanan, implementation tools should be able to adhere to these additional constrains – without sacrificing power, performance or area.

The more complex FinFET structures need updated tools that are able to support more complex design rules than might be required for planar transistors. They require, for example, higher accuracy for reliable simulation and verification. He also notes that designers are finding the need to perform extraction at more corners, which prompts the demand for faster extraction processing.

“The interplay between local IPs and double patterning, pin access and noise, all become more complex at 16nm,” says Carlson. In addition to the expected increased complexities at each new node, IP validation is more sensitive to context. “Formerly, each EDA tool ran through a qualification suite and that was the end of the story.” The qualification tests have become more elaborate but EDA tools cannot be validated one at a time, he insists. “They must be validated in the context of a flow, but they must also be validated on a flow that is applied to a complex design that is representative of the first designs that will be going into production on the new process.”

Narayanan identifies that a new set of design rules has been written for 16nm FinFET “and some of these rules required new types of measurements and analysis by the physical design and verification tools, he says.

He recalls that once TSMC defined the initial set of design rules, it created a regression test suite to validate that physical verification decks produce the expected results, both at initial release and over time. “This test suite was developed by iteratively creating test chips, running the design rules against test chips, observing results, identifying and analyzing errors and updating the design rules until [TSMC] determined that the flow was acceptable for initial production”. It was down to EDA companies to extend tool capabilities to meet new measurement and analysis requirements.

Initially, the foundry focused on accuracy, he reveals, and Mentor collaborated, bringing
Experience of optimizing rules and techniques on achieving accurate results in the fastest possible time, with the smallest memory requirements, he says. He says that the collaboration for optimization for the 16nm node is “progressing even faster than 20nm, in spite of the added complexity that 16nm presents”.

The industry is working hard to create tools to develop 16nm designs – but for what end? Carlson makes an interesting point, saying that looking at enablement of 16nm FinFET also means looking at the expense that the overall ecosystem must bear to being a new process node into production (see illustration: source IBS May 2011). He refers to costs beyond building a facility, citing the process R&D cost for the node and ‘enablement collateral’. Aside for the bricks and mortar costs, he says “Fabless companies creating new SoC platforms face tremendous design costs (including masks).” He says that the implication has to be that rising design costs is that advanced nodes will be used for high margin, or very high volume, products.”

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