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Communication Algorithms Challenge EDA

By Gabe Moretti, Contributing Editor

EDA tools have evolved to support the rapid development of new communication algorithms and other improvements in the connected market.

The explosion in communication products that have made possible portable communication and computing devices has required significant efforts in the development of new algorithms and recurring improvements in modems and other transmitting and receiving hardware.  The evolution of EDA tools that have and are supporting such innovations is relatively short but quite interesting.

Segment Specific Products

According to Dr. Johannes Stahl Director, Product Marketing, System-Level Solutions at Synopsys there is one dominant vendor in the market, Mathworks. They offer MATLAB which is used in a very specific phase of algorithm design, namely the early exploration phase.  The company describes the tool as follows: “MATLAB is a high-level language and interactive environment for numerical computation, visualization, and programming. Using MATLAB, you can analyze data, develop algorithms, and create models and applications. The language, tools, and built-in math functions enable you to explore multiple approaches and reach a solution faster than with spreadsheets or traditional programming languages, such as C/C++ or Java.”

Although MATLAB is a powerful modeling environment once the algorithm development is done developers must use a commercial tool from other vendors, like Cadence, Mentor or Synopsys to integrate it into the complete chip development stream. MATLAB is a proprietary language and thus engineers can only use it under license.  As is the custom of many EDA vendors, Mathworks requires an interested individual to create an account on their website in order to see the pricing structure.

Johannes Stahl continued: “Today, there are basically three significant tools in the market: Simulink from Mathworks, or one can choose between two tools from Synopsys: SPW or System Studio. I think the reason there are not more vendors in this market is that many designers decide to use their own proprietary solution especially if their management does not ask for a commercially supported flow. Algorithm designers are far enough away from the risk of implementation in either software or hardware that management sometimes is not too concerned about which tools they are using. However, for high risk SoC projects we see this changing again. While 10-15 years ago it was the risk of hardware design that drove algorithm designers to consider commercial tools, today we see the risk of multicore software implementation as the cause for design teams to connect algorithm design with the implementation team. So instead of the hardware implementation risk, the software implementation risk is the driver to force the choice of a more standard solution.”

I asked Johannes the reason for two tools from Synopsys in such narrow market.  He responded: “The difference is really not that big. All of these model-based tools have a  and proprietary data base that is used to describe the system and a proprietary C/C++-based  modeling style.  is very difficult, in fact , to transfer a design representation from one to the other. For any commercial tool in the market, the choice tends to be very sticky and becomes even more so as the algorithmic model develops over time. We have customers that have used the same models for more than 20 years. Hence, algorithm developers that are familiar with tool are very reticent to change.   Synopsys decided to keep both tools in the market.”

Cadence developed SPW as a competitor to MATLAB, but chose to target only very large projects, like the Iridium satellite network for example.  SPW provides a path to implementation for digital signal processing systems. At its core is the C data flow (CDF) modeling paradigm which enables an efficient description of digital signal processing algorithms which may be implemented in dedicated digital hardware or embedded software. CDF is a way of describing parallel systems to produce a fully deterministic execution schedule, critical for the design of heterogeneous, multi-core architectures.  After a few years competing indirectly with MATLAB and directly with System Studio from Synopsys, Cadence sold SPW to Coware which, in turn, was acquired by Synopsys in 2010.

The role of C and C++

With the introduction of SystemC and later its standardization first by OSCI (now part of Accellera Systems Initiative) and the IEEE, synthesis tools accepting C or one of its dialects as input were quickly developed by EDA vendors.  Until then, to my knowledge, only Bell Labs used a C synthesis flow for its hardware development, while today the use of C for algorithm modeling is quite common.

When SystemC was proposed as a hardware description language it not only provided a way for hardware and software engineers to use the same language for modeling, which was its intent, but established a new market.  EDA tools providers had explored, with little success if any, behavioral synthesis in the past.  The problems inherent in the approach before SystemC were input languages that required knowledge of abstract algebra, and a discontinuity in connecting the results of the synthesis to existing design flows.  SystemC fixed both problems and opened the possibility of using C and C++, augmented with appropriate classes, to model hardware. Both Cadence and Mentor were quick to realize that a C based methodology was sufficient and appropriate for algorithm development.

By taking advantage of C-to-Silicon Compiler capabilities, Cadence’s customers can integrate an algorithm design into a flow that spans from system verification to silicon generation.  Built on top of anchor platforms from Cadence, Incisive simulation and Palladium acceleration and emulation, the System Development Suite also spans technologies such as virtual prototyping, formal and semi-formal verification, verification IP (VIP), FPGA-based prototyping, verification planning and management, debug analysis, mixed signal verification, power verification and analysis, performance analysis, and others.

Mentor has integrated all of the various functions of system level design, including algorithm development and exploration within its Vista environment.  Vista is an integrated TLM 2.0-based solution for architectural design exploration, verification, and virtual prototyping. Vista enables system architects and SoC designers to make viable architecture decisions, and it allows hardware and software engineers to validate their hardware and software early in the design cycle.

Forte Design Systems offers two products that allow designers to generate RTL from C based models.  Cynthesizer, Forte’s original product now in its fifth version, is a high level synthesis tool.  Cynthesizer 5 includes ideas and experience from more than a decade of production SystemC high-level synthesis deployment. With Cynthesizer 5, design teams can quickly create RTL implementations from abstract SystemC models. The SystemC models can be created using the new Cynthesizer Workbench SystemC IDE, retargeted to new technology platforms, and reused more easily than traditional hand coded RTL. Cynthesizer 5 will also allow designers to make tradeoffs to power in addition to area and performance within the high-level synthesis environment.

Although technically speaking there are a number of languages that can be used for algorithm development, including VHDL by the way, the use of C and its dialects is now established to the point that alternatives would have to offer significant improvements in efficiency and reliability to slow the growth of this market segment.


EDA vendors compete in a market that is well regulated by standards.  The IEEE is the organization that in most cases develops, maintains, and distributes EDA standards together with standards that cover all aspects of electrical and electronics applications.  Two industry organizations, Accellera Systems Initiative and Si2 also develop standards, with Accellera Systems Initiative enjoying a significant leadership in providing seed standards to the IEEE over Si2.  In the case of SystemC, Accellera and OSCI (Open SystemC Initiative) worked together to release the first SystemC standard.  In 2011 the IEEE released its own standard for SystemC, IEEE Standard 1666, fundamentally institutionalizing the work done by Accellera and OSCI which is now been merged with Accellera to form Accellera Systems Initiative.

Accellera Systems Initiative has strengthened the C development environment by producing two related activities.  One is the TLM (Transaction Level Modeling) Working Group.  This group is responsible for the definition and development of methodology and add-on libraries for transaction-level modeling in SystemC.  Transaction-level modeling (TLM) continues to grow in importance for architectural exploration, performance analysis, building virtual platforms for software development, and functional verification. Since its release, TLM has become the industry standard for creating interoperable transaction-level models. It provides a synergistic and comprehensive solution that supports loosely-timed and approximately-timed transaction-level modeling.

A TLM model of a communication block is the most efficient method to verify the functionality of a newly created algorithm.

The SystemC Verification Working Group (VWG) is responsible for defining verification extensions to the SystemC language standard, as well as enriching the SystemC reference implementation by offering an add-on SystemC Verification (SCV) library to ease the deployment of a verification methodology based on SystemC.  On June 20, 2013, the SystemC Verification Working Group began a 90-day public review of the SystemC Verification Library 2.0, an update to SCV 1.0p2. This release contains an implementation of the verification extensions for Accellera Systems Initiative SystemC 2.3.0 and Accellera SystemC 2.2.0 and is compatible with IEEE 1666.

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