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Deeper Dive – 3D-IC Part 1 Fri. July 11 2014

A 3D-IC round table – part I

As the industry transitions from 2.5D to 3D-ICs, Caroline Hayes, senior editor, asked experts from Mentor Graphics, Altera and Synopsys for their view on what system designers need to consider in implementing 3D ICs.

The round table is made up of John Ferguson (JF), Director of Marketing, Calibre DRC Applications Design to Silicon Division, Mentor Graphics; John Park (JP), Business Development Manager and Methodology Architect, System Design Division, Mentor Graphics, Steve Pateras (SP), Product Marketing Director, Silicon Test Products Mentor Graphics, Michael White (MW), Director of Product Marketing Calibre Physical Verification Mentor Graphics, Arif Rahman (AR), Program Director and Architect, Altera Corporation, and Marco Casale-Rossi (MCR), Senior Staff Product Marketing Manager, Design Group, Synopsys.

The advantages of 3D-IC are obvious, but there are challenges (e.g. thermal management). What are these in your view, and how does your company address these?
[JF:] There are many. The biggest issue towards large-scale adoption, at least as I see it, is trust/risk. When you do an SoC today, there is an explicit agreement in place with the foundry, and with that foundry’s blessed IP partners, that if you follow their design rules, you get reasonable manufacturing yield. With 3D, we’re talking about components from multiple processes, potentially from different foundries. When you put them all together, there is no longer anyone guaranteeing your success. It is your skin on the line. As such, it is a very risky proposition. It won’t get huge traction until/unless more designers take the risk and not only show successful design, but demonstrate that by taking such risk, they are able to implement a design that is significantly better than alternative technologies. If the value proposition is only pricing, it is a tough sell. You can always find other places to cut costs and corners in an SoC without the same level of risk.
[JF:] For technical challenges, at least for verification and extraction perspective, the biggest issue is that when you stack dies, you can no longer imply vertical alignment and physical connection by GDSII layer numbers. You have to distinguish each die placement to keep these layers independent. No small task.
[JP:] A big challenge is reliability, which includes thermal stress management. Mentor’s FloTHERM product coupled with stress analysis capabilities will play a critical role in this space. Path finding tools that allow design teams to make quick trade-offs against different packaging technologies to optimize cost, form factor and performance are also required. Mentor’s newly announced Xpedition(tm) Path Finder can play a role here.
[MW] There are both technical and business challenges. Technical challenges include thermal management is clearly one that early adopters are concerned about. Chip/package/TSV stress and the impact of this new packaging on electrical performance is another area of concern. Obviously physical verification (e.g. DRC, LVS) of the assembly and parasitic extraction of key nets are also a challenge with this new packaging approach. Mentor has put in place solutions for all these aspects. Most are already in production use for 2.5D or 3D assemblies.
On the business side, the industry has seen adoption of 3D for select IC segments, (e.g. image sensors, memory) where there are truly compelling performance reasons to do so. Other IC applications are still in their infancy determining for what subset of their IC designs is there a compelling reason to move towards 2.5D/3D-IC.
[AR] Thermal management, creation of high aspect ratio high density TSV, and test/KGD are some of the challenges for 3D integration. We work closely with our manufacturing partners, research institutes, and universities on research and development projects targeted to these areas .
[MCR] 3D-IC is currently in volume production at memory makers: their vertical integration and, from a technical viewpoint, the relatively low numbers of TSV and their patterning regularity make it much easier to implement memories in this process. There are still challenges with respect to extraction, physical verification and place and route (P&R), etc. To address these challenges Synopsys has developed specialized P&R and parasitic extraction capabilities to account for TSV within a die; we have developed a specialized interposer router for RDL; our LVS/DRC supports multi-die and multi-technology checks; we have developed a unique multi-technology circuit simulation capability; our 2.5D- and 3D-IC flows have been certified by silicon foundries such as TSMC, and GlobalFoundries; and we have collaborative research initiatives on-going with IMEC, Applied Materials, and IME (Singapore) and more.

Is there still a place for 2.5D packaging? Where would it be used over 3D-IC?
[JF:] Yes. Consider the Xilinx case. Their issue is that to enable very large designs they are forced to go beyond the full reticle size. They get around this by breaking the FPGA into two dies and placing them side by side on an interposer. It works well in their space because they have very regular designs. I don’t see that approach going away for them.
[JP:] For many applications, 2.5D is the road to full 3D-IC. We would expect for the next decade or more, 2.5D will be the driver and bridge to full 3D-IC. At this point, the reason to proceed with 2.5D over full 3D-IC is primarily thermal and design flexibility. IBM after a long study concluded that for thermal and stress reason they have to proceed with 2.5D.
[AR] Just to be clear we use the term 2.5D to define passive silicon interposer based side by side integration and 3D to define stacking of two or more active device layers with TSV.
We believe both 2.5D- and 3D-IC will co-exist. Thermally limited applications with high-bandwidth chip-to-chip interfaces will most likely prefer 2.5 D integration over 3D integration. Applications requiring integration of multiple heterogeneous die (logic & memory; logic and mixed signal) may deploy 2.5D integration as well.
[MCR] 2.5D-IC is a more evolutionary approach than 3D-IC, and is a viable solution when the footprint is not the primary concern. For example, silicon interposers, manufactured at 65nm, offer one to two orders of magnitude of connectivity compared to TSV and, of course, they are useful for boards.

Part 2 of this round table, where the panel considers means to accelerate adoption of 3D-ICs, will be published July 17.

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