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Deeper Dive – A 3D-IC round table – part II

What’s needed for 3D-ICs to flourish? asks Caroline Hayes, senior editor. Experts from Mentor Graphics, Altera and Synopsys have some ideas for future progress.

The round table is made up of John Ferguson (JF), Director of Marketing, Calibre DRC Applications Design to Silicon Division, Mentor Graphics; John Park (JP), Business Development Manager and Methodology Architect, System Design Division, Mentor Graphics, Steve Pateras (SP), Product Marketing Director, Silicon Test Products Mentor Graphics, Michael White (MW), Director of Product Marketing Calibre Physical Verification Mentor Graphics, Arif Rahman (AR), Program Director and Architect, Altera Corporation, and Marco Casale-Rossi (MCR), Senior Staff Product Marketing Manager, Design Group, Synopsys.

What is the scale of 3D IC adoption/use, for example in 20 or 14nm. What can accelerate adoption?
[JF:] I am just starting to see some 20nm 3D designs. Most 3D designs I’ve seen are focused on more mature nodes: 45, 65, etc.
[JP:] 3D-IC is still at the R&D stage in both academia and the semiconductor industry, the exception being the memory providers. At the 20/14nm nodes, scaling Analog/RF blocks may not be practical, so being able to partition the device into multiple chips across a silicon interposer starts to make a lot of sense. However, issues such as Known Good Dies, assembly and supply chain challenges, including IP’s need to be overcome.
[AR] So far, we see very limited deployment of 3D IC in 20nm and 14nm technologies. Memory vendors appear to be taking the lead to deploy 3D IC technology in 20-ish nm process technology to create high bandwidth and high-capacity memory. JEDEC HBM and Micron’s HMC are two of the early adopters.
[MCR] Memory and FPGA makers are the early adopters. It enables design-level integration for digital + analogue & mixed-signal; and is a good option for ‘More than Moore’ integration which includes integration of electronics + microelectro-mechanics + photonics

What has to come first – availability of the 3D IC process, so that EDA tools can be developed, or tool flows so that foundries can produce 3D ICs economically?
[JF:] It is a chicken and egg situation. EDA doesn’t want to invest in the tools until they know there is a real design market, which implies a foundry process. Foundries don’t want to invest in a process unless there is a design market and EDA tools. Designers don’t want to take the risk without a fully supported flow from a foundry, implying EDA tools in place. The initial work has been done by those market niches which can immediately benefit. They take on the risk and have been working to push those EDA and foundry providers that are willing to share the risk. Issues identified get fixed. Successes get published and begin to establish legitimacy.
[JP:] This will require collaboration between both sides with tools and flows being developed simultaneously.
[SP:] 3D DFT related tools are essentially independent of the 3D IC process and can therefore be developed independently. Mentor already offers a commercial 3D memory BIST solution and has also developed a comprehensive 3D logic test solution that is already part of TSMC’s 3D reference flow.
[AR] EDA tool readiness is not a real show stopper to 3D technology adoption. We believe existing tools and design methodologies can be extended easily to enable 3D IC design.
[MCR] Synopsys collaborated with the foundries to enable development and adoption of 3D-IC processes. It’s not a question of one waiting for the other, but working together to make 3D-IC a reality. Synopsys has made several announcements with TSMC and other partners regarding our 3D-IC collaboration.

What standards would you like to see in place, to regulate interconnect, test for example, for 3D IC?
[JF:] This is a tricky space. Some come at it from an IC perspective, while others come at it from a packaging or board level perspective. Each has its own set of internal standards, but there is really nothing that easily crosses them all. If we focus each tool/standard in the right domain (i.e. design the IC’s with IC based tools, design boards with board tools, etc.) then we just need to make sure that all those components come together correctly. What format will be used for that will largely depend on the process being implemented to combine it all together.
[SP:] The most critical aspect of testing devices within a 3D stack is gaining access to the devices in the middle of the stack. This requires a test access architecture that is shared among all devices in the stack. Since devices will likely originate from different vendors it becomes necessary therefore to have in place an industry standard test access architecture that can adopted by all device developers. The IEEE 1838 working group is currently developing this needed standard.
[MCW:] Yes, the movement to full 3D with >2 stacked dies does bring along the need to deal with thermal, stress, etc. to a far greater degree than is required with 2.5D. For some customers and applications, 2.5D will be an easier and more attractive alternative to vertical stacking for some time. One particular thing that would make 2.5D or other side by side approaches like wafer fan out more interesting is reducing the cost of the medium being used at the interposer. Multiple foundry ecosystems and packaging houses are exploring lower cost solutions to make 2.5D cost effective to more applications.
[MCR] Synopsys is playing a critical role in defining and driving relevant standards. A Principal Engineer from Synopsys is the vice-chair for P1838 working group in IEEE. The charter of this group is to define standardised test access for 3D-IC.
[AR] Test/KGD methodology and interface standard for chip-to-chip communications.
Different types of devices in a 3D stack need to communicate with each other and these devices are expected to be procured from different companies and will be fabricated in different process nodes. There is a need for common low-power and scalable (ability to scale to higher bandwidth) interface standard to enable heterogeneous integration of 3D systems. This interface standard should define physical, electrical, logical, and test requirements.

What opportunities do you see 3D IC will bring for designs in the next five to 10 years (e.g applied to lower geometries; opportunities for new applications, e.g. mobile healthcare use)?
[JF:] Silicon photonics is gaining interest right now for its promise of very low power for use in large scale process compute farms (i.e. cloud computing). Unlike IC design, photonics does not benefit from a shrink. The geometric widths are dictated by the wave lengths of light being used, which are typically much greater than the smallest features available in today’s nanometer processes. So, there is a lot of speculation that designers who wish to combine photonics with advanced IC electronics will do so in a 2.5D or 3D infrastructure, for example adding photonic circuitry into interposers at larger process nodes, while keeping the electronics on advanced processes stacked on the interposer itself.
[MCR] The opportunities are amazing: If we are able to assemble parts from different sources, manufactured using disparate technology nodes, adding MEMS and silicon photonics into the picture, it would lead to a revolution in automotive, computing, healthcare, mobile, networking. For example, a component small enough could be injected in the human body to test something (MEMS sensors), compute (CPU/MCU), transmit (RF) and/or store (FLASH) the results onboard, and dispense (MEMS actuators) the appropriate amount of a medication…the imagination is the only limit.
[AR] Extreme miniaturization of a complete system, which includes sensing, processing, and communication functions, into a very small form factor may require the use of 3D IC technologies. Such systems can facilitate new applications in healthcare (wearable electronics/personalized monitoring, implanted drug delivery devices), environmental monitoring, and imaging.
2.5D/3D integration of optical and electrical components can enable broader deployment of integrated optical interconnect technologies for short-reach communication.

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