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Deeper Dive-Imagination promises a game-changer for multi-core design

In a recent announcement, Imagination Technologies introduced the first IP cores to combine a 64bit architecture and hardware virtualization with scalable performance through multi-threading, multi-core and multi-cluster coherent processing.
By Caroline Hayes, Senior Editor.

Mark Throndson, Director Business Development, Imagination Technologies, told EE Catalog that the MIPS I-class I6400 CPU addresses automotive, embedded, DTV/set top box, mobile and enterprise applications.

They are the first IP cores to combine a 64bit architecture and hardware virtualization with scalable performance through multi-threading, multi-core and multi-cluster coherent processing. This means, explains Throndson, that engineers can implement a smaller core at the same performance, or a faster core in the same area to meet the demands of mobile computing or performance-demanding data center servers.

This is the third announcement for the MIPS Warrior family from the company, but it is not an evolution, says Thordson. “This is the first 64bit MIPS core, and it has new features and new capabilities,” he says, leaving us in no doubt.

This is the sixth release of the architecture and the resulting core supports simultaneous multi-threading – up to four hardware threads per core – to increase performance, and 32MIPS code. As such MIPS r6’s new instructions are claimed to enhance the performance on JIT compile technologies, JavaScript, browsers, PIC (position independent code) for Android, running on MIPS32 architecture without requiring separate ISAs, datapaths or mode switching, says Throndson, eliminating wasted silicon area and power.

Jim McGregor, founder and principal analyst, Tirias Research: “To address the ongoing evolution in applications from IoT to mobile to networking and storage, companies need to select scalable platforms that can future-proof their designs. With 64bit, multi-threading, and multi-core/multi-cluster support, the I6400 is designed to be a flexible, low-power processor architecture capable of scaling across a wide range of applications. Imagination now has MIPS IP cores for everything from microcontrollers to 64bit servers, delivering choice across the range and changing the competitive dynamic in the industry.”

Early access releases are available now, and customers are expected to realize more than 50% higher CoreMark performance and 30% higher DMIPS compared to leading competitors in its class (based on preliminary benchmark results).

The simultaneous multi-threading enables execution of multiple instructions from multiple threads every clock cycle. Preliminary benchmarking shows that adding a second thread leads to performance increases of 40 to 50% on popular industry benchmarks including SPECint and EEMBC’s CoreMark, with less than a 10% cluster area increase.

Like existing MIPS Warrior cores, the hardware virtualization technology adds security throughout the system and across the SoC. There is support for up to 15 secure/non-secure guests as well as the ability to support multiple independent security contexts and multiple independent execution domains. It can be scaled to support secure content delivery, secure payments and identity protection across multiple applications and multiple content sources.
Targetting mobile devices, the cores use advanced power management with PowerGearing for MIPS. A dedicated clock and voltage level can be provided to each core in a heterogeneous cluster, while maintaining coherency across multiple CPUs to ensure that only sleeping core wake when needed, without expending energy on others.

Another feature is the floating point unit which supports both single and double precision capabilities for general computing or control systems processing.

There is also support for a 128bit SIMD support, to boost performance and throughput using SIMD execution in data-parallel applications. It supports 8-, 16-, 32- and 64bit integer and 32- and 64bit floating point data types, for audio, video, vision, and other compute-intense tasks, across the spectrum of applications sectors.

The core is built on the MIPS SIMD RISC architecture, with instructions supported within C or OpenCL, although also to leverage existing code, if this is appropriate.

MIPS Coherency Manager fabric (Figure 1) is based on a multi-core coherent interconnect architecture and is able to support multi-core configurations of up to six cores per cluster. This is particularly useful where cores on one cluster can have different synthesis targets, and operate at different clock frequencies and voltages. For optimum performance, the fabric implements hardware pre-fetching, which combined with wider buses and lower latencies compared to previous generations.

The ecosystem includes software, tools and applications and the new prpl open source foundation. This an open source software for MIPS I-class and Warrier cores, founded by Broadcom, Cavium, Ikanos, Ineda Systems, Ingenic Semiconductor, Lantiq, PMC and Qualcomm, among other. The software is focused on the IoT and data center applications.
One of the first projects completed through the prpl open source foundation is support for the MIPS64 r6 architecture in the QEMU open source emulator, currently available at

Early access releases are available now, with production RTL and general availability scheduled for December.

September 11, 2014

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