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ASIC Prototypes Take the Express Lane for Faster System Validation

Troy Scott, Product Marketing Manager, Synopsys Inc.
Demand for earlier availability of ASIC prototypes during a SoC design project is increasing because of the effort and cost to develop software drivers, firmware, and applications. Industry surveys show that design teams now spend up to 50% of engineering budget on software development. This urgency is pushing commercial vendors of FPGA-based prototypes to field products that can demonstrate improved productivity for the engineers that are responsible for hardware/software integration and system validation. In this article we’ll examine the state-of-the-art in FPGA-based prototyping tools and the benefits they deliver.

Design teams that have adopted commercial FPGA-based prototyping systems versus custom built or adapting FPGA evaluation boards typically do so to stretch the investment dollars over multiple  chip designs. Commercial systems tend to be modular and flexible, by stacking or tiling FPGA modules, so that capacity can be scaled up or down for a project’s resource demand and interface peripheral boards featuring interface PHYs can be selectively assembled around FPGA modules. The best commercial systems provide embedded system control elements for rapid programming, FPGA module chaining, clock and reset distribution, heat mitigation, and fault monitoring. All of which contribute to reliability and uptime that is superior to custom-built systems.

One of the major tasks of a physical prototype project is to map ASIC RTL and IP into the hardware resources of an FPGA which, in comparison to an ASIC design, provides a limited number of low-skew clock trees and dedicated memory resources. Replacement and substitution can be a time consuming effort to make the RTL “FPGA-friendly.” This is where FPGA logic synthesis tailored for FPGA-based prototypes helps speed the conversion task.  Synopsys’s ProtoCompiler, design and debug automation tool, provides two clock conversion techniques for the Synopsys HAPS Series. The first called HAPS clock optimization (HCO) is typically applied very early in the bring-up phase when it’s urgent to get the design operational quickly on the live hardware. HCO automatically chooses a master synchronizing clock and all registered elements are synchronized to it. The conversion is quick and easy since it does not depend on careful identification of clock and data signals or constraints by the prototype developer. When higher performance or asynchronous relationships must be modeled then ProtoCompiler provides advanced clock conversion that logically separates the gating from the clock and routes the gating to the dedicated FPGA clock to enable inputs of sequential elements. Separating the gating from the clock allows a single global clock tree to be used for all gated clocks that reference the same base clock.

The Verilog HDL language in the context of a prototyping flow can help address module replacement or exclusion of non-logic elements of the ASIC design. In ProtoCompiler’s design flow for HAPS, the Verilog Force replaces existing driver of internal signals in the hierarchy with new drivers and Verilog Bind inserts a module instance into the design hierarchy. These constructs are ideal for substituting circuitry, changing a clock tree, or to stub out part of an ASIC design that is not needed in the FPGA prototype. The commands when collected into a new file will override the RTL of the design which allows the prototype engineer to make surgical changes to the logic without touching the “golden” source of the RTL drop.

Another significant trend in the physical prototyping space is for vendors to deliver prototypes integrated with a CPU software development platform. These combinations are a popular architecture for hardware/software integration scenarios and ideal for software-driven testing and driver development.  The reprogrammable FPGA allows for testing of various IP configurations, connecting to analog PHYs implemented on test ICs, and clock, reset, and power management circuit integration between control and PHY.

Figure 1 illustrates a commercial implementation of an FPGA-based prototype with a CPU subsystem. The Synopsys DesignWare IP Prototyping Kits take this integration paradigm even further by pre-packaging various IP subsystems from the DesignWare IP catalog with reference drivers and example application running on Linux OS. The kits feature popular interfaces like USB, PCIe, and MIPI and can be assembled, powered on, and running within a few minutes making them ideal for rapid delivery to software developers.

Figure 2. Synopsys DesignWare IP Prototyping Kit Architecture

The demand for shorter bring-up schedules and more efficient work flows are driving innovations by commercial providers of FPGA-based prototyping tools. Many of the benefits come from the co-design of prototype hardware, firmware, and software elements that help expedite the migration from raw ASIC RTL and IP. Today the state of the art in ASIC prototyping and software development tools join software development platforms running reference designs with pre-packaged IP configurations. Prototyping kits are operational out of the box and allow hardware and software developers to immediately engage in integration and validation tasks necessary to ship the next great SoC design.

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