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Cadence Introduces Genus Synthesis Solution

Gabe Moretti, Senior Editor
Historically synthesis tools have targeted the transistors, keeping in focus the architecture of the silicon and optimizing it while not paying much attention to the system architecture.  it was, of course, a natural thing to do since given a design, EDA tools focused on implementing it in the best of possible way.

This is the main reason that System level tools have been slow to gain traction, and only lately are showing that they can indeed contribute significantly to efficient products.  In fact by analyzing an architecture it is often possible to improve the efficiency of the design and, in turn, deliver a circuit that meets timing, power, and area requirements in less time than by optimizing the gate level netlist.

Genus does just that.  Its goal is to optimize the RTL netlist before logic synthesis by forecasting the physical characteristics of the resulting gate level netlist.

Cadence’s Genus Synthesis Solution is a next-generation register-transfer level (RTL) synthesis and physical synthesis engine.  The company stated that Genus Synthesis Solution incorporates a multi-level massively parallel architecture that delivers up to 5X faster synthesis turnaround times and scales linearly beyond 10M instances. In addition, the tool’s new physically aware context-generation capability can reduce iterations between unit- and chip-level synthesis by 2X or more. This combination enables up to 10X improvement in RTL design productivity.

Figure 1: Genus integrated optimization architecture

Key Genus Synthesis Solution features and capabilities include:

  • Massively parallel architecture –The tool performs timing-driven distributed synthesis of a design across multiple cores and machines. All key steps in the synthesis flow leverage both multiple machines and multiple CPU cores per machine.
  • Physically aware context generation – The complete timing and physical context for any subset of a design can be extracted and used to drive RTL unit-level synthesis with full consideration of chip-level timing and placement, significantly reducing iterations between chip-level and unit-level synthesis runs.
  • Unified global routing with Innovus Implementation System – Genus Synthesis Solution and Cadence Innovus Implementation System, a next-generation physical implementation solution, share an enhanced 4X faster timing-driven global router that enables tight correlation of both timing and wirelength to within 5 percent from synthesis to place and route.

  • Global analytical architecture-level PPA optimization – The solution incorporates a new datapath optimization engine that concurrently considers many different datapath architectures across the whole design and then leverages an analytical solver to pick the architectures that achieve the globally optimal PPA. This engine delivers up to 20 percent reduction in datapath area without any impact on performance.

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