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Advanced-Node Designs in 2016 and Beyond

Vassilios Gerousis, Distinguished Engineer, Cadence

This year, many of the expectations in the semiconductor industry are around the technologies that enable advanced-node design, along with the applications that are driving the migration to smaller processes.

If 2015 was any indication, we will continue to see an emphasis on designs for the Internet of Things (IoT), wearable, and mobile spaces. This means a continued focus on lowering power, lowering costs, and shrinking area—the characteristics that advanced process nodes are suited to deliver.

At advanced nodes, the main concerns are around higher speed and lower power, which FinFET 14nm and 16nm both provide. We have already seen some industry announcements about designs (CPUs) done at ultra-low voltage (sub-threshold region) using mature nodes like 40nm as an example. Since the speed at these voltages will be very slow, the main targeted application will be IoT designs, where ultra-low power is needed. This year, we will likely see both CMOS and FD-SOI technologies help overcome some of the challenges of ultra-low power designs.

While few expect 10nm production, we will definitely see 10nm test chip products this year. Some will even hit production timelines and become actual product designs. At the same time, we will see more products go into production at the 14nm and 16nm process nodes. Designers are definitely migrating from 28nm, and even skipping over 20nm.

10nm Design Challenges

10nm design brings more complex design rules along with a multi-coloring approach, resulting in as many as three masks per layer, as well as multiple colors for vias. The handoff to the foundry, therefore, will have to be colored, making it essential for the entire digital implementation flow to be color-aware.

Since the designs are shrinking, we must anticipate unexpected electrical performance behaviors. The interconnect will continue to be the major bottleneck at 10nm, in terms of electromigration issues, an increase in resistance, and an increase in coupling capacitance (relative to total capacitance). The interconnect is much thinner in these designs, so electromigration is a major design challenge to address in addition to timing and signal integrity. Designers will need newer capabilities in EDA tools to provide good solutions for their 10nm designs.

Unlike previous technologies, 1D routing direction (no wrong-way routing) is becoming the normal design behavior rather than the exception at 10nm and 7nm. Improved routing features to address 1D very effectively will be essential to providing better power, performance, and area (PPA) design targets.

Extending Moore’s Law

3D-IC technology further extends Moore’s Law, generating higher bandwidth with lower power consumption at a small form factor—all without requiring traditional process scaling. At the moment, the majority of products for 3D-IC are appearing mainly in memory and FPGAs. The through-silicon vias (TSVs) in 3D-ICs consume a lot of area compared to the rest of the wiring, limiting how much functionality you can integrate onto the device and also impacting cost. The new monolithic 3D-IC technology, which uses normal sequential processing and regular vias instead of TSVs, is starting to appear. Again, memory products are leading the way in using monolithic 3D-IC processing.

New packaging technologies have already emerged to support cost-, power-, and form factor-sensitive applications like those in the IoT and mobile spaces. For example, we now have access to packaging technology that provides a thin package supporting one or two die.

We could see FinFET designs move to nanowire technology at even smaller processes, such as 5nm or 3nm. Nanowire FinFETs, architected with all gates surrounding the silicon, are ideal for their superior electrostatic control. Indeed, these smaller nodes are on the horizon. In October 2015, IMEC and Cadence announced that they completed the first tapeout of a 5nm test chip using extreme ultraviolet (EUV) and 193 immersion lithography.

Summary

In 2016, we will see an emphasis in product design starts at 10nm, and the year will also introduce a few 7nm test chips. Lines plus cuts, as illustrated in Figure 1, will be one of the main technologies to use at 7nm.

Figure 1: Lines plus multi-color cuts used in 5nm tapeout.

Cadence is working with leading foundries and research labs to prepare our tools to address the challenges that these advanced nodes bring. Innovation continues to be the key with each technology node in order to utilize these nodes more effectively.

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