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Cadence Releases Next-Generation Virtuoso Platform

Gabe Moretti, Senior Editor

Cadence has chosen to retain the user interface of the Virtuoso custom design product while adding significant enhancement that, simply said, make it perform as a new product.  The platform includes new technologies within the Virtuoso Analog Design Environment (ADE) and enhancements to the Cadence Virtuoso Layout Suite to address requirements for automotive safety, medical device and Internet of Things (IoT) applications.  The new Virtuoso ADE enables engineers to explore, analyze and verify designs against goals to ensure that design intent is maintained throughout the design cycle.  “The Virtuoso Layout Suite offers up to 100X accelerated zoom, pan, drag and draw performance on large layouts” says Steve Lewis, marketing director CIC and Packaging Group (CPG) at Cadence.

The Virtuoso ADE Product Suite

The new Cadence Virtuoso ADE product suite addresses the challenges that come with the emergence of new industry standards, advanced-node designs and the requirements for system design, enabling engineers to fully explore, analyze and verify designs to ensure that design intent is maintained throughout the design cycle.  The suite’s key technologies include:

  • Virtuoso ADE Explorer: Enables fast and accurate real-time tuning of design specs, provides pass/fail datasheets and delivers a complete corners and Monte Carlo statistical environment for detecting and fixing variation problems
  • Virtuoso ADE Assembler: Enables engineers to analyze their designs under various process-voltage-temperature (PVT) combinations; also offers GUI-based verification plans so designers can easily create conditional and dependent simulations
  • Virtuoso ADE Verifier: Provides a substantial technological advancement in analog verification, offering an integrated dashboard that lets engineers easily verify that all of the blocks are contributing to the overall design specifications

Yanqiu Diao, deputy general manager, Turing Processor business unit at HiSilicon Technologies Co., Ltd. Commented that: “Through our early use of the new Cadence Virtuoso ADE product suite, we’ve found that we can improve analog IP verification productivity by approximately 30 percent and reduce verification issues by one-half. Our smartphone and network chip projects should benefit from these latest capabilities.”

Figure 1: New Virtuoso ADE Architecture

Virtuoso Layout Suite Enhancements

The enhanced Virtuoso Layout Suite addresses the most complex layout challenges by offering accelerated performance and productivity for custom analog, digital and mixed-signal designs at the device, cell, block and chip levels. The suite’s latest updates provide the following enhancements:

  • Graphics rendering performance: Provides from 10X to 100X accelerated zoom, pan, drag and draw performance on large layouts
  • Module Generator (ModGen): Interactive pattern manipulation flow that makes real-time customization of ModGens very visual and simple; also now supports synchronous clones, which are layout elements with identical physical propertieslike width and length of transistorsthat the layout designer can layout once and reuse
  • New structured device-level routing: Structured device-level routing capabilities can enhance routing productivity by as much as 50 percent

“Customers have continually placed their trust in the Cadence Virtuoso platform for more than 25 years, taping out thousands of designs each year,” said Tom Beckley, senior vice president and general manager, Custom IC & PCB Group at Cadence. “The need to do custom design has never been greater, and increasing complexity is driving the need to further simplify the design process so our customers can meet design schedules.”

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