By Ed Sperling
System-Level Design sat down with Ravi Varadarajan, an Atrenta fellow; Geert Rosseel, vice president of technology at Arteris; Yankin Tanurhan, vice president and general manager of Virage Logic’s processor and NVM business units, and Mike Smayling, senior vice president of product technology at Tela Innovations. What follows are excerpts of that conversation.

SLD: How real is 3D?
Smayling: 3D is clearly happening. People are building chips with 3D. As with any pioneers, they’re the ones with the arrows in their back. There are a lack of tools and a lack of infrastructure, but that will change. Applied Materials announced it is supporting the dielectric coatings for through-silicon vias. It’s important to have those tools available if you’re going to build the structures. Having the big manufacturers get involved means they see the importance of the business and the demand for multiple tools.
Varadarajan: The business need and the technical need for 3D is real. Moving to 28nm and below, there are two factors at play. One is the complexity of the interconnects. When you are dealing with 2D, the wires are incredibly long. The performance you’ll get by going to smaller geometries will be nullified by the long wires and the complexity of doing the layout. The second aspect is heterogeneous integration. There’s really no need to migrate everything you want to put onto an SoC into the new technology. That’s an impediment today. If you have an analog block and some memories that don’t need to move to the next node, you still have to do it if you’re building a chip in 2D. When you look at the complexity on one side and the parasitics on the other, both of those say you need to have some sort of 3D technology moving forward. The process enhancement has been happening and 3D technology is coming to the point where it can become mainstream. This is a wonderful opportunity where the technology is maturing and the need is prevalent. Leti, Imec and SEMATECH are all coming together. If you don’t have some sort of 3D strategy in 2012 you’re going to be left behind, at least for memory on core architectures.
Rosseel: Somebody has to take a contrary view. I think we have to define first what 3D is. You can start with a package on package, which is some version of 3D, and then you have stacked die and go all the way down to having four or five chips fully designed as an integrated circuit. I think the last one is a long way from reality, and I’m not sure if that’s even desirable. Stacked die is already happening. But implementing stacked die as multiple chips on top of each other may not be worth it. You get an extra process complexity and extra cost for doing that. There are too many problems to implement that.
Tanurhan: The real driver of 3D is that no one can pay all the costs for a certain process node. Being able to use multiple process nodes on the same application is opening that corner, and that’s how the whole mechanical 3D solution came in. For a while it was called system in package. The first time I heard the ‘3D’ word in conjunction with semiconductors design was the early 2000s, and in 2007 it started to become a marketing name. I still don’t know what it is. The IBM concept is different than an SiP. A single-die 3D is a big change, because you will get higher density, you will minimize the wiring, and you will need a lot of IP. But we are not seeing that pull yet. One of the reasons is the tools are not available and another is the yield is not there. But 3D is extremely interesting for us. With non-volatile memory the sweet spot is still 90nm and above, even though we have 65nm and 40nm available. It doesn’t make sense to take this technology to 28nm because the price tag will be enormous. The analog circuit doesn’t shrink. You have to pay more for the wafer. So stacked dies are becoming very interesting. But it’s not easy to do. The world is going to multiple processors, heavy on-chip communication and heavy processing. Now you have to cross domains from one chip to another and you cannot use the communication protocol you’ve been using. It behaves more like a PCB, but it really isn’t one. And, by the way, it’s your problem to solve the timing issues because we don’t have tools, either. For a memory block, it’s a done deal. But having multiple processors communicating on the same bus and sharing the same memory will be a heavy thing to lift for all designers.

SLD: Let’s dig into some of the problem points.
Varadarajan: You’re talking about people conceptualizing where you have 90nm, 65nm and 45nm. Just splitting the gates across the different technology nodes and figuring out the best possible layout and the routing is an interesting technology problem to solve. I don’t think we’re going to get there anytime soon. But memory is happening today. You can even extend that one step further to when you have a two-die structure and you just put in memory. You have a lot of white space on the memory die. If you look at systems on chip today, they are complex IPs put together with a bus fabric connecting them. These IPs exist in multiple technologies. You can start to question whether this IP belongs at a lower technology node or whether it can go into older technology nodes because there is empty real estate. By doing that, how do to the timing and high-speed IP look? That is a practical application. It’s memory and then also migrating entire IPs into different tiers and dies. Then you have to look at timing and your thermal profile and whether you need to do something special to dissipate the extra heat. But if you can solve all of these problems you have a viable approach.
Rosseel: We’re looking at this more from an architecture point of view. People are not going to share transistors and gates, but they are going to share IP between different die. Then the only question is how these IP blocks are going to talk to each other. We see network on chip as a communication mechanism. You need some kind of communication because they’re all developed separately and designed separately. To create that coupling you’re going to have to create some standard interfaces. They will have to be asynchronous and configurable. With standard interfaces you can test them separately and design them separately.
Tanurhan: Network on chip is on-chip. This one is off-die. There is a lot of development that needs to be done. The white space issue is real and has to be addressed, but it’s a system architect’s nightmare. It is not straightforward to have all that timing budget and model it right. The reason why it works with memory is it is very nicely encapsulated. Sharing IP blocks will require two elements. One is local management capability, so you will some type of system supervisor to make sure all that local intelligence is managed right. That is not a passive element. On the really high-speed 3D, you also will have all the cooling problems. Today you can create a really high-speed processor. If you have two of those, one sitting on top of the other, how do you keep them alive? So one challenge we have is connectivity. A second is yield. The cost function still has to make sense, too. Yield is a multiplier of cost.
Smayling: 3D has been around in ICs since 1985. At that time we were building DRAMs with planar capacitors and we couldn’t build the chips big enough because of reticular limitations so we began building in 3D structures, either trench capacitors or cup capacitors. Integrated devices like DRAMs had to start long ago, because of cost reasons, to go 3D. Cost has always driven our industry. People will do 3D or hybrids if they’re cost-effective, but they won’t be if the tools aren’t there for the masses to use them. You can always have very big engineering teams figure out ways to grind through these problems, but unless you have EDA support, ecosystem support and standards it won’t happen. How can you design a 3D chip with the tools you have? The data structures aren’t even there to understand what you’re trying to do. At TI we built these merged process devices and they were successful if you knew what you were going to merge at the beginning and then used as much of the additional process complexity across the chip as possible. If you added 5% to the wafer price but only used it on 2% of the area you had a losing proposition.

By Ed Sperling
System-Level Design sat down with Glen Daves, director for packaging solutions development at Freescale Semiconductor; Carey Robertson, product marketing director for Calibre Design Solutions at Mentor Graphics, Rajiv Maheshwary, senior director of customer marketing at Synopsys and head of the company’s 3D initiative; Javier DeLaCruz, director of semiconductor packaging at eSilicon. What follows are excerpts of that discussion.

SLD: Given all the considerations in SoC design today—thermal issues, placement, routing, power—does that all get in the way of how you manage the flow in 3D?
Robertson: Yes and no. It’s easier to look at the design intent and what needs to be addressed in a flow rather than allowing all degrees of freedom and architecting tools to respond to a particular scenario. You’ve got to prioritize. Here is a particular problem we’re going to solve with TSV implementations. Maybe it’s thermal, maybe it’s something else. If we narrow the focus, we can do a good job. This lends itself to a best practices approach. For example, ‘Here’s what TSV is going to address.’
Daves: A lot of the leaders in this technology—those who are the farthest ahead—are holding their cards close to their chest. There are applications out there where people know the first step and the second step, but no one is talking about it until it comes to market. That places the EDA community at a disadvantage.
Maheshwary: It’s both yes and no. Yes, because this is an emerging area and so much is in flux. And no when we look at some of these initial applications. We have one customer that has all these memories in a stack and all these TSVs in the middle of the die. They’ve got 500 TSVs in the middle of the die, but you can’t route metal 2, metal 3 or metal 4 on it. Is this a product application? No, it’s a test chip. Three months later, they say they can use level 3. All of this has to be done in collaboration with a customer. You have to work the design methodology accordingly. We need insights into these things, and restrictive designs will come into play. Foundries will emphasize it. We will need rules and over time we can relax the rules because of all the unknowns.
DeLaCruz: You have the luxury of waiting until customers develop the specific application only if you can react very quickly. If you can’t react quickly, you have to predict what will be done and put those tools out there. If the tools and teams are in place, then you could wait until you have specific examples. The applications for TSVs are very diverse. There are fingerprint sensors where you need to interface with the silicon. On the face of the CMOS you also need an interconnect, so you can avoid having an air cavity. You put the glass lens directly on the surface of the silicon. A lot of these developers need to make sure they have an infrastructure in place. The cost is unknown. And there are a lot of reliability issues. But if we’re going to wait for one or two customers to drive this, it’s not going to happen.
Maheshwary: I agree that we shouldn’t wait. But we all do need to partner to get clarity in terms of what it is we’re trying to build. If you look at the EDA community it’s now via middle, not via early or via last. It’s die-to-wafer bonding. That’s great. But you’ve got to define these things in terms of a pragmatic approach. Then you say, ‘What’s the methodology to make this work?’

SLD: At advanced nodes, the bulk of the cost is in the verification. Does that change with 3D? And does it move from a linear to a concurrent flow where multiple things have to be done at once?
Robertson: As much as possible, we’re trying to fit into the paradigm that exists today in terms of bottom-up as you build up these components. But there also is back-and-forth between the various dies and how they behave in silicon. I don’t know if it’s going to change the cost structure. But in terms of how customers respond to this, it is going to change their methodologies and their methodologies for modeling, as well as how they go back in to fix certain parts of the design that aren’t performing as well as they expect. There are well-established methodologies for fixing things now. Fixing things in a multi-die infrastructure is going to be very problematic and quite a big challenge. I think methodologies will have to change.
Maheshwary: If you put the boundary conditions on what you are trying to build, there will be some tasks that will be done in parallel. You can do LVS or timing models of stacked die. Test is an interesting area. You will probably do intra-die testing, and then testing between die using JTAG or whatever standard evolves. This is an evolutionary change for EDA. When you’re looking at a heterogeneous device that includes logic and memory or logic and analog, when you have logic on logic and you’re moving structures from this die to this die—that’s the real power of 3D, but it’s going to take some rethinking about what we do and the tools we use. I see that happening five years from now.
DeLaCruz: If you’re designing an ASIC that’s going to be used for a high level of integration, it would be crazy to have all of your test pins come out of each die and go into the package. Test compression on one ASIC is going to drive the test for all the other devices. It can test all the connectivity for all the other chips and send out a ‘pass’ or ‘no pass.’ To have a die in isolation wouldn’t work.

SLD: Does bulk CMOS and existing packaging work?
Daves: Most of the effort today revolves around using standard CMOS processes to deliver the TSV. That’s going to prove to be a solvable problem. On the packaging front, assembly is a challenge. As the I/O pitch goes down, it gets more challenging. But wafer-to-wafer is going to end up being a small number of applications. As we move to die to wafer, it’s hard to envision putting too many chips in the die-to-wafer configuration unless the sizes work out just right. So I think we’re looking at die-to-die. There’s certainly a lot of work on all three of those. I think we’ll be in the realm of standard packaging materials. The challenge is assembly.
DeLaCruz: I agree. Even though you do all this integration, the main ASIC will be a typical device and that will use more traditional technology. That ASIC will have TSVs connecting to the next device. There are a lot of other 3D formats that are not TSVs where you build a package right on the die rather than putting the die in a package. That is an emerging technology. There you will have some very advanced 2D integration.

By Pallab Chatterjee

The advent of digital imaging in the production, broadcast and projection of films will drive the current 3D craze into a sustainable long-term trend. The digital medium allows for “headache-free” viewing and is expected to produce about $1 billion in revenue this year in North America.

What’s changed this time is 3D formats will not be limited to feature films in theaters. The technology is going to be used for feature films in digital cinema, IMAX movies, Blu-ray home video, video downloads, 3D home television, cable broadcast, and even gaming. For the next few years all of these 3D formats will require some form of glasses (circularly polarized, active switching, etc.) and will be viewable on standard digital silver screens and properly equipped flat panel and DLP displays. Portions of the last Olympics and the upcoming 2012 Olympics are targeted for 3D live broadcast and in Europe, where a full 3D channel is planned next year.

To manage these broadcast signals and digital workflow, all of the editing and post-production work is being done on 2D objects, with 3D effects added in. The four leading 3D systems are RealD, XPand, Dolby 3D and Master Image (MI). Worldwide, MI is the leading format. To date, the largest installed projector is a Texas Instruments DLP-based system that projects two 2K images to make the 3D. The newest most versatile system is from Sony and is a digital 4K projector, which can put out a single 4K image or two 2K images for 3D.

The home format for TVs and Blu-ray players is being addressed by the Society of Motion Picture and Television Engineers (SMPTE). The group is targeting formal specifications and standards by 2011, but the Blu-ray Disk Association and the associated 3DDisplay Association will have a working standard at the end of December 2009 that will support full 2D compatibility with existing players and existing displays. At this time, they are targeting an encoding system that will allow them to keep a full-length movie under 50 GB so it can stay on a BD50 disc. The cable industry indicated its rollout, which is on a three-to-five year timetable, would be the standard definitions, then silicon, then set-top boxes, then encoders and finally displays.

On the gaming side, the game play is being enhanced for 3D, as well as just the graphics. The games will be playable on 3D televisions with special glasses and on standard laptop displays and large-format flat panel displays, as the rendering is done in real time through the graphics card. UbiSoft, Electronic Arts and Blitz games either have existing 3D titles or will have them by this holiday season, including the UbiSoft release of “Avatar” on all three console systems and the PC.

Some of the challenges that are being faced for live broadcast have to do with the real-time marker on the broadcast. These include the familiar telestrator drawings, current position and first-down markers on the football field, scoring and scoreboard banner position, etc.

On the Blu-ray side, one of the major issues is creation and placement of subtitles. Depth of field and making sure subtitles are not obscured by objects in the 3D foreground are systematic issues that need to be addressed.

The last technical issue is to whether to shoot the original content in 3D, which is limited by the sheer size of the stereoscopic rig, or whether to shoot in 2D and convert to 3D in post processing. This gives a more predictable cost but not always the best effect.

There is $500 million available for the digital cinema upgrade in North America, which is driving the creation of almost 30 titles in 3D in 2010. The current rate of expansion should have 11,000 digital cinema screens worldwide in early 2010, which will be a large enough base to carry the films on an ongoing basis. These digital solutions are in addition to film based projections solutions from Technicolor and Trioscopics3D. The Trioscopics solution already has been deployed on over 20 million hom

By Cheryl Ajluni

At the 46th Design Automation Conference in San Francisco last month, attention turned to a discussion of how to extend the momentum of Moore’s Law into the next decade. One plausible solution, according to Philippe Magarshack, the general manager of Central CAD & Design Solutions at STMicroelectronics, is 3D stacking for complex System-on-Chips (SoCs).

The concept of 3D stacking or integration technology is not new. In fact, 3D stacking of dies has been successfully demonstrated and is currently being commercially employed in some embedded domains (e.g., stacking DRAM memory on CPU cores). A recent 3D IC report from Yole Développement suggests that by 2012, the number of 3D IC-processed wafers could surpass 10 million units, driven in part by handset, wireless and computing applications. Given the intense interest and work going into developing 3D integration technology, this prediction seems just about right—assuming, of course, that a few challenges can first be met.

Exploring the third dimension

Very simply put, 3D integration consists of stacking integrated circuits and connecting them vertically so that they behave as a single device. A 3D chip is therefore just a stack of multiple device layers with direct vertical interconnects tunneling through them. So what’s the big deal about 3D integration?

Today’s semiconductor chips face extreme pressure to achieve increased performance, while reducing their size and accommodating lots of new functionality. When these factors coalesce in traditional 2D chips, longer interconnects result. In SoCs, longer interconnects translate into reduced speed and increased power consumption.

A key benefit of 3D integration is that it can reduce the length of interconnects. Additionally, it provides higher transistor density, faster interconnects and heterogeneous technology integration, with potentially lower power, cost and faster time-to-market. As Matt Nowak, director of engineering in the VLSI technology group of Qualcomm’s CDMA technology division, pointed out in a DAC 2008 presentation, the 3D approach “achieves extremely high densities, allowing us to use heterogeneous technologies and reduce form factor. The key is that it enables the use of new differentiating technologies to build new architectures that cannot be built in existing technologies.”

Eyeing recent developments

Up to this point, most efforts in 3D integration have focused on developing different fabrication techniques for stacking multiple device layers and forming the vertical interconnects. Much of the work has been done through collaborations with academia, industry organizations and government-sponsored laboratories around the world. One of the key technologies to come out of this research is a next-generation interconnect technology known as Through-Silicon Via (TSV). The TSV is a vertical electrical connection that passes completely through a silicon wafer or die to produce multilevel chips with an optimum combination of cost, functionality, performance, and power consumption. By using TSV technology, 3D ICs can pack greater functionality into a smaller footprint and realize shorter critical electrical paths, resulting in faster operation.

Some of the other developments to come out of ongoing 3D integration research were recently recognized at the Electronic Components and Technology Conference. Sandia National Laboratories presented details of its W TSV process, which is said to provide a suitably low-resistance metal with a coefficient of thermal expansion close to Si, a via fill that is conformal, and can be readily integrated into IC fabrication. IMEC introduced a novel process for die-to-wafer bonding (using Cu-Cu bonds) of its 3D SIC technology and a scalable TSV technology for 3D wafer-level packaging. Its TSV technology is designed for 3D structures where interconnects are fabricated after standard CMOS processing.

SEMATECH also is focusing its 3D research on TSV technology, particularly for implementation. The industry organization is actively working to bring together partners from across industry—chipmakers, equipment and materials suppliers, assembly and packaging service companies—to make 3D TSV suitable for high-volume manufacturing (Figure 1).

Figure 1. In contrast to the 2D-SoC or 3D System-in-Package, 3D TSVs offer a cost-effective way to achieve high density and performance, while also being able to integrate non-CMOS products with CMOS. The SEMATECH 3D project is based on cost modeling to assure products will be both manufacturable and affordable.

Help: tool support needed!

While ongoing research and development is absolutely critical to the success of 3D integration, perhaps one of the greatest challenges it faces is tool support in terms of design techniques and methodologies. Without it, engineers have virtually no efficient way to exploit the technology’s benefits. Tool support is especially critical when it comes to 3D integration because vertical stacking tends to increase thermal resistances, further exacerbating temperature-induced problems that can negatively affect system reliability, performance and leakage power. The use of 3D also will significantly complicate the typical design flow.

The key, of course, lies in creating a standardized design environment and methodology for physical design of 3D chips that could support a range of different tools. Having the tools integrated in one place would make it easier for designers to explore and make architectural decisions and then, to hand those decisions off to next stages in the design process.

3D IC integration is still in its infancy and, as a result, tools developed today for one specific application (e.g., stacked memory) may not be suitable for heterogeneous integration tomorrow. Nevertheless, there are some tools available now, with more in development. Some of these tools include:

3D PathFinding

Javelin Design Automation. 3D PathFinding provides a detailed 3D flow for accurate performance/power/cost estimates that can be used for rapid design exploration and optimization of 3D stacked ICs. Developed in collaboration with IMEC and Qualcomm, the solution extends Javelin’s existing PathFinding methodology and j360 Silicon PathFinder physical design prototype platform to support virtual chip design (Figure 2).

Figure 2. Javelin’s 3D PathFinding solution allows the designer to assess the impact of various 3D interconnect strategies throughout the IC design and fabrication process, in a matter of just a few hours or days. Silicon process engineers can use it to fine-tune their technology to the system architecture specifications.

MAX-3D, R3Integrator, R3CAD, and R3Artist; R3Logic

These tools, developed through work conducted as part of research programs sponsored by the Defense Advanced Research Projects Agency (DARPA), enable 3D IC design and analysis (Figure 3). MAX-3D is a 3D mask layout tool whose technology file includes all properties of stacking process, wafer orientations, bond materials, via electrical/material properties, and also incorporates 2D foundry design kits. R3Integrator is used for die/interposer/package co-design with TSVs. R3CAD is a java-based, multi-platform tool for 3D design research and prototype study and R3Artist is an embedded 3D layout editor (Figure 3).

R3Logic is currently collaborating with STMicroelectronics and CEA-LETI to develop a full 3D design flow for 3D heterogeneous system and system-in-package design.

Figure 3. R3Artist features single and multiple wafer technologies, integrated material properties database and solid model extraction, including dielectric layers.

3DCACTI

3DCACTI estimates the optimum access times and power dissipation of a cache using 3D IC technology for a given number of active device layers and by partitioning device layers for various technology nodes. Based on the estimation, it searches for the optimized configuration that provides the best delay, power and area efficiency trade-off according to the cost function for a given number of different 3D partitions.

3D Magic and PR3D, Massachusetts Institute of Technology

3D Magic is a comprehensive layout methodology for 3D circuit-layout editing and extraction with MAGIC, an open source layout editor developed by UC Berkeley. PR3D is a placement and routing tool for standard cell design in 3D. Both tools were developed through MIT’s Interconnect Focus Center Research Program. MIT also developed SysRel (System-Level IC Reliability) for assessing the interconnect reliability of 3D ICs from a thermal-aware perspective at the circuit-layout level.

Conclusion

With the pressure on traditional 2D chips mounting, 3D integration has begun to establish itself as a viable means of breathing more life into Moore’s Law. It certainly touches on all the hot buttons in the industry today, namely low power, cost and time-to-market. The challenge will be in ensuring that these benefits are realized in a timely and efficient manner. 3D-specific design tools and methodologies are coming to meet this challenge head on. In the meantime, the tools available now and the groundwork for future tools and methodologies being laid by industry organizations, academia and commercial companies alike, will go along way in ensuring 3D integration plays a critical role in the future of the semiconductor industry.