By Ed Sperling

It was a good week for thinking out of the package.

Mentor Graphics acquired Valor Computerized Systems, a recognition that system problems now extend well beyond the chip. Valor’s expertise is in PCB software and DFM. The purchase price was about $50 million, including $32.5 million in cash and 5.6 million shares of Mentor stock. Interestingly, Valor’s revenue for 2008—the last full year it reported—was about $40 million.

Mentor also inked a three-year joint-development deal with STMicroelectronics to develop advanced SoC design solutions down to 20nm.

Actel appears to be benefiting from its new SmartFusion rollout. The company updated guidance, saying Q1 revenue will be up 4% to 8%, instead of 2% to 6% it had previously reported. http://www.actel.com/company/press/files/busupdateQ110.pdf

Cadence is expanding its academic network in Europe, adding three universities from Bucharest, Stockholm and Braunschweig for everything from PCB design to low-power methodology.

Intel rolled out its first six-core 32nm Xeon chip for servers, claiming it offers 60% more performance for the same power consumption of 130 watts. Versions of the chips with lower clock speeds can use as little as 40 watts.

By Ed Sperling

Synopsys is teaming up with Imec, the Belgian research lab, to help solve the problems of 3D IC stacking and through-silicon vias. This is important stuff for re-use of older technologies, not to mention cutting verification time and achieving timing closure and getting chips to market on time and improving yield and…well, you get the idea. Synopsys also added design-rules-driven technology to Galaxy Custom Designer that helps speed DRC repair tasks.

Mentor Graphics added Amba 4 verification IP to its Questa library. Given the growing popularity of ARM’s processor, this is a necessary step—especially with Mentor’s commitment to the Android phone.

Actel got its first public endorsement of its new SmartFusion chip. Micrium is porting its embedded software stack to the mixed-signal FPGA. Micrium’s software is targeted at the ARM Cortex-M processor line.

TSMC sales were up 0.1% from January to February, which isn’t much. But when you consider that’s 144% higher than last year it starts putting things in perspective. Still, it would be nice to have a breakdown by process nodes.

By John Blyler & Ed Sperling
Is the Electronic Design Automation (EDA) tools market shrinking or growing? That depends greatly upon how you define EDA.

A recent report by the Global Industry Analysts, based on information from EDA Consortium (EDAC), predicts that the global EDA tool market eventually will re-emerge to drive growth to $9.8 Billion by 2015. The report suggests that this growth will be fueled in part by the traditional efforts to improve efficiency and performance throughout the chip development process.

EDA Chip-Level Tools
Aart de Geus, chairman and CEO of Synopsys, expanded upon this finding in a recent interview. “As a percentage of our business, classic EDA is shrinking, but this is not a case of ‘classic EDA doesn’t grow.’” For example, in the past, EDA companies added front-end RTL synthesis and design tools with timing and power closure to improve the productivity of chip designers. Next, efficiencies were found in the back-end of the process by adding physical design with extraction and Design for Manufacturing (DFM) and Yield (DFY) tools. Today, EDA vendors are improving the value of system-level design with architectural tools.

Synopsys is indeed attempting to improve their architecture tool flow with the recent double acquisitions of two electronic-system level (ESL) design companies – VaST and CoWare. The emphasis on architectural integrated circuit (IC) design productivity has pushed traditional EDA chip companies to expand into the next level of product development, namely, package and board design and – on the software side – even application development.

But this time around, productivity and efficiency within the chip development process will not be enough to save EDA. In addition to continuing improvements in both front and back-end tool design, chip-level EDA companies must be successful in reaching outward to embrace new customers and industries.

Perhaps no one understands this shift in thinking better than Mentor Graphics, who has products in the chip, package, board and even embedded real-time operating system (RTOS) markets. “We (EDA chip tools) as an industry are stubbornly targeting a limited number of customers,” said Serge Leef, vice president of new ventures and General Manager of the System-Level Engineering Division at Mentor Graphics. “We really need to figure out where to go beyond that.”

There are four choices, according to Leef. One is to sell products to existing customers, which EDA companies will continue to do. The second is to sell new products to existing customers, which they are attempting in areas such as submicron design, DFM and yield enhancement. A third option is to sell existing products to new customers in places like China and India, but most of those companies are either part of multinational companies that already buy EDA tools or they’re underfunded startups that cannot afford tools. A fourth option is to sell new products to new customers.

On paper, the last option seems the most promising. The problem is getting the new customers to look at what EDA has to offer, which means that EDA companies must understand the needs of the new customers – i.e., different industries.

IP Drives Profit
A universal need shared by most new customers in today’s economically challenged markets is that of cost reduction. This has two effects. One is to increase the use of intellectual property (IP) blocks in chip-level design while the other is to move from ASIC to FPGA-based designs.

Increasing the use of IP was a primary theme in Virage Logic’s keynote address at the recent DesignCon show. That was expected, but the arguments that were used to support the growth of IP are worth noting. Brani Buric, executive vice president for marketing and sales at Virage, explained it this way: “As we move into consumer markets with low profit margins we must think beyond the technical challenges to the business issues. The question is not just how to do the design more efficiently in terms of cost, but whether to do the design at all.”

The business focus of this approach is reflected in its name, i.e., Design for Profitability (DFP). Companies focusing on profit might just write the spec for a new chip, then hand off the rest of the design and implementation to design companies such as eSilicon or Open-Silicon. Owning the spec would typically be a lot less expensive than owning any part of the implementation process. This approach relies heavily on IP blocks to build the chip to spec.

Interestingly, the growth of IP is one of the key drivers cited by in the Global Industry Analysts report for overall EDA growth. The reason that EDA tool revenues are expected to climb in 2015 is because EDA owns IP. By including Broadcom, Qualcomm and ARM as some of the largest IP licensing companies, EDA will indeed be one of the fastest growing sectors—at least on paper. The reasoning for this inclusion, according to EDAC, is that EDA tools are an integral part of licensing the IP, so IP licensing revenues should be counted in the EDA business calculations.

EDA in the Board-Level Market
The growing reliance on FPGA-based electronics is the second trend driven by profit-focused designs. But this is another area where companies like Actel, Xilinx and Altium are trying to engage a broader customer base, e.g., medical, industrial and automotive markets.

Actel’s purchase of Pigeon Point moves that company squarely into the Advanced TCA and MicroTCA world, which has been heavily utilized by communications companies and defense. Xilinx, meanwhile, is positioning its next-generation 28nm FPGA platform to help win business in non-traditional markets. And Altium has been focusing on a single database implementation of FPGA-based, board-level products that include embedded software development.

While all of these expansions reflect broader changes in the overall semiconductor industry, real growth in the EDA sector can only come from expansion beyond traditional markets. But there will always be a nagging question facing EDA companies moving into these new markets: Is this really EDA, or are we venturing into a new sector that reaches well beyond the confines of EDA to include a true system-level approach?

By Ed Sperling

Money is flowing again. Sometimes into companies, sometimes out of companies. But at least it’s moving.

Synopsys bought VaST Systems for an unknown price, but it doesn’t appear it was a vast amount of money. Synopsys said it didn’t materially affect its numbers, which means it fell well below the radar screen. Apparently it’s tough to break into the software prototyping market without serious integration with other tools in a flow. This builds on Synopsys’ acquisition of Virtio in 2006.

Virage Logic’s revenue for Q1 of its fiscal 2010 was $21.7 million, up from $11.3 million in the same quarter in 2009 and $13.1 million in Q4. The company reported a loss for the quarter of $2.2 million, but that loss reflects the costs of recent acquisitions. Minus those charges, profit would have been $900,000. More significant for Virage, royalty income for Q1 was $4.7 million vs. $2.8 million in the same period in 2009, a sign that companies are building chips again and licensing IP to get to market more quickly.

Actel posted a profit in Q4 2009 vs. the same period in 2008, despite a drop in overall revenue. Net income was $1 million in the quarter, vs. a loss of $12.5 million during the same period in 2008. Revenue was $49.7 million in Q4 2009, down 5.8% from 2008, but up 5.2% from Q3 2009. For the full fiscal year revenue was $190.6 million, down 12.7% from fiscal 2008. The company expects revenues in the current quarter to rise 2% to 6% compared to Q4.

Actel also announced that its president and CEO, John East, would step down once a replacement is found. East, who is 65 years old, will continue serve as a consultant through August 2011, after which he will retire. He has led the company for the past two decades.

Things were modestly upbeat at Cadence for the first time in months. The company reported financial results for Q4 and fiscal year 2009. In Q4 revenues slipped to $220 million vs. $227 million in 2008, but net income was $2 million vs. a loss of $1.63 billion (!) in the same period in 2008. It must be nice to write in black ink again. The Q4 2008 loss included a $1.36 billion “impairment charge.” For the 12 months, revenue was $853 in 2009 vs. $1.04 billion in 2008. Net loss for 2009 was $150 million vs. $1.86 billion including that one-time charge (or $500 million without that charge).

The bottom line—the worst is over. Traffic on Silicon Valley roads is up, and attendance at DesignCon this week was strong. Next comes the jobs.

By Ed Sperling

Mentor Graphics added SystemC support to its high-level synthesis Catapult C, basically trumping the competition in the HLS space. The advantage is that you can now run synthesis in the same language as high-level modeling. But given this is a game of leapfrog, don’t count on this lead to stay untouched.

Toshiba Information Systems standardized on Synopsys’ VMM-LP methodology, scoring one for the VMM side in what is often a contentious “non-war” between the non-rival verification methodologies OVM and VMM. And where is UVM in all of this?

Synopsys also expanded its IP portfolio with new 3G DigRF and Camera Serial Interface 2 controllers, and PHY for the Mobile Industry Processor Interface.

Atrenta inked a deal to develop an EDA tool quality management system with the Semiconductor Technology Academic Research Center in Japan. As part of the arrangement, STARC provided regression test specs and test cases to Atrenta, which has integrated them into its SpyGlass test suite.  STARC cut another deal with Cadence along similar lines.

In the standards world, Actel is now in compliance with the rigorous ISO 9001 and SAE/AS9100 standards, which mean its chips are now qualified for the most extreme conditions imaginable–and then some.

Ever wonder why Intel decided to build all those fabs in the desert? Check out the eight new solar operations the company is planning. Expected power generation is about 2.5 megawatts. Who needs power companies?

TSMC’s Q4 revenue increased 43% compared with the same quarter last year and net income increased 163%. That’s a lot of zeros in the right place. Either they were giving away wafers last year during the downturn or the number of companies developing chips at advanced nodes is way, way up.

By Ed Sperling

Actel’s ProASIC FPGAs are all over the new Boeing 787, which is supposed to be significantly more fuel-efficient than previous Boeing jets. Actel has been developing chips that use flash instead of SRAM to make them more resistant to single-event upsets caused by stray neutrons, which are about 150 times more prevalent at 35,000 feet than at sea level.

Synopsys began laying the groundwork for the next big market, namely India. The company’s VLSI design curriculum was adopted by five regional centers of excellence. This is similar to what many of the EDA players did in China at the beginning of the last decade.

AMD raked in $1.65 billion in sales in Q4, up 18% from the previous quarter and up 42% from the same period in 2008. The company also reported a profit of $1.18 billion. But dig a little further into the numbers and you find that Intel paid AMD $1.25 billion to settle its longstanding dispute. How long can AMD live on the Intel settlement and can it reach profitability on its own before the money runs out?

Rambus settled its longstanding patent infringement case against Samsung, taking home $900 million. But the bigger win may be a joint development deal between the companies to work together on a variety of new memory technologies.

By Ed Sperling

The new year is off to a gallop, which either means the economy is recovering or everyone took the holidays off and now they’re playing catch-up.

There were a barrage of press releases over the past week. While individually they look like the usual marketing, collectively they tell a different story—and probably the first really positive one since the downturn hit. Business is up, design activity is up, and executives are back to pitching financial success to Wall Street.

Virage Logic signed a partnership deal with eSilicon to become an IP partner in eSilicon’s value chain. Virage also inked a deal to provide its Sonic Focus software on IDT’s codecs for PCs. and another deal to license its ARC processor cores to Phison, which makes USB drives and memory controllers.

Canon is migrating its India Design Centre to OVM and is using Mentor’s Questa verification platform. Business is healthy in Asia.

Top execs are back on the road again doing more than just sales calls, too. CEOs from Synopsys (Aart de Geus) and Actel (John East) will be presenting at the Needham conference in New York next week.

And electronics companies began talking up the products that are running their latest technology at CES. ARM is showcasing its Cortex-A9 processor in an NXP set-top box  while MIPS is showcasing its cores in set-top boxes running Android.

Even jobs are beginning to return to the market, according to job boards. Some of this work is still on a consulting basis, but it’s at least a first step toward a broader recovery. Welcome to 2010.

By Ed Sperling

Arteris raised $9.7 million in a new “strategic” round of funding. While that may not seem like a lot of money, what’s far more interesting is who led that group—ARM and Qualcomm. Our take is that ARM thinks the NoC is a potential alternative to AMBA, the on-chip bus standard created by ARM, even though it won’t come out and say that. And Qualcomm is going to need NoCs to solve some of the complexity of power islands and multiple cores. Other investors are Synopsys and Japan’s giant DoCoMo Capital. This may speak volumes about the future of NoCs.

Mentor Graphics’ displaced workers program is the kind of industry involvement we need to see more of. So far, 452 engineers have taken classes through the program, and there are more classes available. Retooling is always a good idea, even if you’re not unemployed. For information, click here.

Synopsys was chosen by Hisilicon as its primary EDA partner. If the name sounds unfamiliar, just remember that Hisilicon is a subsidiary of Huawei—the Cisco of China. (There are some at Cisco who still insist that relationship is literal, even though Cisco dropped its IP theft lawsuit back in 2004.)

Actel updated its Q4 financial outlook. Revenues are expected to be right on target, which is up sequentially 2% to 6%. There’s nothing like hitting your numbers after a long recession.

Along the same lines, TSMC’s sales edged up 0.6% in November vs. October. If that doesn’t sound like much, consider that the foundry’s sales were down 17% for the first 10 months. November 2009 sales, incidentally, are 52% higher than November 2008. Break out the plastic cups.

TSMC is either feeling good about its numbers or looking for a hedge in the future–or both. The company invested $193 million in Motech Industries, a Taiwanese solar cell manufacturer that also owns its own fabs. In the recent downturn, though, solar didn’t work particularly well as a hedge strategy.

Mentor expanded its Questa multi-view verification components library to support the latest standards, including USB 3.0, Ethernet 40/100G and DDR2.

Cadence won a deal with AppliedMicro, which has standardized on Cadence’s Encounter platform.

By Ed Sperling

It was the best of times and it was the worst of times, but for EDA it was primarily the latter. And just how bad depended on whether you looked at the world from a GAAP (generally accepted accounting principles) perspective or a non-GAAP approach.

Mentor Graphics reported $189 million in revenue for fiscal Q3, ended Oct. 31, compared with $185 million in the same period in 2008. Non-GAAP earnings were 5 cents a share vs. a GAAP loss of 28 cents. Mentor said sales were up for test, place and route and DFM, and that the outlook for fiscal Q4, which ends Jan. 31, is about $220 million in revenue with non-GAAP earnings of 44 cents per share and GAAP earnings of 33 cents per share. For fiscal 2010 the company expects revenue to increase 1% from fiscal 2009 to $795 million.

Synopsys, meanwhile, posted revenue of $338 million for its fiscal Q4, also ended Oct. 31, compared with $353 million in the same period last year. On a GAAP basis, it showed a profit of 13 cents a share, while on a non-GAAP basis it was $1.75 per share—up slightly from 2008. Revenue targets for the quarter ending Jan. 31 are between $325 million and $333 million.

Cadence, whose Q3 ended on Sept. 30, reported revenue of $216 million compared with $232 million in 2008. On a non-GAAP basis, earnings were 3 cents a share, while on a GAAP basis the company lost 5 cents per share. And Magma, which seems to have overcome its near-death experience (at least as far as its auditors predicted), posted revenue of $30 million for its fiscal Q2, ended Nov. 1, with GAAP earnings of 9 cents a share compared with a loss last year of 60 cents a share. Non-GAAP earnings were 3 cents a share.

The picture presented by all the large EDA players is relatively flat, which is far better than in many other sectors. The companies that have done best—and the product areas within these companies that have fared best—are in areas where there is the most pain in the SoC development process. Private companies with tools that help reduce some of the complexity say they have been seeing solid growth throughout the past couple quarters.

On the non-financial side, Virage Logic shifted gears somewhat with its acquisition of ARC, moving into adaptive volume software, which keeps a consistent volume on computers and handsets. The feature is similar to what is offered by some television makers to keep the volume of commercials at the same level as regular programming. But while there are standards on television, there are none for other devices.

Atrenta won a deal with the Semiconductor Technology Academic Research Center (STARC) to integrate its constraints SDC equivalence verification into STARC’s production flow. Early design closure becomes more important at each new process node.

Intel stepped up its pressure on ARM, rolling out a developer kit for future netbook applications based upon its Atom processor. For the past couple months Intel has been making vague mention of an applications store to go along with the Atom, beginning next year, starting first with netbooks and then extending beyond netbooks to mobile devices such as smart phones and mobile Internet devices. Vendors will have their own storefronts in this mega department store, but how that works and whether it will be successful remains to be seen. Nevertheless, it wouldn’t be the first time a company stole a good idea from Apple and made a bundle off it.

TSMC is jumping into the automotive-grade semi world with a fab in Shanghai. While that may seem rather odd for TSMC—Taiwan Semiconductor Manufacturing Corp.—it’s a tacit recognition of where the majority of cars will be built and sold over the next decade.

Actel extended its popular 8051 core into the world of high-reliability aerospace applications, where cosmic radiation can wreak all sorts of havoc on chips. The big advantage of the strategy is that it leverages a much broader ecosystem than is normally available for military applications.

By Ed Sperling

The world is still full of engineers who can build fast interconnects to things like PCI Express or USB 2.0 who can create complex schematics for determining the connections between a processor core, memory, logic and various IP blocks on a piece of silicon. But over the next several years, many of those engineers will have to figure out new ways to make a living.

The number of companies that are jumping into pre-configured interconnect strategies—either through existing bus structures such as AMBA or the emerging network on chip approach—is growing rapidly. This is the latest trend in the disaggregation of the supply chain for systems on chip, using pre-configured approaches or high-level flexibility to plug in third-part components instead of developing everything in-house.

There are several reasons these approaches are gaining in popularity:

1. Complexity is making it harder to keep track of the interconnects, particularly in devices where there are multiple cores and multiple power islands that can be turned on and off.
2. Smaller staffs with targeted resources, or even the same size staff with more complex demands, are forcing design teams to put their resources where they can make a competitive difference rather than re-inventing something that is good enough and which adds no value.
3. Market windows are forcing companies to rethink their make vs. buy decisions, which is driving decisions about everything from intellectual property to restrictive layouts.

Riding the bus

One of the earliest standardized approaches to solving interconnects was the bus approach, and it remains popular in many chip designs today. ARM rolled out the Advanced Microcontroller Bus Architecture (AMBA) in 1996. AMBA is now in its third generation, with significantly improved speed over the first iteration. IBM developed its own CoreConnect standard for its Power chip architecture.

For chip developers, the nice thing about both bus architectures is that they’re free and well documented. AMBA 3.0 actually includes five different bus interfaces, most notably the Advanced High-performance Bus (AHB), which permits such things as burst transfers and split transactions, and the Advanced eXtensible Interface (AXI), which focuses on addressing and data phases. CoreConnect, meanwhile, includes a processor local bus, an on-chip peripheral bus and a device control register bus.

The advantage—and the disadvantage—of buses is that they’re hard-wired through a crossbar switch. While that guarantees a connection, there are fairly regimented ways of making those connections. For example, you can’t just connect a 32-bit IP core with a 64-bit interface without a converter, and you can’t just match up components with different frequency without using a clock converter.

“Ultimately, a bus performs the same task as a network on chip,” said Mike Dimelow, director of marketing for ARM’s processor division. “Their ways of solving the interconnect issue are different, though. They are both complementary and competitive with each other, but the problem they are trying to solve is the same—connectivity.”

They’re also a way of adding re-usability for IP, which is why Xilinx is now adding support for the AMBA bus architecture in its FPGAs—the last of the major FPGA vendors to support AMBA (both Actel and Altera have supported AMBA for years, while Xilinx backed the IBM CoreConnect approach). One of the attractive things about AMBA is its support for IP-XACT, the IP interoperability standard created by the SPIRIT Consortium (now part of Accellera).

“What this allows us to do is standardize on an interconnect scheme,” said Vin Ratford, senior vice president for worldwide marketing and business development at Xilinx. “FPGAs are a repository for a lot of IP. AMBA is one element for allowing more reusable IP.” (See Figure 1)

Figure 1: AMBA's IP connection (Source: ARM)

Adding flexibility

Building on the need for pre-configured connectivity, networks on chip have taken that approach a couple steps further by decoupling the transaction from the transport, and more recently decoupling the entire physical layer. The approach follows the broader networking world, where information is packetized into discrete bundles rather than maintaining a constant connection the way old telephone lines used to do. (For a look at life before packetization, check out some of old political thrillers where the telephone was kept off the hook one a connection was made to make sure that communication would not be interrupted.)

Decoupling of all those pieces allows a much more flexible design, and both Sonics and Arteris have been pitching the value of different NoC approaches. Sonics joined forces with Synopsys in June to create a pre-configured IP block that includes a memory scheduler and Synopsys’ Designware protocol controller IP. Arteris upped the ante in the NoC world in August, rolling out a peripheral NoC that instantly connects timers, USB, infrared interfaces and audio and touch-screen components.

The advantage of NoCs is a reduction in the number of wires and the flexibility of the design. “What this provides is ultimate flexibility,” said Geert Rosseel, chief technology officer at Arteris. “There is no topology or configuration you have to worry about up front, so in the end this can lead to truly smaller chips with higher frequency. You get big improvements with power, area and performance by using this approach.” (See Figure 2)

Figure 2: The NoC approach. (Source: Arteris)

That’s particularly useful from an architectural level when not all the functions or connectivity that ultimately will be required are known. In some cases, new standards or interfaces are completed before a chip reaches tapeout, and having the flexibility to add onto the design at a later stage is invaluable—particularly when the design will be used for a series of derivative chips.

ARM, meanwhile, is hedging its bets on both the bus and NoC. While it continues to update and support AMBA, its QoS now supports both, according to Dimelow.