By Ed Sperling
Mentor Graphics introduced its RealTime addition to Calibre for instant signoff verification in custom IC designs. What’s interesting is DRC checking at the layout stage of the design. Mentor also won a deal with CamSemi for its design and verification flow. And it added logic and physical synthesis support for Xilinx 7 series FPGAs.

Xilinx seems to be getting lots of attention these days. Synopsys added synthesis support for Xilinx’s ISE Design Suite 13.

eSilicon inked a deal with SMS, which will use eSilicon’s semiconductor manufacturing services business to produce its WiFi chips.

Arteris ran a note that TI is using the C2C and MIPI low-latency interfaces. Our guess is it has something to do with Arteris.  The company’s earnings were positive, too, as in cash-flow positive in 2010 and profitable in Q4. Looks like NoC technology is catching on.

Microsemi leveraged its Actel acquisition last year, rolling out a vertical suite of programmable FPGAs for intelligent management of solar panels in addition to Microsemi’s traditional DC-DC converters and MOSFETs. The company plans to follow suit in other vertical markets in coming months.

On the foundry front, TSMC sales dropped 7.8% between January and February, but they were still 8.8% higher than February 2010. It’s hard to figure out exactly what’s going on here as there are too many factors in play, including the recovery, Q4 buildup, and typical first-quarter uncertainty.

By Ed Sperling
Microsemi bought FPGA maker Actel for $430 million, extending its acquisition spree of discrete analog/mixed signal and defense systems to include programmable analog and low-power FPGAs. Prior to these acquisitions, many people in the semiconductor industry had never even heard of Microsemi. They’re certainly paying attention now.

Synopsys bought Optical Research Associates for an undisclosed sum, stepping quickly and rather firmly into an adjacent market for modeling electronics in the LED market. ORA software is used to design and optimize applications requiring light to be controlled or manipulated.

Mentor Graphics announced it was rolling out $20 million in debentures to qualified institutional buyers. The company will use $19.9 million of that amount for general corporate purposes. Does that mean more acquisitions?

TSMC said its net sales grew 0.4% between August and September. Growth is good. And just to put things in perspective, that’s up about 31% over September 2009.

By Ed Sperling
Mentor Graphics rolled out its Embedded ReadyStart platform, which includes an integrated suite of IP tools and services for popular hardware boards and SoCs. The platform integrates Mentor’s Nucleus RTOS. What’s particularly interesting about this announcement is it comes ready to work with Atmel and ARM-based products. Shay Benchorin, director of marketing and strategic alliances in Mentor’s Embedded Systems Division, said the company envisions a future in which low-power megaplatforms will become dominant because of the rising cost of development and the lack of expertise in low-power engineering. Differentiation will be added on top of those platforms by other SoC designers. If Mentor is correct, it’s certainly a good starting point.

Synopsys rolled out its HSPICE multithreading technology that it claims delivers up to seven times simulation speed up for analog/mixed signal designs. Speed is a good thing in large complex designs. It may interfere with those three-hour simulation-driven lunch breaks, though.

MIPS, Open-Silicon and Dolphin Technology successfully taped out a high-performance ASIC that runs at 2.4GHz. The companies say it’s one of the highest frequency ASIC processors ever built, based on the MIPS32 74K. This is the updated version of the 65nm 1.1GHz chip Open-Silicon and MIPS announced at the end of 2009. http://www.mips.com/news-events/newsroom/newsindex/index.dot?id=26336

Actel has created mixed-signal reference designs for motor control applications with its new SmartFusion chips. This is an interesting way to add some intelligence into motor control, which is one of the top three or four power-saving approaches that can make a huge difference. It ranks right up there with fluorescent light bulbs and mass transit systems. http://www.actel.com/company/press/2010/9/21/

By Ed Sperling
Intel unveiled a slew of announcements at the Intel Developers Forum (IDF). The most notable development was a deal to use Altera FPGAs in conjunction with Intel’s Atom chip, adding programmability outside the chip rather than trying to do everything with embedded software. If it’s successful, don’t be surprised if Intel starts cutting similar deals around its SoC development where platforms can be modified using an FPGA approach. It’s not quite as fast as having everything on the same chip, but not everything requires the same speed.

ARM likewise had a slew of announcements—which must have been a coincidence given the timing of IDF—that flex its international ecosystem leadership. ARM is collaborating with Dolby and India’s Ittiam in the audio sector.  Its Cortex-A9 processor is in a full computer-on-chip implementation from China’s Nufront. And it has hired a partner, FastCompanyBrazil, to make deeper inroads into Latin America’s growing tech market.

In the customer win category, Apache Design Solutions won a deal with Exar for its noise and reliability tools. Mentor’s DO-254 verification platform was adopted by the Civil Aviation University of China , Synopsys’ FastSPICE for circuit simulation was adopted by eMemory,  and Cadence’s silicon realization end-to-end product line was adopted by SMIC for 65nm to 40nm designs.  Global Unichip, the design services company in which TSMC has a major stake, also is using Cadence’s Encounter Timing System.

Synopsys introduced a serial advanced technology attachment IP solution for testing interoperability at process nodes ranging from 30nm to 40nm.

Actel, meanwhile, introduced its SmartFusion A2F500 development kit and said its largest SmartFusion Device is now in production using an ARM Cortex-M3 processor.

TSMC has begun building a thin-film solar R&D center and fab in central Taiwan.

By Ed Sperling
Cadence’s Richard Goering drills down into 3D ICs, which many companies think will be a game-changer. The reasons for their focus on 3D stacking varies, though, which may help to explain why one side doesn’t fit all. Some see huge performance benefits. Others are looking for re-usability.

Mentor’s Hollis Blanchard looks at ARM’s hardware virtualization. What’s particularly interesting is what appears to be a growing relationship between Mentor and ARM, which Blanchard hints at. Synopsys has been working closely with ARM for years, particularly with its standard interface IP. This could be like two boys asking the same girl to a dance and having her say ‘yes’ to both.

Synopsys’ Cary Chin investigates a big mystery, namely why some applications use more battery life than others. You should know about this stuff before trying to watch a movie on your iPad.

Daniel Nenni reviews the CEO panel at the GlobalFoundries event and notes the glaring absence of some of them while offering reviews for the two that did show up.

Cadence’s Team ESL—now there’s a new one for you—looks at the difference between latency and throughput. There must have been a recurring problem with this concept, but imagine what would happen if you really did confuse these two ideas. It would be like a Samuel Beckett play where you argue about why your e-mail is late—or whether you should even bother to send it.

And just in case you were wondering about Team ESL, there’s also a Team Verify at Cadence. Which team are you rooting for?

Mentor’s Colin Walls peels back the covers on the four modes of data transfer in USB. It’s probably not something you want to talk about at the kids’ soccer game, but it is interesting stuff for the right audience.

Synopsys’ Frank Schirrmeister asks an interesting question: Is it the applications driving the hardware or is it hardware that’s enabling applications? It depends who you ask. The folks over at Cadence have put out a manifesto on the subject.

But how many people actually read the Cadence manifesto, aka “EDA 360?” According to John Cooley’s research, not enough. Many engineers went looking for the executive summary of the 32-page document, which doesn’t exist. One anonymous engineer said it came down to a choice between Cadence and lunch and he chose lunch. The reality is that some people really do look forward to the food at conferences. There’s nothing like a fresh lunch for 10,000 people to make you forget about work.

Semico’s Tony Massimini looks at the tablet PC market and what that means to the netbook. Apparently it’s nothing to worry about, even for Intel. ARM might have a different take on that, however.

OVM providers are making the OVM Cookbook and the Examples Kit available for free via download, according to Mentor’s Dennis Brophy. Does anyone find it strange that there isn’t a UVM Cookbook?

Meanwhile, back on the VMM side, and deep down in the weeds, Vidyashankar Ramaswamy talks about using TCL to conditionally generate registers. No UVM here, either.

And finally, Actel’s Ted Speers explains what Speers’ Law really is. It’s the FPGA world’s answer to Moore’s Law. This one should at least make you smile.

By Ed Sperling
ARM took the covers off its new speedy Cortex-A15 chip, which is notable for several things. First, it includes virtualization technology, which allows cores to be used whenever needed—either for specific applications or for acceleration of those applications—and only when they’re needed. Second, it allows SoC developers to tweak the power/performance ratio for specific markets. And third, it includes multicore debug and trace. Intel gets its chance to respond next week at the Intel Developer Forum.

Silicon Image cut pin-limited test cost by 95% using Synopsys’ DFTMAX Compression. Expect to see more of this kind of news. The test market is getting very competitive, particularly in the mixed-signal and packaging arenas as designs get increasingly complex.

Actel confirmed its Q3 guidance that revenues will be up 3% to 7% sequentially. Numbers holding firm is a good thing, particularly when they’re pointing up and to the right.

TSMC‘s net sales rose 0.9% in August vs. July, which is a 26.3% increase compared with August 2009. Net sales were up 0.5%.

The Terminator…er, governor…helped Marvell launch a Smart-Electronics Initiative to increase awareness about energy consumption. It’s nice to see Arnold Schwarzenegger actively promoting Silicon Valley technology, considering it is one of the state’s biggest industries.

GlobalFoundries outlined its path for future process nodes and technology. This should be an interesting war of the titans between GF and TSMC.

Actel teamed up with Unison to create what it calls an “ultra tiny” Linux-compatible operating system for its SmartFusion chips. Considering Linux has been considered a memory and power hog, this is a major step forward for mixed signal FPGAs.

Two of the Big Three EDA vendors reported earnings for the past quarter. Numbers were relatively flat, but the outlook for the rest of the year is looking up.

Mentor Graphics turned in a respectable $187.9 million in revenue in Q2 compared with $182.6 million in the same period last year. For the quarter the company posted a non-GAAP income of $751,000 vs. $1.5 million in Q2 2009, or a GAAP loss of $14.2 million compared with $21.3 million in 2009. The earnings picture for Mentor is as complicated as its product lines. While the company showed growth in all of its top EDA products, it also grew in adjacent markets such as transportation. For Q3, Mentor expects revenue to grow to about $220 million and GAAP earnings to increase to 8 cents a share. Revenue for the full year is projected at $880 million with GAAP earnings of 20 cents per share.

Synopsys, meanwhile, posted revenue of $336.9 million for its fiscal Q3, which ended on July 31, compared with $345.2 million for the same period in 2009. On a GAAP basis, net income was $39.3 million compared with $47.4 million in 2009. Synopsys’ revenue targets for the next quarter are in the $349 million to $357 million range, which puts the company back on a solid growth curve.

In the IP world, MIPS joined forces with Hong Kong Science and Technology Parks Corp. to help startups with SoC designs in the Asia/Pacific region. A number of MIPS cores will be made available as part of Hong Kong Science’s pilot production programs.

And finally, on the full-chip level, Intel will acquire McAfee for $7.68 billion. The move raises more questions than it answers, particularly about what gets built into future Intel processors and what runs as software on top of it. With Intel increasingly leaning toward heterogeneous cores, this could be the first move by Intel into matching core sizes and power to the application—a move that could save significant power without sacrificing performance.

By Ed Sperling
You would have to be hiding in a cave without WiFi to miss the Synopsys acquisition of Virage Logic, which is due to go through in Synopsys’ fiscal Q4. This should turn Synopsys into an IP powerhouse and push it further into adjacent markets. And Synopsys still has a pile of cash remaining, so don’t think this is the end of the acquisition spree.

Case in point: At least some of the money leftover went to purchasing Synfora’s high-level synthesis technology. Considering Synopsys didn’t really have a play in the HLS market until last year, it has gained expertise in this area rather quickly. Synopsys’ push into software prototyping followed a similar pattern. There are three other big players in HLS, Mentor, Cadence and Forte. Synopsys doesn’t have enough cash to buy Mentor or Cadence, but there are plenty of rumors floating around about what company it can buy.

Mentor, meanwhile, is working on drumming up interest in HLS, which has been slow on the uptake for the better part of a decade. It introduced a high-level synthesis reference book, known as the HLS Blue Book. It’s everything you wanted to know about HLS–and it’s free.

Cadence is raising some big bucks on the side in a note-swapping deal that will provide millions to the company’s general fund. So far it hasn’t said what it’s going to do with that money, but given EDA stock prices these days Cadence may be gearing up to do some acquisitions of its own.

Mentor rolled out yet another addition to its Calibre DFM suite, this one aimed at fast and accurate extraction using 3D field solver technology. Translation: Calibre is a cash cow for Mentor and the company is making sure it stays that way.

All the big EDA companies seem to have some sort of announcement with TSMC this week. It might have something to do with the new flows that TSMC has introduced, including its analog/mixed signal reference flow 1.0. Synopsys validated its custom design solution with that flow and is working to validate Galaxy at 28nm for TSMC’s interoperable process design kit. Cadence likewise threw its support behind TSMC’s AMS 1.0 for 28nm. TSMC also included Apache Design Solutions’ power and noise solutions in two of its flows, including the AMS 1.0. And Mentor is working with TSMC on waivers for its design rule checks so previously waived IP doesn’t slow verification.

On the processor front, ARM introduced a virtual debug interface called VSTREAM that allows developers to stop the processor, view and change the value of registers and system memory. The tool works with both Mentor’s and Cadence’s emulation platforms, as well.

Actel is offering a free IP cores bundle and RTL package options with its standard software bundle. Until now most of the FPGA vendor giveaways were basic tools. This ups the ante by quite a bit.

By Ed Sperling
Mentor Graphics is working with NetLogic to use its embedded Linux with NetLogic’s multicore chips. Both companies are founding members of the eNsemble Multicore Alliance.

Synopsys released its financials for fiscal Q2. Revenue was up $1.3 million to $338.1 million vs. $336.8 million for the same period in 2009. Net income was down $9.8 million to $39.5 million compared with $48.3 million in 2009. At least some of that income hit can be explained by acquisition costs. The rest is still ramp-up time for new products coming out of the downturn.

MIPS, which has been a strong supporter of the Android platform, threw its support behind two more open architectures—the WebM open Web media project and the open source VP89 video codec. Given the current pressure to cut engineering costs and the robustness of the open source community these days, the strategy is certainly worth watching.

MoSys adopted Apache Design Solutions’ power integrity and noise tools for IP validation and model generation. MoSys makes IP for memory and I/O.

Things must be picking up in the mil/aero FPGA market. Actel introduced a development kit for system designers working with the ARINC 429 development platform for the avionics market.

Mentor also extended its Precision Synthesis FPGA tool in a number of directions, most notably adding mil/aero and safety-critical applications support and integration with other tools.

Cadence plunked down $315 million in cash for Denali (minus $45 million in cash that Denali has sitting in the bank), moving Cadence squarely into the IP business. Whether this is a good move or not is pure speculation. Denali is a private company. What is memory modeling IP worth? And more to the point, what is it worth to Cadence? On a side note, will the annual Denali party at DAC now become the Cadence party?

Arteris boosted its global distribution, naming a slate of execs to handle sales in various geographies and inking deals with distributors outside of North America and Europe. This is how a company that develops interconnects makes connections. It’s also a sign that it has reached critical mass.

Synopsys is collaborating with SMIC on USB PHY for the foundry’s 65nm low leakage process. Don’t count SMIC out. Looked at differently, it’s now a three-way race between Abu Dhabi (Global Foundries), Taiwan (TSMC and UMC) and China for commercial semiconductor manufacturing.

Apache Design Systems introduced its PathFinder tool to locate potential electrostatic discharge problems all the way up in the place-and-route phase of chip design. ESD is becoming a big problem at advanced nodes, and is expected to be a persistent thorn in 3D IC stacking.

Actel made a full portfolio of IP cores available for its SmartFusion mixed-signal FPGAs. This is an interesting way of reducing time to market while still allowing for modifications and future derivative chips.

Cavium Networks has adopted MIPS cores for its Octeon II multicore processors, which play across a wide swath of markets. Cavium, which started out making security chips, bought embedded Linux vendor MontaVista last year and has been pushing heavily into the Internet infrastructure world.

From the bellwether standpoint, just in case you haven’t come to grips with the fact that a recovery is well under way, TSMC’s April sales were up 6% from March and 50% from April 2009. What a difference a year makes.