Cadence took the covers off its software-driven approach to design called EDA 360. The company contends it’s not just about Cadence, but time will tell who else follows the company’s lead. It also announce a partnership with Wind River—not exactly shocking given the fact that some of the new upper management came from there—and its new Palladium XP that combines simulation, acceleration and emulation.

Mentor Graphics and Lauterbach inked a deal to jointly deliver a hardware-accelerated software development and debug platform for SoC verification. The deal combines Mentor’s Veloce emulation with Lauterbach’s debug tools.

Synopsys introduced universal DDR controllers that are both faster and which reduce the cost of embedded DRAM interfaces. The company says the new controllers reduce latency and silicon area by up to 50% vs. previous generations of its own controllers.

On the financial front, Actel announced Q1 earnings, showing revenue up 7.8% from the same period in 2009 and up 5.2% from Q4. Net income was $2.9 million, vs. a loss of $3 million in Q1 of 2009. http://www.actel.com/company/press/files/2010q1pr.pdf

Also showing positive gain, MIPS posted its fiscal Q3 results, ended March 10. Revenue was $17.5 million, up 15% sequentially and net income was $3.1 million, flat from the previous quarter and the same quarter in 2009. More telling, though, royalties were up 13% year over year and licensing revenue was up 42%.

ARM sailed into Q1 with $143.3 million in revenue compared with $120.9 million in the same quarter in 2009. Profits before tax were up 57% year over year. What downturn? http://www.arm.com/about/newsroom/arm-holdings-plc-reports-results-for-the-first-quarter-ended-31-march-2010.php

And Cadence reported revenue of $222 million, up from $206 million for the same period in 2009. Net loss was $12 million vs. $63 million in Q1 2009. Projections for next quarter continue to point toward a gain a revenue and a reduction in the loss—not to mention a profit in non-GAAP terms.

By Ed Sperling
eSilicon will acquire Silicon Design Solutions, which makes memory IP cores. SDS is headquartered in Silicon Valley, but it has design centers in Vietnam and Texas.

Apparently things were better than expected at Virage Logic. The company updated its guidance for the quarter, pushing its numbers upward by as much as $1 million. Executive chairman Daniel McCranie attributed the change to rapid integration of acquisitions, controlling spending and a “significant increase” in royalties. We all like that kind of news.

Synopsys rolled out DesignWare DDR multiPHY IP, fusing support for six different DDR standards in a single PHY. This is the IP version of a package deal. http://synopsys.mediaroom.com/index.php?s=43&item=789

Cadence won a deal with STMicroelectronics to use its OrCAD PSpice technology for evaluating analog and power ICs.

As strong as the FPGA market is in the United States and Europe, it’s exploding in places like China and India. Proof point: Actel’s 24 x 5 technical support. It’s not that chip engineers work the same kind of hours as software developers—the Mountain Dew swigging night owls. But they do work in a lot of different time zones these days.

By Ed Sperling

It was a busy week for Mentor Graphics. The company scored another DFM win, this time from SMIC, the Shanghai-based foundry. SMIC will use Calibre for signoff for 65nm and below. It also set up a shared emulation resource with Platform Computing.  And perhaps even more important, one of its development engineering managers, Vladimir Szekely won an award from the Hungarian Parliament for advanced transient temperature equipment.

Actel extended its SmartFusion FPGAs up into carrier-grade equipment with programmable ATCA systems, which is an interesting move for this market. In the past, most of the ATCA solutions involved swap-in modules in a standard chassis. This adds analog programmability for the first time through Actel’s Pigeon Point subsidiary.

Synopsys rolled out Design Compiler 2010 for its Galaxy flow. The company says the new tool will double the productivity of RTL synthesis and place and route.

Virage Logic teamed up with MIPS to offer optimized embedded memory IP for their joint customers. So who are the joint customers? Think set-top boxes and broadband.

Cadence added a couple dozen new companies to its ChipEstimate planning and IP portal. Virage and Xilinx ramped up their support.

eSilicon CEO Jack Harding was re-elected to the GSA board for the first time as a value chain producer, a new category created by the GSA to include eSilicon. It’s a good thing he got elected.

By Ed Sperling
The consolidation of intellectual property from small developers to large players with integrated IP blocks is accelerating. Large IP companies are now developing integrated suites that are pre-tested for specific vertical markets, and new companies are sprouting up to make it easier to put even broader collections of IP together in meaningful ways.

It’s difficult to tell whether the trend is being driven more by the IP vendors or pulled through by chip developers looking to cut costs—or whether it builds upon the stamp of approval by foundries for certain pieces of IP. The net effect, however, is the creation of subsystems and partial platforms that are one step below reference platforms.

“A reference design suggests a complete solution,” said Eric Schorn, vice president of marketing for ARM’s processor division. “Customers don’t want us to go that far. But we are moving in a segment-oriented fashion. That’s the reason we bought a graphics processor company. We are making a processor along with a graphics socket for mobile phones and set-top boxes.”

The company isn’t alone in recognizing the opportunity for putting together more pieces of IP in very specific ways. Virage Logic’s recent acquisitions of ARC and NXP’s IP unit have positioned it to lead with integrated subsystems in markets such as high-performance audio and video.

“You have to have a reference platform these days,” said Yankin Tenurhan, vice president and general manager of Virage’s ARC business unit. “That’s not much different from the good old days of silicon, though, when you needed a complete solution and a full blown prototype. Philips, NXP, Texas Instruments and ST all have demonstrator chips for whatever you want on a cell phone. The same is happening in the IP world.”

Putting together the pieces
It’s not just the IP vendors that are putting together suites of IP. Two startups are focused on making IP easier to understand and integrate. Parallel Engines, which emerged from stealth mode this week, is focused on organizing IP by data mining pertinent information about everything from power requirements to the interfaces and interconnects.

“There are 12,000 pieces of IP out there, including 8,000 pieces of hard IP that are made by about 50 companies and about 4,000 pieces of soft IP,” said George Janac, CEO of Parallel Engines. “The hard IP is already in FPGAs from companies like Actel, Xilinx and Altera. You just need the soft IP to make it work.”

Somewhat conveniently, Janac’s brother, Charlie, is the CEO of Arteris, which makes network on chip technology that can be used to glue together these IP blocks.

“A company may have one or two pieces of IP that are the secret sauce and some software,” Charlie Janac said. “Why not drop those into an FPGA and connect up the other pieces of IP? Those two worlds are merging. We’re going to see much more custom logic on an FPGA.”

Another company involved in bringing IP together is Silicon IP, run by Kurt Wolf (formerly of TSMC), who said there’s a disconnect between chipmakers and IP vendors that still needs to be closed. “The chip guys distrust the IP industry,” Wolf said. “There’s more integration of IP, but there’s still a lack of confidence about how to choose, buy and license IP.”

Wolf’s company is focused more on bringing the two sides together with better information and connecting the pieces in an organized way.

The future
All of these efforts—by both large IP vendors and startups—are signs of just how important commercial IP has become in chip development. What began with embedded processors and standard memory designs has evolved into a huge market that actually gained momentum in the recent downturn.

Outsourcing is gaining ground at every level of business, even outside of the semiconductor world, but in the past most of the gains have been in areas where there was little value add. Outsourcing traditionally has been relegated to commodity services. What’s changing is that IP now includes areas that companies cannot do themselves in addition to those they don’t want to do, as well as the extremely tedious and time-consuming integration work that is necessary to create a final product.

When most analysts predicted a massive growth in IP at the beginning of the decade they were largely talking about small, relatively unsophisticated IP blocks pieces that can be put together by highly sophisticated companies. In the future, the differentiation may be less around the technology and more on getting very complex chips assembled and to market faster for specific market segments.

By Ed Sperling

It was a good week for thinking out of the package.

Mentor Graphics acquired Valor Computerized Systems, a recognition that system problems now extend well beyond the chip. Valor’s expertise is in PCB software and DFM. The purchase price was about $50 million, including $32.5 million in cash and 5.6 million shares of Mentor stock. Interestingly, Valor’s revenue for 2008—the last full year it reported—was about $40 million.

Mentor also inked a three-year joint-development deal with STMicroelectronics to develop advanced SoC design solutions down to 20nm.

Actel appears to be benefiting from its new SmartFusion rollout. The company updated guidance, saying Q1 revenue will be up 4% to 8%, instead of 2% to 6% it had previously reported. http://www.actel.com/company/press/files/busupdateQ110.pdf

Cadence is expanding its academic network in Europe, adding three universities from Bucharest, Stockholm and Braunschweig for everything from PCB design to low-power methodology.

Intel rolled out its first six-core 32nm Xeon chip for servers, claiming it offers 60% more performance for the same power consumption of 130 watts. Versions of the chips with lower clock speeds can use as little as 40 watts.

By Ed Sperling

Synopsys is teaming up with Imec, the Belgian research lab, to help solve the problems of 3D IC stacking and through-silicon vias. This is important stuff for re-use of older technologies, not to mention cutting verification time and achieving timing closure and getting chips to market on time and improving yield and…well, you get the idea. Synopsys also added design-rules-driven technology to Galaxy Custom Designer that helps speed DRC repair tasks.

Mentor Graphics added Amba 4 verification IP to its Questa library. Given the growing popularity of ARM’s processor, this is a necessary step—especially with Mentor’s commitment to the Android phone.

Actel got its first public endorsement of its new SmartFusion chip. Micrium is porting its embedded software stack to the mixed-signal FPGA. Micrium’s software is targeted at the ARM Cortex-M processor line.

TSMC sales were up 0.1% from January to February, which isn’t much. But when you consider that’s 144% higher than last year it starts putting things in perspective. Still, it would be nice to have a breakdown by process nodes.

By John Blyler & Ed Sperling
Is the Electronic Design Automation (EDA) tools market shrinking or growing? That depends greatly upon how you define EDA.

A recent report by the Global Industry Analysts, based on information from EDA Consortium (EDAC), predicts that the global EDA tool market eventually will re-emerge to drive growth to $9.8 Billion by 2015. The report suggests that this growth will be fueled in part by the traditional efforts to improve efficiency and performance throughout the chip development process.

EDA Chip-Level Tools
Aart de Geus, chairman and CEO of Synopsys, expanded upon this finding in a recent interview. “As a percentage of our business, classic EDA is shrinking, but this is not a case of ‘classic EDA doesn’t grow.’” For example, in the past, EDA companies added front-end RTL synthesis and design tools with timing and power closure to improve the productivity of chip designers. Next, efficiencies were found in the back-end of the process by adding physical design with extraction and Design for Manufacturing (DFM) and Yield (DFY) tools. Today, EDA vendors are improving the value of system-level design with architectural tools.

Synopsys is indeed attempting to improve their architecture tool flow with the recent double acquisitions of two electronic-system level (ESL) design companies – VaST and CoWare. The emphasis on architectural integrated circuit (IC) design productivity has pushed traditional EDA chip companies to expand into the next level of product development, namely, package and board design and – on the software side – even application development.

But this time around, productivity and efficiency within the chip development process will not be enough to save EDA. In addition to continuing improvements in both front and back-end tool design, chip-level EDA companies must be successful in reaching outward to embrace new customers and industries.

Perhaps no one understands this shift in thinking better than Mentor Graphics, who has products in the chip, package, board and even embedded real-time operating system (RTOS) markets. “We (EDA chip tools) as an industry are stubbornly targeting a limited number of customers,” said Serge Leef, vice president of new ventures and General Manager of the System-Level Engineering Division at Mentor Graphics. “We really need to figure out where to go beyond that.”

There are four choices, according to Leef. One is to sell products to existing customers, which EDA companies will continue to do. The second is to sell new products to existing customers, which they are attempting in areas such as submicron design, DFM and yield enhancement. A third option is to sell existing products to new customers in places like China and India, but most of those companies are either part of multinational companies that already buy EDA tools or they’re underfunded startups that cannot afford tools. A fourth option is to sell new products to new customers.

On paper, the last option seems the most promising. The problem is getting the new customers to look at what EDA has to offer, which means that EDA companies must understand the needs of the new customers – i.e., different industries.

IP Drives Profit
A universal need shared by most new customers in today’s economically challenged markets is that of cost reduction. This has two effects. One is to increase the use of intellectual property (IP) blocks in chip-level design while the other is to move from ASIC to FPGA-based designs.

Increasing the use of IP was a primary theme in Virage Logic’s keynote address at the recent DesignCon show. That was expected, but the arguments that were used to support the growth of IP are worth noting. Brani Buric, executive vice president for marketing and sales at Virage, explained it this way: “As we move into consumer markets with low profit margins we must think beyond the technical challenges to the business issues. The question is not just how to do the design more efficiently in terms of cost, but whether to do the design at all.”

The business focus of this approach is reflected in its name, i.e., Design for Profitability (DFP). Companies focusing on profit might just write the spec for a new chip, then hand off the rest of the design and implementation to design companies such as eSilicon or Open-Silicon. Owning the spec would typically be a lot less expensive than owning any part of the implementation process. This approach relies heavily on IP blocks to build the chip to spec.

Interestingly, the growth of IP is one of the key drivers cited by in the Global Industry Analysts report for overall EDA growth. The reason that EDA tool revenues are expected to climb in 2015 is because EDA owns IP. By including Broadcom, Qualcomm and ARM as some of the largest IP licensing companies, EDA will indeed be one of the fastest growing sectors—at least on paper. The reasoning for this inclusion, according to EDAC, is that EDA tools are an integral part of licensing the IP, so IP licensing revenues should be counted in the EDA business calculations.

EDA in the Board-Level Market
The growing reliance on FPGA-based electronics is the second trend driven by profit-focused designs. But this is another area where companies like Actel, Xilinx and Altium are trying to engage a broader customer base, e.g., medical, industrial and automotive markets.

Actel’s purchase of Pigeon Point moves that company squarely into the Advanced TCA and MicroTCA world, which has been heavily utilized by communications companies and defense. Xilinx, meanwhile, is positioning its next-generation 28nm FPGA platform to help win business in non-traditional markets. And Altium has been focusing on a single database implementation of FPGA-based, board-level products that include embedded software development.

While all of these expansions reflect broader changes in the overall semiconductor industry, real growth in the EDA sector can only come from expansion beyond traditional markets. But there will always be a nagging question facing EDA companies moving into these new markets: Is this really EDA, or are we venturing into a new sector that reaches well beyond the confines of EDA to include a true system-level approach?

By Ed Sperling

Money is flowing again. Sometimes into companies, sometimes out of companies. But at least it’s moving.

Synopsys bought VaST Systems for an unknown price, but it doesn’t appear it was a vast amount of money. Synopsys said it didn’t materially affect its numbers, which means it fell well below the radar screen. Apparently it’s tough to break into the software prototyping market without serious integration with other tools in a flow. This builds on Synopsys’ acquisition of Virtio in 2006.

Virage Logic’s revenue for Q1 of its fiscal 2010 was $21.7 million, up from $11.3 million in the same quarter in 2009 and $13.1 million in Q4. The company reported a loss for the quarter of $2.2 million, but that loss reflects the costs of recent acquisitions. Minus those charges, profit would have been $900,000. More significant for Virage, royalty income for Q1 was $4.7 million vs. $2.8 million in the same period in 2009, a sign that companies are building chips again and licensing IP to get to market more quickly.

Actel posted a profit in Q4 2009 vs. the same period in 2008, despite a drop in overall revenue. Net income was $1 million in the quarter, vs. a loss of $12.5 million during the same period in 2008. Revenue was $49.7 million in Q4 2009, down 5.8% from 2008, but up 5.2% from Q3 2009. For the full fiscal year revenue was $190.6 million, down 12.7% from fiscal 2008. The company expects revenues in the current quarter to rise 2% to 6% compared to Q4.

Actel also announced that its president and CEO, John East, would step down once a replacement is found. East, who is 65 years old, will continue serve as a consultant through August 2011, after which he will retire. He has led the company for the past two decades.

Things were modestly upbeat at Cadence for the first time in months. The company reported financial results for Q4 and fiscal year 2009. In Q4 revenues slipped to $220 million vs. $227 million in 2008, but net income was $2 million vs. a loss of $1.63 billion (!) in the same period in 2008. It must be nice to write in black ink again. The Q4 2008 loss included a $1.36 billion “impairment charge.” For the 12 months, revenue was $853 in 2009 vs. $1.04 billion in 2008. Net loss for 2009 was $150 million vs. $1.86 billion including that one-time charge (or $500 million without that charge).

The bottom line—the worst is over. Traffic on Silicon Valley roads is up, and attendance at DesignCon this week was strong. Next comes the jobs.

By Ed Sperling

Mentor Graphics added SystemC support to its high-level synthesis Catapult C, basically trumping the competition in the HLS space. The advantage is that you can now run synthesis in the same language as high-level modeling. But given this is a game of leapfrog, don’t count on this lead to stay untouched.

Toshiba Information Systems standardized on Synopsys’ VMM-LP methodology, scoring one for the VMM side in what is often a contentious “non-war” between the non-rival verification methodologies OVM and VMM. And where is UVM in all of this?

Synopsys also expanded its IP portfolio with new 3G DigRF and Camera Serial Interface 2 controllers, and PHY for the Mobile Industry Processor Interface.

Atrenta inked a deal to develop an EDA tool quality management system with the Semiconductor Technology Academic Research Center in Japan. As part of the arrangement, STARC provided regression test specs and test cases to Atrenta, which has integrated them into its SpyGlass test suite.  STARC cut another deal with Cadence along similar lines.

In the standards world, Actel is now in compliance with the rigorous ISO 9001 and SAE/AS9100 standards, which mean its chips are now qualified for the most extreme conditions imaginable–and then some.

Ever wonder why Intel decided to build all those fabs in the desert? Check out the eight new solar operations the company is planning. Expected power generation is about 2.5 megawatts. Who needs power companies?

TSMC’s Q4 revenue increased 43% compared with the same quarter last year and net income increased 163%. That’s a lot of zeros in the right place. Either they were giving away wafers last year during the downturn or the number of companies developing chips at advanced nodes is way, way up.

By Ed Sperling

Actel’s ProASIC FPGAs are all over the new Boeing 787, which is supposed to be significantly more fuel-efficient than previous Boeing jets. Actel has been developing chips that use flash instead of SRAM to make them more resistant to single-event upsets caused by stray neutrons, which are about 150 times more prevalent at 35,000 feet than at sea level.

Synopsys began laying the groundwork for the next big market, namely India. The company’s VLSI design curriculum was adopted by five regional centers of excellence. This is similar to what many of the EDA players did in China at the beginning of the last decade.

AMD raked in $1.65 billion in sales in Q4, up 18% from the previous quarter and up 42% from the same period in 2008. The company also reported a profit of $1.18 billion. But dig a little further into the numbers and you find that Intel paid AMD $1.25 billion to settle its longstanding dispute. How long can AMD live on the Intel settlement and can it reach profitability on its own before the money runs out?

Rambus settled its longstanding patent infringement case against Samsung, taking home $900 million. But the bigger win may be a joint development deal between the companies to work together on a variety of new memory technologies.