By Ed Sperling

The new year is off to a gallop, which either means the economy is recovering or everyone took the holidays off and now they’re playing catch-up.

There were a barrage of press releases over the past week. While individually they look like the usual marketing, collectively they tell a different story—and probably the first really positive one since the downturn hit. Business is up, design activity is up, and executives are back to pitching financial success to Wall Street.

Virage Logic signed a partnership deal with eSilicon to become an IP partner in eSilicon’s value chain. Virage also inked a deal to provide its Sonic Focus software on IDT’s codecs for PCs. and another deal to license its ARC processor cores to Phison, which makes USB drives and memory controllers.

Canon is migrating its India Design Centre to OVM and is using Mentor’s Questa verification platform. Business is healthy in Asia.

Top execs are back on the road again doing more than just sales calls, too. CEOs from Synopsys (Aart de Geus) and Actel (John East) will be presenting at the Needham conference in New York next week.

And electronics companies began talking up the products that are running their latest technology at CES. ARM is showcasing its Cortex-A9 processor in an NXP set-top box  while MIPS is showcasing its cores in set-top boxes running Android.

Even jobs are beginning to return to the market, according to job boards. Some of this work is still on a consulting basis, but it’s at least a first step toward a broader recovery. Welcome to 2010.

By Ed Sperling

Arteris raised $9.7 million in a new “strategic” round of funding. While that may not seem like a lot of money, what’s far more interesting is who led that group—ARM and Qualcomm. Our take is that ARM thinks the NoC is a potential alternative to AMBA, the on-chip bus standard created by ARM, even though it won’t come out and say that. And Qualcomm is going to need NoCs to solve some of the complexity of power islands and multiple cores. Other investors are Synopsys and Japan’s giant DoCoMo Capital. This may speak volumes about the future of NoCs.

Mentor Graphics’ displaced workers program is the kind of industry involvement we need to see more of. So far, 452 engineers have taken classes through the program, and there are more classes available. Retooling is always a good idea, even if you’re not unemployed. For information, click here.

Synopsys was chosen by Hisilicon as its primary EDA partner. If the name sounds unfamiliar, just remember that Hisilicon is a subsidiary of Huawei—the Cisco of China. (There are some at Cisco who still insist that relationship is literal, even though Cisco dropped its IP theft lawsuit back in 2004.)

Actel updated its Q4 financial outlook. Revenues are expected to be right on target, which is up sequentially 2% to 6%. There’s nothing like hitting your numbers after a long recession.

Along the same lines, TSMC’s sales edged up 0.6% in November vs. October. If that doesn’t sound like much, consider that the foundry’s sales were down 17% for the first 10 months. November 2009 sales, incidentally, are 52% higher than November 2008. Break out the plastic cups.

TSMC is either feeling good about its numbers or looking for a hedge in the future–or both. The company invested $193 million in Motech Industries, a Taiwanese solar cell manufacturer that also owns its own fabs. In the recent downturn, though, solar didn’t work particularly well as a hedge strategy.

Mentor expanded its Questa multi-view verification components library to support the latest standards, including USB 3.0, Ethernet 40/100G and DDR2.

Cadence won a deal with AppliedMicro, which has standardized on Cadence’s Encounter platform.

By Ed Sperling

It was the best of times and it was the worst of times, but for EDA it was primarily the latter. And just how bad depended on whether you looked at the world from a GAAP (generally accepted accounting principles) perspective or a non-GAAP approach.

Mentor Graphics reported $189 million in revenue for fiscal Q3, ended Oct. 31, compared with $185 million in the same period in 2008. Non-GAAP earnings were 5 cents a share vs. a GAAP loss of 28 cents. Mentor said sales were up for test, place and route and DFM, and that the outlook for fiscal Q4, which ends Jan. 31, is about $220 million in revenue with non-GAAP earnings of 44 cents per share and GAAP earnings of 33 cents per share. For fiscal 2010 the company expects revenue to increase 1% from fiscal 2009 to $795 million.

Synopsys, meanwhile, posted revenue of $338 million for its fiscal Q4, also ended Oct. 31, compared with $353 million in the same period last year. On a GAAP basis, it showed a profit of 13 cents a share, while on a non-GAAP basis it was $1.75 per share—up slightly from 2008. Revenue targets for the quarter ending Jan. 31 are between $325 million and $333 million.

Cadence, whose Q3 ended on Sept. 30, reported revenue of $216 million compared with $232 million in 2008. On a non-GAAP basis, earnings were 3 cents a share, while on a GAAP basis the company lost 5 cents per share. And Magma, which seems to have overcome its near-death experience (at least as far as its auditors predicted), posted revenue of $30 million for its fiscal Q2, ended Nov. 1, with GAAP earnings of 9 cents a share compared with a loss last year of 60 cents a share. Non-GAAP earnings were 3 cents a share.

The picture presented by all the large EDA players is relatively flat, which is far better than in many other sectors. The companies that have done best—and the product areas within these companies that have fared best—are in areas where there is the most pain in the SoC development process. Private companies with tools that help reduce some of the complexity say they have been seeing solid growth throughout the past couple quarters.

On the non-financial side, Virage Logic shifted gears somewhat with its acquisition of ARC, moving into adaptive volume software, which keeps a consistent volume on computers and handsets. The feature is similar to what is offered by some television makers to keep the volume of commercials at the same level as regular programming. But while there are standards on television, there are none for other devices.

Atrenta won a deal with the Semiconductor Technology Academic Research Center (STARC) to integrate its constraints SDC equivalence verification into STARC’s production flow. Early design closure becomes more important at each new process node.

Intel stepped up its pressure on ARM, rolling out a developer kit for future netbook applications based upon its Atom processor. For the past couple months Intel has been making vague mention of an applications store to go along with the Atom, beginning next year, starting first with netbooks and then extending beyond netbooks to mobile devices such as smart phones and mobile Internet devices. Vendors will have their own storefronts in this mega department store, but how that works and whether it will be successful remains to be seen. Nevertheless, it wouldn’t be the first time a company stole a good idea from Apple and made a bundle off it.

TSMC is jumping into the automotive-grade semi world with a fab in Shanghai. While that may seem rather odd for TSMC—Taiwan Semiconductor Manufacturing Corp.—it’s a tacit recognition of where the majority of cars will be built and sold over the next decade.

Actel extended its popular 8051 core into the world of high-reliability aerospace applications, where cosmic radiation can wreak all sorts of havoc on chips. The big advantage of the strategy is that it leverages a much broader ecosystem than is normally available for military applications.

By Ed Sperling

The world is still full of engineers who can build fast interconnects to things like PCI Express or USB 2.0 who can create complex schematics for determining the connections between a processor core, memory, logic and various IP blocks on a piece of silicon. But over the next several years, many of those engineers will have to figure out new ways to make a living.

The number of companies that are jumping into pre-configured interconnect strategies—either through existing bus structures such as AMBA or the emerging network on chip approach—is growing rapidly. This is the latest trend in the disaggregation of the supply chain for systems on chip, using pre-configured approaches or high-level flexibility to plug in third-part components instead of developing everything in-house.

There are several reasons these approaches are gaining in popularity:

1. Complexity is making it harder to keep track of the interconnects, particularly in devices where there are multiple cores and multiple power islands that can be turned on and off.
2. Smaller staffs with targeted resources, or even the same size staff with more complex demands, are forcing design teams to put their resources where they can make a competitive difference rather than re-inventing something that is good enough and which adds no value.
3. Market windows are forcing companies to rethink their make vs. buy decisions, which is driving decisions about everything from intellectual property to restrictive layouts.

Riding the bus

One of the earliest standardized approaches to solving interconnects was the bus approach, and it remains popular in many chip designs today. ARM rolled out the Advanced Microcontroller Bus Architecture (AMBA) in 1996. AMBA is now in its third generation, with significantly improved speed over the first iteration. IBM developed its own CoreConnect standard for its Power chip architecture.

For chip developers, the nice thing about both bus architectures is that they’re free and well documented. AMBA 3.0 actually includes five different bus interfaces, most notably the Advanced High-performance Bus (AHB), which permits such things as burst transfers and split transactions, and the Advanced eXtensible Interface (AXI), which focuses on addressing and data phases. CoreConnect, meanwhile, includes a processor local bus, an on-chip peripheral bus and a device control register bus.

The advantage—and the disadvantage—of buses is that they’re hard-wired through a crossbar switch. While that guarantees a connection, there are fairly regimented ways of making those connections. For example, you can’t just connect a 32-bit IP core with a 64-bit interface without a converter, and you can’t just match up components with different frequency without using a clock converter.

“Ultimately, a bus performs the same task as a network on chip,” said Mike Dimelow, director of marketing for ARM’s processor division. “Their ways of solving the interconnect issue are different, though. They are both complementary and competitive with each other, but the problem they are trying to solve is the same—connectivity.”

They’re also a way of adding re-usability for IP, which is why Xilinx is now adding support for the AMBA bus architecture in its FPGAs—the last of the major FPGA vendors to support AMBA (both Actel and Altera have supported AMBA for years, while Xilinx backed the IBM CoreConnect approach). One of the attractive things about AMBA is its support for IP-XACT, the IP interoperability standard created by the SPIRIT Consortium (now part of Accellera).

“What this allows us to do is standardize on an interconnect scheme,” said Vin Ratford, senior vice president for worldwide marketing and business development at Xilinx. “FPGAs are a repository for a lot of IP. AMBA is one element for allowing more reusable IP.” (See Figure 1)

Figure 1: AMBA's IP connection (Source: ARM)

Adding flexibility

Building on the need for pre-configured connectivity, networks on chip have taken that approach a couple steps further by decoupling the transaction from the transport, and more recently decoupling the entire physical layer. The approach follows the broader networking world, where information is packetized into discrete bundles rather than maintaining a constant connection the way old telephone lines used to do. (For a look at life before packetization, check out some of old political thrillers where the telephone was kept off the hook one a connection was made to make sure that communication would not be interrupted.)

Decoupling of all those pieces allows a much more flexible design, and both Sonics and Arteris have been pitching the value of different NoC approaches. Sonics joined forces with Synopsys in June to create a pre-configured IP block that includes a memory scheduler and Synopsys’ Designware protocol controller IP. Arteris upped the ante in the NoC world in August, rolling out a peripheral NoC that instantly connects timers, USB, infrared interfaces and audio and touch-screen components.

The advantage of NoCs is a reduction in the number of wires and the flexibility of the design. “What this provides is ultimate flexibility,” said Geert Rosseel, chief technology officer at Arteris. “There is no topology or configuration you have to worry about up front, so in the end this can lead to truly smaller chips with higher frequency. You get big improvements with power, area and performance by using this approach.” (See Figure 2)

Figure 2: The NoC approach. (Source: Arteris)

That’s particularly useful from an architectural level when not all the functions or connectivity that ultimately will be required are known. In some cases, new standards or interfaces are completed before a chip reaches tapeout, and having the flexibility to add onto the design at a later stage is invaluable—particularly when the design will be used for a series of derivative chips.

ARM, meanwhile, is hedging its bets on both the bus and NoC. While it continues to update and support AMBA, its QoS now supports both, according to Dimelow.

By Geoffrey James

Until a few years ago, SoC designers focused almost exclusively on ASICs. While it was theoretically possible to create an SoC design for an FPGA, the programmable chips were too bulky and pricey to be useful for much more than prototyping. Today, however, designers are increasingly turning to FPGAs for their SOC targets for production systems.

Why the sudden upsurge in SoCs on FPGAs? The answer, as usual, is Moore’s Law – and the design hassles it creates. ASIC designs at sub-65nm are becoming increasingly expensive to develop. And turning an ASIC design into physical silicon can take months, so if there’s a design flaw that’s elapsed time that could mean missing a market window. By contrast, FPGAs offer SoC designers the flexibility to tinker and test without the expense and risk of a manufacturing run.

Even so, there’s more than economics at play here. Four key technical trends have conspired to make FPGAs more viable as a platform for serious SoC production.

Trend #1: Today’s FPGAs are gaining features appropriate for SoCs.

In the past, FPGA were often implemented as an element in a larger chip set that would be integrated on a board. Standard functions were relegated to other (smaller) chips, while the FPGA (which was hefty by comparison) carried the part of the design unique to the end product. This tended to make FPGA designs expensive because the FPGA chip was more expensive than a comparable ASIC and the additional chips and assembly added additional design and manufacturing costs.

Today, however, FPGAs are much smaller and more efficient than before. Xilinx, for instance, makes FPGAs at 40nm, while Actel has developed a 65nm version with flash memory. Though FPGA circuitry still takes up more physical space than non-programmable circuitry, at 65nm and below there is more than enough raw circuitry to support a wide range of designs.

“We see FPGAs as a major vehicle for innovation among our customers, who have used it to develop capabilities that we were later able to incorporate inside our standard products,” says Pranav Mehta, CTO of Intel’s embedded and communications group.

Newer FPGAs also include standard functions such as USB communications, sometimes encapsulated inside “hardened” (i.e. non-programmable) portions of the chip. Some FPGAs even have CPU cores built into them or support special versions of CPU cores (such as an ARM processor) that can run inside the programmable portion of a hybrid FPGA.

“The inclusion of advanced features makes FPGAs strong candidates for even complex SoC designs,” says John Swanson, senior manager of the solutions group at Synopsys.

Trend #2: The FPGA tool sets are becoming more sophisticated.

Programming FPGAs originally involved using rudimentary tool sets provided by the FPGA maker. However, as FPGAs (and the applications on them) have gotten more complex, EDA firms have come to the assistance of designers with better FPGA development tools. Forte Design Systems, for example, provides an ESL design environment that supports FPGAs as effectively as ASICs, according to Brett Cline, the company’s vice president of marketing and sales. “We have one client who is doing seven designs, three of which are targeted at FPGAs,” he explains. “We even have one client who is porting an ASIC design back onto an FPGA for further development.”

The traditional EDA vendors have taken FPGA more seriously over the years because their customers demanded it, according to Daniel Platzker, the product line director for FPGA synthesis products at Mentor Graphics. “While FPGA tools have been around inside Mentor since 1992, it’s become a major market for us in the areas of synthesis, verification and simulation,” he says. (See Figure 1)

Fig. 1: Mentor Graphics' FPGA design environment.

Andy Biddle, director of business development at Magma agrees. “We see even customers using FPGAs to develop mix-signal designs that previously would have been difficult or impossible,” he says.

The demand for better tools was spawned by the fact that newer FPGAs can experience some of the same challenges that occur in ASICs. “These designs get so complex that it’s necessary to have professional-grade routing tools, for instance, to ensure that the chip doesn’t run into any problems with timing and closure,” says Juergen Jaeger, director of marketing, for the Confirma rapid prototyping platform at Synopsys.

Trend #3: SoCs are proliferating into a wider range of products.

As sophisticated electronics get built into an ever-wider variety of devices, it’s creating an almost insatiable demand for FPGA-style SoCs. “Designers in third-world countries work in environments that won’t support and can’t afford a full ASIC development process,” explains EDA analyst Gary Smith of GarySmithEDA.com. “In order to save money, they’re using FPGAs in everything from vacuum cleaners to fans to pumps.”

FPGAs also are showing up in products elsewhere in the industrialized world, according to Tom Feist, senior director of marketing for IP products at Xilinx. “We’re seeing substantial FPGA interest in the automotive industry for SoCs that can be easily upgraded to handle new features, like shape recognition and object avoidance,” he explains. (See Figure 2)

Relative markets for FPGAs vs. ASICs

Given the wealth of potential markets, it’s probably not surprising that the number of FPGA design starts dwarf the number of similar ASIC design starts. “There are 140,000 FPGA designs done every year as opposed to 10,000 to 12,000 ASIC starts,” says Rich Wawrzyniak, senior analyst at the market research firm Semico. While he counsels that only 5% of those FPGA starts end up in finished products, that’s still an enormous amount of SoC development.

Trend #4: Converting from FPGA to ASIC is constantly getting easier.

Targeting an SoC design at an FPGA platform is a cost-effective way to develop a product. Typically, companies use the FPGA in the new product until it becomes clear that product volumes will be large enough to justify an ASIC version of the chip. “The FPGA has come a long way in terms of the fundamental hurdles of unit cost and power utilization,” says Intel’s Mehta. “But there’s still no question that for large volumes, ASICs will continue to remain more economic.”

Fortunately, it’s becoming easier than ever before to re-target an SoC design from an FPGA to an ASIC. Forte, for example, supports two design trees from the same code base, allowing chip designers to target both platforms. “We encourage designers to think about their designs at a higher level, without being forced to worry over much about whether the final chip is programmable,” says Cline.

The use of an FPGA in early development phases can reduce overall costs at the corporate level because the lower cost lowers the risk of a product failure. “FPGAs allow you to more easily hit a market window, thereby making it more likely that you’ll have a hit product,” explains Synopsys’s Jaeger. And because the door is open to move the design to an ASIC, if and when the time is right, it’s no wonder FPGAs are proving so popular among the SoC-savvy.

By Ed Sperling

ARM introduced a 2GHz, dual-core version of its Cortex A9 embedded processor. Does that sound like the market dominated by Intel?

Yes is the correct answer. And that explains why Intel introduced a high-end SoC version of its Xeon processor aimed at embedded communications—one that comes with a small footprint and lower power. It’s one of ARM’s strongholds. There’s nothing like a good fight to get everyone in the holiday spirit.

And with the Intel Developer Forum on tap next week, you won’t have to wait long to see fireworks. Intel is already gearing up for battle, streamlining its internal organization by dividing the empire into two parts—products and manufacturing.

But in any reorg there are winners and losers—often for reasons that make no sense outside the company. (Sometimes they don’t even make sense inside the company, but that’s another matter.) Pat Gelsinger, Intel’s former CTO, a longtime company evangelist and one of the earliest proponents of IDF apparently didn’t see much of a role for himself in the newly reorganized Intel. He bowed out one week before IDF to take over a division at EMC, the enterprise storage and security company. He was still listed as one of the IDF keynoters until this week. Intel’s stock dropped on the news. Ouch.

Actel updated its Q3 guidance to investors. The new projection is that revenues will be flat to up 3%. That’s instead of the old guidance, of -2% to up 4%. It’s nice to see those negative numbers go, isn’t it? We may survive this downturn after all.

Chartered’s board recommended that the company be sold to ATIC International Investment Company, the Abu Dhabi government’s investment group, in an effort to raise necessary investment capital and to allow the foundry to achieve global scale. The board said the offer appeared to be “fair and reasonable.” No surprises here, other than the initial offer.

For anyone working on the manufacturability side of semiconductors, the joint deployment by Mentor Graphics and Applied Materials of the OASIS.MASK should represent a milestone in data reduction. OASIS, which stands for Open Artwork System Interchange Standard, reduces the size of mask data files by about half. That, in turn, speeds up manufacturing because just transferring that amount of data can slow systems down to a crawl.

Also on the manufacturing side, TSMC chose Synopsys’ HSIM simulator for its sub-40nm memory IP. The simulator will be used for timing, power simulation, dynamic IR drop and EM analysis.

By Ed Sperling

Actel introduced the first radiation-tolerant FPGA with embedded radiation-protected mutiply-accumulate blocks for use in outer space. With increased density at each node, the number of single-event upsets increases proportionately due to cosmic radiation. In some cases, these kinds of events can destroy a chip, leading to all sorts of complicated error-correction designs.

Mentor Graphics pushed further into the IP world, rolling out its configurable Precise-IP independent IP platform for FPGA design that links to categorized third-party IP from a variety of vendors including ARC (soon to be part of Virage Logic), ARM, Aeroflex Gaisier, CAST, Eureka, Hellon, IPextreme, Innovative Logic and OptNgn. This is like an instant ecosystem. Just add water.

That comes on the heels of a couple of major product adoptions for Mentor—Catapult C Synthesis by Fujitsu and Veloce Emulation by MIPS. Sounds like business is starting to pick up again.

Speaking of Fujitsu, the company seems to be in technology acquisition mode. ARM licensed its Cortex-M3 processor to Fujitsu for future low-power applications.

Synopsys, meanwhile, was making noise about one of its customers, Ubixum. The company used Galaxy Custom Designer to achieve first silicon for its sensor chip. Coming on the heels of multiple customer wins, this is yet another sign of life in the chip world.

Cadence inked a multi-year deal with GlobalFoundries, the AMD spinoff, to incorporate Cadence technology across the flow from design to manufacturing. Given the source of the money behind this deal, it’s a …well…big deal.

Magma announced it is offering a 6% conversion price for restructuring its debt. This will surely feed into lots of speculation about whether that is high, low, normal, and indicative of the company’s future. We’re staying blissfully neutral on this one.

By Ed Sperling

Mentor Graphics introduced the first Verification Academy, aimed at boosting functional verification skills. This is a good concept, given this is one of the big pain points and cost centers in chip design. Better still, it’s available anytime, anywhere using the latest methods in verification. We think this is a nifty idea for anyone working in verification.

Network-on-chip provider Arteris introduced an interesting twist on the whole NoC concept—the ability to connect peripherals by the dozens without worrying about what’s on, what’s off and in what order. This is a big step forward, and certainly one of the more interesting twists on ESL design.

Actel’s Q2 numbers show a slide, but minus all the restructuring charges the company still managed to keep its net income in the black and its four tires on the road. Revenue was $45.2 million, which is down from last year but down just 6.7% from the first quarter, which is the only real measurement companies can use these days to measure their progress—and their imminent turnaround. Projections for next quarter will be up by as much as 4%. Actel also introduced a new version of its Libero low-power and design integrated design environment, complete with design debug that allows engineers to insert a probe after layout to bring signals out to package pins.

Magma’s auditors may have doubts about the company, but apparently Magma’s customers don’t. The company will beat previously announced guidance for the quarter ended Aug. 2, posting better-than-expected sales and a lower-than-expected loss of 16 cents to 17 cents a share, rather than the projected 19 cents to 20 cents. The company also generated cash flow of $4.5 million. That doesn’t sound quite as dire as last week’s report.

Intel teamed up with Facebook to do good rather than just do well, creating a new volunteer program that allows computer owners to turn over their unused processing power for disease research and climate change study. It may not sell more processors, but it certainly will help ensure that people are around to buy them.  Along the same lines, but this time more on the doing well side, Intel Capital invested in five cleantech companies. This stuff may be good for the planet, but it’s also good for Intel’s bottom line.

Mentor Graphics inked a deal with EDA Direct, a distributor, for its PCB and FPGA products. Just to put things in perspective, Mentor is the only major EDA company that has an indirect channel, which cuts down the cost of sales in a high-volume market. That should say something about the state of the EDA market, in general.

And along the same lines, Synopsys and Actel renewed their OEM relationship for FPGA design software, which became essential after Synopsys bought Synplicity. Given the low-power focus of Actel and the heavy push by Synopsys into low-power design, this relationship bears watching.

Analog has been getting a lot of attention these days, although mostly in the layout area. Synopsys just added analog simulation to its Galaxy platform.  They’re not alone, of course. Mentor, Cadence and Magma all have offerings in this space. The only question is whether analog engineers will actually use these tools. In pure analog chips the jury is still out, but in mixed signal chips these kinds of tools are generally seen as useful.

Moore’s Law has always been an economic equation, despite the fact that most design engineers see it alternately as an interesting challenge and a royal pain in the neck. The simple fact is that if you put twice as many transistors on a piece of silicon, it’s cheaper to make the entire device because you can include more functions on that chip, thus requiring fewer parts overall. The use of chemical vapor deposition has been well established, but using silicon oxynitride at 28nm has not. This is something of a breakthrough using a standard technology at a new node, and TSMC claims the title.

By Ed Sperling

Single event upsets used to be as rare as some elements on the Periodic Table, with the damage they could cause relegated more to theory than reality. Not anymore.

At 90nm, what was theory became reality. And at 45nm, the events are becoming far more common, often affecting multiple bits in increasingly dense arrays of memory and now, increasingly, in the logic. Known alternatively as soft error rates, these errors increasingly must be accounted for in designing SoCs, FPGAs, embedded IP and memory chips, adding to the cost and the complexity of these devices and straining power budgets with error correction technology.

“About two years ago most of the system companies, when they handed down the spec, there were a few lines of code in there called SER, or soft error rate,” said Tom Quan, senior director of EDA and design service marketing at TSMC. “It used to affect the RAM more, and you had to put in error correcting. The issue now is the logic. It’s so dense already, and it’s going to get denser as we go to 28nm and 22nm. “

Already, the problems have moved beyond a single-bit error. Olivier Lauzeral, president and general manager of iRoC Technologies, an independent testing firm, said the level of single-bit errors has remained stable as manufacturing processes moved from 130nm down to 45nm, but the number of multi-bit upsets has risen dramatically. That creates an even bigger problem. While it is possible to correct for single-bit errors, it is not possible to detect more than two bit errors at a time or correct more than one.

“The mechanism we are dealing with is that charged particles travel through silicon for a certain range before losing their charge,” Lauzeral said. “In the memory, a zero or a one is held by a small charge, which is the critical charge. If a particle deposits its own charge, it can flip the one to a zero or a zero to a one. At 65nm, the charge is 1.1 volts. At 45nm, it is 0.9 volts.”

Sources of the problem

There are two known sources of soft errors: One is caused primarily by alpha particles emitted by decaying radioactive elements while the other is caused by stray neutrons, which are present in great abundance. As the voltage and capacitance have been reduced in conjunction with the finer geometries at each process node, the destructive power of these particles has increased proportionately.

“Flip-flops were no problem before 130nm,” said Lauzeral. “As we go to 90, 65 and 45nm, the failure rates are increasing.”

SRAM is particularly sensitive to soft errors because the way the charge is stored. In fact, that is the primary reason why Actel has shifted away from SRAM to flash memory. In FPGAs programmability has to reside somewhere, and historically that’s been in SRAM.

“With flash, you can’t get enough charge on a floating gate to cause an error,” said Mike Brogley, product marketing manager at Actel. “SRAM is more sensitive. You can do some things to mitigate it, but it’s difficult to protect from the SRAM effect without sacrificing area and performance.”

Xilinx, which has been working on the problem for nearly two decades, has developed an epitaxial layer on a heavily doped substrate for parts used in outer space, where highly charged alpha particles can wreak havoc on electronics. Gary Swift, senior staff engineer at Xilinx, said the real concern in space is latch-ups or gate ruptures, which can destroy a device.

“In space, you should monitor your configuration continuously,” said Swift. “For commercial applications, Xilinx provides reference designs to do the same thing. Most of our commercial customers are happy with detection of single event upsets. In the Virtex-5 devices, you also can correct a bit error autonomously. But even as we scale to future nodes, these events are relatively infrequent at sea level.”

Swift said that most people are comfortable re-booting their computer or cell phones a few times a year, if there is an upset, but their tolerance would be severely tested if they had to do it once a day.

Particle physics

Studies of alpha particles began with atomic bombs in the 1940s. The field of study shifted to cosmic radiation in the 1970s because there was concern that spacecraft and airplanes could be affected by the more highly charged alpha particles in the upper atmosphere. The study was expanded even further to include terrestrial neutrons (as well as protons) in the 1980s by computer systems vendors, which were concerned about the reliability of their systems.

By themselves, neutrons cannot affect the systems because they carry no charge. But they can merge with other neutrons to create a heavier nucleus, which does have a charge. Error correction in DRAM was one of the first attempts at addressing this problem in the semiconductor world. In addition to stray neutrons, some DRAM packaging contained trace levels of decaying radioactive material from elements such as thorium, polonium, radium and uranium, which in turn produced alpha particles.

All of those effects proved manageable at 1 micron and above. But as Mentor Graphics chairman and CEO Wally Rhines has said publicly, at deep submicron geometries the laws of physics don’t change, but they are more rigorously enforced.

Where the problems strike

“We’ve got several customers in the telecomm space who were seeing system-level failures from these effects,” said Actel’s Brogley. “In an FPGA, these can change the circuitry. They can disconnect a customer or completely change the system. It could be benign or it could be a basic change.”

That threat is less severe in ASICs, where everything is hard-wired, and it rarely happens in software. In fact, Lauzeral said software can be used to mitigate the problem. “You can use an algorithm to protect data. In network communication, for example, when a packet is corrupt you can recall it. But if you get corruption in the addressing of where that packet needs to go, you have a problem. If data is corrupted it’s less of a problem than if it’s the base station for cell phones or the braking or driving system of a car.”

In most cases, there are workarounds. Even in packaging, impurities can be removed for a significant amount of money. But increased density—caused by more bits in a smaller space, even though the bits increasingly are smaller—is elevating the problem out of pure research and into mainstream designs. What remains unclear is just how much extra these workarounds will add to cost, particularly in sensitive consumer markets, and what the overall effects will be as we progress from one process node to the next.