By Ed Sperling
Among tools vendors it’s been standard practice to listen closely to customers but not deliver everything they ask for—or at least not always on the customers’ timetable.

This strategy has worked well enough for both sides in the past, but at 20nm and in stacked die configurations, the level of tension between these two worlds is increasing, and the gaps in the tool chain are becoming more noticeable. Part of the problem is that skyrocketing complexity is forcing more automation, but integration issues, physical effects, process variation and the realities of physics make it more difficult and time-consuming to develop tools to make that complexity more manageable. R&D budgets for EDA companies already are hovering around 30% or more, compared with average R&D investments of about 10% to 20% in other areas of chip development and manufacturing, and betting on the wrong area can have a significant impact on EDA company’s earnings.

The other part of the problem is that chipmakers’ own internal tools are running out of steam at advanced nodes because of the need to bridge both hardware and software design environments and because old methods of doing things are way too slow and very often ineffective. This is clearly reflected in the fortunes of EDA tools vendors, which have been rising steadily for the past couple of years, with the strongest growth in areas such as ESL, including hardware-software co-design and software prototyping, and emulation.

Add in stacking of die, in both 2.5D and 3D configurations, and the number of issues that have to be dealt with by both chipmakers and tools vendors increases by orders of magnitude. On top of that there are double patterning issues at 20nm, finFETs at 14, and potentially 450mm wafers that will require significantly higher yields to be cost-effective, but which may be harder to test in wafer-on-wafer or die-on-wafer configurations.

Where chipmakers see challenges
Riko Radocjic, director of design for silicon initiatives at Qualcomm, breaks the design process down into three areas—design authoring, which is the actual chip design; pathfinding, which includes exploration for how to best build a chip; and tech tuning, which is physical space exploration. Most of the EDA tools have been effective in the design-authoring phase, with some point tools now finding their way into the pathfinding area. But the real challenges are in the tech-tuning area.

Mechanical stress becomes a serious issue in 3D stacks, ranging from the effects of TSVs to die alignment. “You cannot solve the problems with a tool. They have to be solved in a flow,” he said. “It’s a debug nightmare. You need a separate domain that takes external stresses and produces a set of rules. You also need hotspot checking to make sure you have caught all of the interactions.”

Also missing, he said, are EDA tools that understand the materials inside a stacked die, and a standard PDK for all mechanical and thermal properties.

“Thermal is the next frontier,” he said during a presentation at the Electronic Design Process Symposium this month. “You need to manage for hotspots and overall system power. On a global level you have skin temperature and overall system power. On a local level you have to manage hot spots, junction temperatures and power density. And there is also the compounding factor that all advanced systems use some form of thermal management. We need a system-chip co-design methodology and tools to deal with this. We cannot solve thermal issues only at the component level. It must be system and component, and we will need tools for pathfinding thermal issues. We don’t even know where to put our thermal sensors. We need thermally aware floor planning.”

Summing it up, he said it amounts to 3D-aware co-design tools for package, system and thermal, and a flow to integrate everything.

A stacked die of the future; memory on top left, with logic/memory in middle on top and I/O and analog RF blocks on top right. All feed into interposer stack in the middle. Source: Qualcomm.

Altera, which has just developed its first 2.5D stacked FPGA prototype, is encountering similar thermal and mechanical issues. While the company continues to offer scaled down tools for FPGA development, it needs the most advanced tooling for creating those FPGAs in the first place. Topping his list are robust standards for cells, IP and stacked ICs, as well as tools to help quickly identify some of the problems that Altera encountered while developing its prototype stacked die.

Signal integrity issues encountered and addressed by Altera in stacked die using interposers.

“We’re looking for more of a divide and conquer strategy,” said Arif Rahman, product architect at Altera. “Die stacking will be an enabler for a complete solution in the future, but it will not just be an FPGA. It will be an FPGA plus other accompanying functions.”

Where EDA tools vendors see challenges
For the tools vendors, the list of problems that need to be solved is exploding. So many things need to be fixed and solved that it’s imperative just to focus on both what will have the most impact and what will provide the greatest long-term returns.

At least part of that effort involves existing tools, which have to be run faster and do more things than in the past. This is particularly true in areas such as emulation, which in the past were used almost exclusively for hardware. They are now becoming the tool of choice for software verification because the complexity of the software makes it far too slow to run using simulation. What takes hours or days in simulation can be measured in seconds in emulation. And given the fact that verification is still the lion’s share of the NRE, anything that can be done to solve this problem is considered a big win.

Mentor Graphics’ announcement this week of enhancements to its emulation tools is a case in point. Recognizing that software engineers are using the emulation tools as much as the hardware engineers, the company has added a virtualization layer that allows a workstation to be a front end—matching the way software engineers work—rather than doing work in a lab the way hardware engineers typically work.

“This allows one workstation per user,” said Jim Kenney, director of marketing for Mentor’s Emulation Division. “We’ve also been working to improve performance and capacity so you have more robust software execution and debug.”

Mentor isn’t alone in this quest. Cadence has been updating its own emulation, and all the EDA vendors have been racing to improve the reach and integration of their tools. Bassilios Petrakis, product marketing director at Cadence, noted that building smaller die that yield better is still a challenge that needs to be solved—particularly before stacking becomes mainstream.

“When you look at multiple die with TSVs, the cons are that the ecosystem is still emerging, there is no volume production yet and there are thermal issues,” Petrakis said.

Samta Bansal, senior product marketing for SoC Realization at Cadence, predicts that stacking memory on logic using an interposer will become mainstream beginning in 2013 to 2014, with TSVs becoming mainstream by 2015. She said work in EDA typically needs to begin three to four years before these efforts, noting that it began in earnest at Cadence in 2009. Synopsys rolled out its 2.5D tool flow last month and is working on a full 3D flow, and Mentor has been working on a variety of areas ranging from test to modeling of stacked die over the past several years.

But EDA vendors also need to pick new areas for the future, and this is where even the best educated guesses become difficult.

“EDA traditionally has been an industry where big companies acquire small companies doing interesting things,” said Wally Rhines, chairman and CEO of Mentor, noting that markets that have shown strong growth include DFM, formal verification, ESL and power analysis. He said the next wave of electrical design challenges include low-power design at higher levels of abstraction, optimizing embedded software for power, in-circuit emulation, design for test, physical verification, stacked die verification, and system design that extends beyond the PCB.

That concern is echoed by Drew Wingard, chief technology officer at Sonics: “From an EDA perspective, the next layer up in the power hierarchy is how we convince ourselves that the hardware and software are working together correctly. This is a different protocol check than we normally do. You have dependencies, because you can’t turn off one until another turns off. The mix of hardware and software makes it difficult to prove what’s correct. Right now there is not even enough time to test the power management until the second spin.”

He noted that just trying to get software to turn on the power management features in a chip is a challenge. “The thermal/power reduction to be gained by turning on features already in a chip can be significant.”

One issue that almost certainly needs attention is derivative designs. Getting them out the door is painful, expensive, and time-consuming.

“A lot of engineering that’s being done is derivative engineering,” said Naveed Sherwani, president and CEO of Open-Silicon. “This is not something that EDA vendors focus on, but it’s something that’s definitely needed. What’s out there is a kluge of methodologies and flows. EDA so far has not woken up to this opportunity. They certainly listen to their customers, but they’re still not close enough. You have to do the work to understand it, and the revisions and changes that are needed are painful. A derivative is almost like a new project. There can be 1 million degrees of improvement here.”

Conclusions
All of this requires tools—notably more and new capabilities built into existing tools—as well as new tools that can integrate all of these pieces. But what gets addressed first is a difficult balance.

While chipmakers at the leading edge are used to developing some of their own tools, methodologies and dealing with poor yields, their existing development is running out of steam. That means moving forward at advanced nodes and in stacked configurations will require developing entirely new versions of tools, methodologies—an enormous expense by anyone’s calculations.

Qualcomm's proposed tech-tuning flow.

EDA vendors, meanwhile, have their work cut out for them just updating their existing tools, and they are cautious about massive investments in new areas that may not return dividends within an appropriate time frame—or within an immature supply chain when it comes to stacking of die.

“To get ROI back on tools of this complexity you need more than 20 customers,” said Mike Gianfagna, vice president of marketing at Atrenta. “That means you’re going to be negative on that investment for three or four years. So you really have to pick your battles, and small companies probably can’t do this at all.”

Gianfagna noted that for chipmakers the challenge is too many options. “You need a way to prune the solutions space fast. You have to figure out which architectures to choose quickly and which roads to pursue further. The real gap is not in the tech tuning. It’s coming up with the right architecture that supports meaningful decision-making.”

The question now is when the gaps that each side sees will merge, and when it will become profitable enough to take an investment risk.

By Ed Sperling
Synopsys rolled out a suite of integrated tools specifically for both 2.5D and 3D stacked die, setting the stage for a huge change in how ICs are designed and packaged over the next decade. The company also introduced its audio subsystem, complete with IP, tools, a processor and audio codecs. In addition, Synopsys teamed up with Altera and TSMC for silicon-accurate parasitic modeling and extraction at 28nm, and it created parasitic extraction models for double patterning with an industry consortium.

Mentor Graphics added support for the Yocto Project, allowing its embedded Linux middleware to support the various flavors of Linux development without putting the burden on developers. This is an important step forward in the commercialization of Linux, where development has been piecemeal in keeping with its university/scientific roots. Mentor’s tools allow developers to build embedded systems without worrying about which hardware to use. Mentor Graphics also teamed up with Triad Semiconductor to create a low-cost, mixed-signal tool the companies claim can slash costs and development time for mixed-signal ICs. Triad is based in Winston-Salem, N.C.

Cadence announced verification IP support for two new enterprise-level cloud storage standards, NVM Express and 12GB/second SAS (serial-attached SCSI).

By Ed Sperling
Cadence rolled out new LPDDR3 memory IP, upgrading the bandwidth management engine to improve performance while lowering power consumption. The company also expanded its Shanghai office for R&D, as well as sales and technical support.

Synopsys rolled out verification IP for Non-Volatile Memory Express (NVMe), which allows solid state drives to connect directly to PCI Express. Synopsys also announced its VDK family of products for ARM Cortex processors, including big.LITTLE.

Altera has jointly developed its own 3D IC test vehicle using TSMC’s chip-on-wafer-on-substrate integration process. This puts Altera head to head with Xilinx on stacked die.

And GlobalFoundries shipped its 250,000th 32nm high-k/metal gate wafer, thereby ending speculation about whether HKMG will ever go mainstream. The 28nm node uses the same technology.

By Ed Sperling
Synopsys continued its buying spree, acquiring verification IP developer ExpertIO. Synopsys will absorb the entire ExpertIO team, including CEO Craig Stoops, into its verification group. Terms of the deal were not disclosed. What’s particularly interesting is that ExpertIO’s partners include all of the Big Three EDA vendors.

Synopsys also is collaborating with Sigrity to accelerate signal integrity analysis, and it won a deal with Yamaha, which is standardizing on its Processor Designer tool for custom DSPs.

Mentor Graphics won a deal with Altera, which will use its Voloce emulator to verify its next-generation FPGAs.  Mentor also won a deal with Fujitsu Semiconductor, which is expanding its use of Mentor’s Calibre platform for physical verification and DFM. e

Open-Silicon rolled out a 28nm version of its Interlaken IP core for chip-to-chip packet transfers for networking products.

Arteris reported more than 100% growth in NoC technology licensees in 2011. The number is now 39, up from 18 at the beginning of last year.

By Ed Sperling
Altera is embedding Synopsys’ virtual prototyping technology in its ARM-based SoC FPGA products. Considering FPGA vendors have been giving away their tools for years, much to the chagrin of EDA vendors that have tried repeatedly to win a foothold in the FPGA tools market, this potentially is a big deal. And considering the existing market for virtual prototyping is still small and the FPGA opportunity is quite large…well, this gets very interesting.

On another front, Synopsys is collaborating with UMC to develop IP for the foundry’s 28nm HLP Poly SiON process.

Mentor Graphics is working with Freescale to accelerate automotive infotainment that relies on ARM A9-based processors. Mentor’s In-Vehicle Infotainment base platform is compliant with the requirements of the GENIVI Alliance, the association of automotive and consumer electronics companies.

Russia-based IntegrIT has ported its NatureDSP Math Library to Tensilica’s baseband DSPs. The traditional emphasis on science and math is still alive and well in Russia—and expanding into some new markets. IntegrIT develops signal-processing routines for DSP functions.

By Pallab Chatterjee
The National Association of Broadcaster show is the one place where you can be sure to find some of the most advanced technology on the planet—the kind of stuff used to broadcast, capture and edit 3D content. But while the market for this kind of technology is growing, the quantities of like products are still not high enough to warrant ASICs.

It’s a world dominated by FPGAs, and the leaders on the equipment side are Xilinx and Actel. They accounted for just about all of the visible FPGAs on the show floor. What was particularly interesting, though, was that the chips were not even the fastest chips in the FPGA companies’ lineup. They were not at the most advanced (smallest geometry) process. And they didn’t use the largest number of cores. In fact, most of the FPGAs were one or two generations behind.

The most popular chip on the show floor was the Virtex-4, which was used in most of the single-width and height cards from Grass Valley Group, Miranda and others. The cards are either single-, dual- or quad-channel functions. Based on the card size, mechanical cabling connections and simultaneous switching characteristics, moving to a higher channel configuration than a quad does not make a lot of design sense. As a result, the older technology (90nm, 1.2v core, sub 960 I/O) does just fine with the data rates, signal integrity and jitter levels that are required for video processing. These chips can support the mainstream SD and HD data rates, the 3Gb/s SDI channels for streaming data and the high speed 6.5Gb data channels, if required.

As the chips include both DSP cores and processor cores, the codec functions needed for signal processing, and signal conditioning are easily implemented. This split architecture, supported by the local in-die memory allows the flexibility to support the multiple standards such as MPEG2, JPEG 2000 and MPEG4. As some of these standards are still being finalized and adjusted (the 3D portion of the MPEG4 specification is in progress), the in-field programmability of the FPGAs is a major asset. This will allow currently deployed equipment to be upgraded to meet the data standards as they emerge, which would not be possible with an ASIC or SoC.

The globalization of video also has changed the hardware requirements for the post-processing and broadcast communities. It is not uncommon for a single editing station to be receiving input from PAL, DVB, ATSC, P2 media, SD card, 3Gb fiber, 6Gb fiber channels, SD and 720 / 1080 HD data sources. This combo of inputs requires mixing and editing hardware to perform transformation to common formats, in addition to signal steering. This mix of data formats requires the chips have multiple clock domains with very small skews and tracking that is systematic (frame- and line-based rather than absolute psec based). The FPGA products, with their multiple distributed logic functions and distributed clock domains, fit this requirement well.

While some of the high-density video functions are power-sensitive, the broadcast signal processing cards are not. High-speed cross point switches, which may be as large as 200 x 200 channels, are shooting for power factors in the 100mW to 400mW per channel range. The signal processing cards typically consume 25W to100W/channel for the rack based systems.

For 3D, the hardware can utilize the same base chips. As the 3D formats are based on left and right eye frames each being shown at half the data rate, the performance requirements for the processing chips do not change. The new 3D capable products featured a reconfiguration of the control logic for the dual-frame format, but left the interfaces the same while remaining on the same FPGA platforms.

The display side of the 3D world (TVs and set-top boxes) is much more standardized on their data and has a much more limited I/O requirement. While these applications are good targets for SoCs and ASICs, the signal-processing world for video appears to remain the province of FPGAs.

By Ed Sperling
The consolidation of intellectual property from small developers to large players with integrated IP blocks is accelerating. Large IP companies are now developing integrated suites that are pre-tested for specific vertical markets, and new companies are sprouting up to make it easier to put even broader collections of IP together in meaningful ways.

It’s difficult to tell whether the trend is being driven more by the IP vendors or pulled through by chip developers looking to cut costs—or whether it builds upon the stamp of approval by foundries for certain pieces of IP. The net effect, however, is the creation of subsystems and partial platforms that are one step below reference platforms.

“A reference design suggests a complete solution,” said Eric Schorn, vice president of marketing for ARM’s processor division. “Customers don’t want us to go that far. But we are moving in a segment-oriented fashion. That’s the reason we bought a graphics processor company. We are making a processor along with a graphics socket for mobile phones and set-top boxes.”

The company isn’t alone in recognizing the opportunity for putting together more pieces of IP in very specific ways. Virage Logic’s recent acquisitions of ARC and NXP’s IP unit have positioned it to lead with integrated subsystems in markets such as high-performance audio and video.

“You have to have a reference platform these days,” said Yankin Tenurhan, vice president and general manager of Virage’s ARC business unit. “That’s not much different from the good old days of silicon, though, when you needed a complete solution and a full blown prototype. Philips, NXP, Texas Instruments and ST all have demonstrator chips for whatever you want on a cell phone. The same is happening in the IP world.”

Putting together the pieces
It’s not just the IP vendors that are putting together suites of IP. Two startups are focused on making IP easier to understand and integrate. Parallel Engines, which emerged from stealth mode this week, is focused on organizing IP by data mining pertinent information about everything from power requirements to the interfaces and interconnects.

“There are 12,000 pieces of IP out there, including 8,000 pieces of hard IP that are made by about 50 companies and about 4,000 pieces of soft IP,” said George Janac, CEO of Parallel Engines. “The hard IP is already in FPGAs from companies like Actel, Xilinx and Altera. You just need the soft IP to make it work.”

Somewhat conveniently, Janac’s brother, Charlie, is the CEO of Arteris, which makes network on chip technology that can be used to glue together these IP blocks.

“A company may have one or two pieces of IP that are the secret sauce and some software,” Charlie Janac said. “Why not drop those into an FPGA and connect up the other pieces of IP? Those two worlds are merging. We’re going to see much more custom logic on an FPGA.”

Another company involved in bringing IP together is Silicon IP, run by Kurt Wolf (formerly of TSMC), who said there’s a disconnect between chipmakers and IP vendors that still needs to be closed. “The chip guys distrust the IP industry,” Wolf said. “There’s more integration of IP, but there’s still a lack of confidence about how to choose, buy and license IP.”

Wolf’s company is focused more on bringing the two sides together with better information and connecting the pieces in an organized way.

The future
All of these efforts—by both large IP vendors and startups—are signs of just how important commercial IP has become in chip development. What began with embedded processors and standard memory designs has evolved into a huge market that actually gained momentum in the recent downturn.

Outsourcing is gaining ground at every level of business, even outside of the semiconductor world, but in the past most of the gains have been in areas where there was little value add. Outsourcing traditionally has been relegated to commodity services. What’s changing is that IP now includes areas that companies cannot do themselves in addition to those they don’t want to do, as well as the extremely tedious and time-consuming integration work that is necessary to create a final product.

When most analysts predicted a massive growth in IP at the beginning of the decade they were largely talking about small, relatively unsophisticated IP blocks pieces that can be put together by highly sophisticated companies. In the future, the differentiation may be less around the technology and more on getting very complex chips assembled and to market faster for specific market segments.

By Ed Sperling

The world is still full of engineers who can build fast interconnects to things like PCI Express or USB 2.0 who can create complex schematics for determining the connections between a processor core, memory, logic and various IP blocks on a piece of silicon. But over the next several years, many of those engineers will have to figure out new ways to make a living.

The number of companies that are jumping into pre-configured interconnect strategies—either through existing bus structures such as AMBA or the emerging network on chip approach—is growing rapidly. This is the latest trend in the disaggregation of the supply chain for systems on chip, using pre-configured approaches or high-level flexibility to plug in third-part components instead of developing everything in-house.

There are several reasons these approaches are gaining in popularity:

1. Complexity is making it harder to keep track of the interconnects, particularly in devices where there are multiple cores and multiple power islands that can be turned on and off.
2. Smaller staffs with targeted resources, or even the same size staff with more complex demands, are forcing design teams to put their resources where they can make a competitive difference rather than re-inventing something that is good enough and which adds no value.
3. Market windows are forcing companies to rethink their make vs. buy decisions, which is driving decisions about everything from intellectual property to restrictive layouts.

Riding the bus

One of the earliest standardized approaches to solving interconnects was the bus approach, and it remains popular in many chip designs today. ARM rolled out the Advanced Microcontroller Bus Architecture (AMBA) in 1996. AMBA is now in its third generation, with significantly improved speed over the first iteration. IBM developed its own CoreConnect standard for its Power chip architecture.

For chip developers, the nice thing about both bus architectures is that they’re free and well documented. AMBA 3.0 actually includes five different bus interfaces, most notably the Advanced High-performance Bus (AHB), which permits such things as burst transfers and split transactions, and the Advanced eXtensible Interface (AXI), which focuses on addressing and data phases. CoreConnect, meanwhile, includes a processor local bus, an on-chip peripheral bus and a device control register bus.

The advantage—and the disadvantage—of buses is that they’re hard-wired through a crossbar switch. While that guarantees a connection, there are fairly regimented ways of making those connections. For example, you can’t just connect a 32-bit IP core with a 64-bit interface without a converter, and you can’t just match up components with different frequency without using a clock converter.

“Ultimately, a bus performs the same task as a network on chip,” said Mike Dimelow, director of marketing for ARM’s processor division. “Their ways of solving the interconnect issue are different, though. They are both complementary and competitive with each other, but the problem they are trying to solve is the same—connectivity.”

They’re also a way of adding re-usability for IP, which is why Xilinx is now adding support for the AMBA bus architecture in its FPGAs—the last of the major FPGA vendors to support AMBA (both Actel and Altera have supported AMBA for years, while Xilinx backed the IBM CoreConnect approach). One of the attractive things about AMBA is its support for IP-XACT, the IP interoperability standard created by the SPIRIT Consortium (now part of Accellera).

“What this allows us to do is standardize on an interconnect scheme,” said Vin Ratford, senior vice president for worldwide marketing and business development at Xilinx. “FPGAs are a repository for a lot of IP. AMBA is one element for allowing more reusable IP.” (See Figure 1)

Figure 1: AMBA's IP connection (Source: ARM)

Adding flexibility

Building on the need for pre-configured connectivity, networks on chip have taken that approach a couple steps further by decoupling the transaction from the transport, and more recently decoupling the entire physical layer. The approach follows the broader networking world, where information is packetized into discrete bundles rather than maintaining a constant connection the way old telephone lines used to do. (For a look at life before packetization, check out some of old political thrillers where the telephone was kept off the hook one a connection was made to make sure that communication would not be interrupted.)

Decoupling of all those pieces allows a much more flexible design, and both Sonics and Arteris have been pitching the value of different NoC approaches. Sonics joined forces with Synopsys in June to create a pre-configured IP block that includes a memory scheduler and Synopsys’ Designware protocol controller IP. Arteris upped the ante in the NoC world in August, rolling out a peripheral NoC that instantly connects timers, USB, infrared interfaces and audio and touch-screen components.

The advantage of NoCs is a reduction in the number of wires and the flexibility of the design. “What this provides is ultimate flexibility,” said Geert Rosseel, chief technology officer at Arteris. “There is no topology or configuration you have to worry about up front, so in the end this can lead to truly smaller chips with higher frequency. You get big improvements with power, area and performance by using this approach.” (See Figure 2)

Figure 2: The NoC approach. (Source: Arteris)

That’s particularly useful from an architectural level when not all the functions or connectivity that ultimately will be required are known. In some cases, new standards or interfaces are completed before a chip reaches tapeout, and having the flexibility to add onto the design at a later stage is invaluable—particularly when the design will be used for a series of derivative chips.

ARM, meanwhile, is hedging its bets on both the bus and NoC. While it continues to update and support AMBA, its QoS now supports both, according to Dimelow.

If you think things are bad, be glad you’re not in the Taiwanese foundry business—where the pain level is strangely uniform.

TSMC’s sales dropped 59.5% in February compared to the same month last year, and 7.5% compared to January. How many ways can you spell ouch? 

UMC’s numbers are down 56.9 percent in February 2009 vs. the same period in 2008. That’s pretty close. In fact, it’s remarkably close.

This kind of information is only available in Taiwan. SMIC, based in Shanghai, and Chartered, based in Singapore, don’t report monthly sales numbers.

Nevertheless, there was at least some encouraging news out of Chartered. It said that sales seem to be stabilizing and wafer starts appear to be increasing for Q2. 

There is evidence of this showing up in other parts of the market. U.S. retail sales, excluding big-ticket items like cars, show modest increases in areas like clothes and consumer electronics. Numbers were up in January and February. It certainly wasn’t a robust gain, but it wasn’t negative, either. That will translate into new design starts sometime in the next few months, which barring any more major drops will start this whole cycle rolling again.

Design activity has to begin at least six months prior to any turnaround, which means that if the overall economy is expected to show growth in 2010,  electronic designs have to begin by mid-year—perhaps even sooner.

None of this is perfect, however. Why, for example, did National Semiconductor just announce plans to cut 26% of its workforce? At least part of that can be explained by closing of an assembly and test plant in China and a fab in Texas. Too much capacity is expensive, and we wouldn’t be surprised if National ultimately begins outsourcing some of its work to foundries. Yes, it’s analog, but is it still more efficient to run fabs yourself, even if they’re fully depreciated, when TSMC and UMC are begging for business?

Meanwhile, in the FPGA realm, chip design is getting so complex that EDA vendors are finally beginning to find inroads. This is a market previously owned by tools from the FPGA vendors, which they readily gave away to customers at little or even no cost. That worked fine before the industry got to 90nm, and at 45nm it’s tough enough even with the best of tools.

Mentor introduced its Precision Synthesis Tool family for Altera’s Stratix and Arria families. Our guess is that you can expect to see a lot of activity in this market in the near future, and not just from Mentor. Synopsys’ purchase of Synplicity gives it a vested interest in the FPGA market, as well.

–Ed Sperling