By Ed Sperling
Cadence added in-circuit acceleration for the Incisive verification and Palladium emulation portions of its System Development Suite. This will reduce the time it takes to run tests on complex SoCs—for both hardware and software—allowing more time to make sure the chip actually works. Cadence also extended its Verification IP catalog for acceleration and emulation. The company also introduced an NVM Express subsystem with pre-integrated and tested IP.

Mentor Graphics won two deals. The first was from U.K.-based Professional Circuit Design, which standardized on Mentor’s PCB design through manufacturing technologies and consulting services.  The second involved Vestel Electronics, a set-top box manufacturer in Europe, which is using Mentor’s Inflexion user interface technology.

Synopsys won a deal with AMD, which will use Synopsys’ Discovery VIP involving everything from USB 3.0, ARM’s AXI, SATA 3.0, PCI Express 3 and Synopsys’ Protocol Analyzer. What makes this especially interesting is AMD’s play in the enterprise space.

MIPS rolled out a new generation of processor cores called Aptiv, with an emphasis on performance and energy efficiency. The cores are targeted at high-end mobile devices and smart home entertainment, squaring off against ARM’s big.LITTLE with what it claims is a much simpler power management scheme.

By Pallab Chatterjee
With the rise of mobile appliances, smart phones and tablets, there has been a lot of discussion about the place for PCs, servers, embedded processors and networks. A number of companies have claimed they will rule the world of computing and there will no room for others.

Reality seems to be somewhat different, however. The mobile end point devices—smart phones, tablets, and netbooks, are content-consumption devices. They playback content—video, music, still images, business data—that already exist.

The majority of business data is created on desktop/laptop PCs that use an x86 processor from Intel or AMD. These have been the dominant platform since the early ’80s and still are the workhorses inside most offices. Tablets are starting to be brought in to supplement the PCs and extend their lifecycle, but they are not displacing the existing machines. The computing power of these larger systems allows them to be used for presentation creation, as opposed to viewing, graphics creation, report writing and calculation. These are in addition to the engineering and scientific uses, which are also compute-intensive.

A common misunderstanding is that the multi-core microcontrollers that are in the tablets and smartphones can perform equivalent computational tasks to microprocessors. The applications on these devices (power optimized in-order-execution controllers with direct mapped memory) are created on machines using out-of-order execution featured microprocessors, which also provide deep, virtualized memory, large data stores and the true multi-user and multi-tasking. This allows for the creation of memory and runtime-optimized applications (i.e. Web browsing and games with multiple pre-defined playing levels and performance metrics) that have both known and minimized data and resource extents for the micro-controller based players.

As a result, standard development environments on Windows/Linux/Mac OSX using x86 machines are the default basis for the application and content creation for the mobile appliances. These are not just created on workstations. They also are created on a server base. Depending on who is quoted, the ratio of server cores per end point device is in the range of 1:8 to 1:20. This means worst case for servers, at the 1:20 ratio, it would require 2.5 billion x86 cores to address the 50 billion end-point devices forecast for the Internet of Things. Rather than spelling the death of big iron devices, it means massive sales in this market. Based on real applications, the ratio will average out to something closer to 1:12, which brings the number of cores close to 5 billion.

The advantage of these machines is the ability to support virtual users (multi-simultaneous clients) using products from Microsoft, IBM, VMware and Citrix, as well as full virtual machines. A virtual machine differs from multi-user approaches in that the I/Os, storage, security and CPU/GPU interaction are also virtualized for each user. This allows for mapping direct-attached and tiered storage, including a storage-area network, to be virtualized for access from the virtual machines.

Currently, the virtualization support for the microcontrollers and their associated hypervisors do not support full virtual machine capabilities. In discussions with more than 75 enterprise and data center administrators, this need for full storage and memory access, as well as out-of-order execution to support multi-applications from multi-users at once, are preventing microcontrollers from gaining ground in the server space. They have made only limited gains, mostly for targeted applications at the edge of the network for running Web servers and fixed fill-in-form applications that can be crafted the same way that end point code is created.
This accounts for, at most, 1% of the server environment at a ratio of one core for four users. It also brings with it a cost of development and support that is about four to five times the cost of general-purpose code that has single release capabilities and does not need multiple operating variants to be deployed for support of multiple device platforms and OSes.

By Ed Sperling
As complexity increases and the industry increasingly shifts away from ASICs to SoCs, the concept of coherency is beginning to look more like a stack of issues than a discrete piece of the design.

There are at least five levels of coherency that need to be considered already, with more likely to surface as stacked die become mainstream over the next few years. Perhaps even more mind-numbing, this stack itself will have to take on a level of coherency over the couple generations of chips.

Let’s take a closer look.

Cache coherency
The concept of keeping data coherent historically was relegated to processor makers such as IBM, Intel and AMD, which have focused on improving performance through faster access to data. One solution to that improved performance has been multithreading and multiprocessing. Along with that, these vendors have added in various levels of cache memory for faster recall of important data.

More cores also makes it harder to effectively use these caches. Data has to be kept consistent, which requires more system overhead in terms of processing and power just to maintain that coherency. And it gets even harder as more cores are added into an SoC, which increasingly are not same size, do not run at the same frequency, and sometimes do not even connect directly to the main CPU.

“With cache coherency, some of the traffic may be serviced by the cache on another GPU,” said Drew Wingard, CTO at Sonics. “If you’re just using an ARM core, the CPU coherence is sufficient. But the GPU uses its own local memory. You really want it to be fully cache coherent across all of those.”

But even finding the data to maintain consistency may be a problem in a complex SoC.

“You can view what’s in memory, or view it and be able to change what’s in memory, but first you have to find it,” said Kurt Shuler, vice president of marketing at Arteris. “If you have four cores, the most efficient way to hook them up is for each core to have its own cache and graphics to have its own cache. If you change something, you have to snoop in all the caches to make sure it’s consistent.”

But there is also a move in the completely opposite direction—sharing memories among multiple cores—because it reduces the number of components on the bill of materials. The Low-Latency Interface specification from the MIPI Alliance is a case in point, where a memory can be shared between a modem and an applications processor. Intel, meanwhile, has added on-chip graphics that share memory with the CPU.

“The whole design gets more complex,” said Shuler. “You have more traffic beyond the cores, and from a power standpoint the overhead goes up.”

Still, cache coherency is one of the better-understood pieces of this stack. It has been an issue ever since multiprocessing was first employed in the 1960s. “Snooping” has been widely used since that time.

Software coherency
A newer facet of coherency involves embedded software. Because SoCs now include an increasing amount of software in the design, engineering teams now have to wrestle with coherency issues that previously were dealt with by the operating system.

“Fundamentally you’ve got two combined issues here,” said Andy Meyer, verification architect for Mentor Graphics’ Design Verification Technology Division. “You’ve got cache coherency, where the same data is being viewed in a couple places. And then you’ve got an issue with consistency in the simple code in a uniprocessor that now has to run on a second processor. The ordering of events can change in multiprocessing.”

Those problems crop up regularly in verification, but not always with the expected results. It’s difficult to effectively write the stimulus in a testbench for coherency. What happens, for example, when a core is shut down to save power?

“The scariest part is when there is no OS support,” said Meyer. “There’s also a big problem with heterogeneous cache, such as when you have a CPU working with a GPU.”

Another issue has to do with effective coverage in verification, already a problem for complex SoCs. States frequently are distributed across multiple chips and multiple boards. Timing varies from one state to another, and can be particularly problematic if snooping functions are tied to a state. And parallelism continues to baffle even the most advanced teams.

“Standard coverage methods don’t work well here,” said Meyer. “You have to query in ways you traditionally didn’t have the power to query and ask questions across months of regressions. For instance, ‘Have we been here ever—or in the last two months.’ Until coverage steps up, people with deep knowledge of verification running hundreds of full-time emulator systems are finding out at the last minute that it’s not okay to ship.”

I/O coherency
Tied in with both cache coherency and software coherency is I/O coherency. Increased communication on a chip, between chips, and between a chip and the outside world, have turned what used to be a relatively straightforward networking issue into a complex jumble of prioritization and synchronization.

“You have to deal with this even in single processors,” said Sonics’ Wingard. “You may have a PCI core streaming data into memory. Today, without I/O coherence, it’s difficult to determine what is coming in. The CPU has no way of knowing what was transferred when it dos a copy from non-cache to cache.”

He noted that personal computers had I/O coherency for a long time, particularly with direct memory access. DMA was developed initially to help solve the bottleneck that occurred when a CPU was involved in an I/O transfer. Rather than tie up the CPU with that transfer, the CPU continued running, then accepted an interrupt when the transfer was completed.

But with more of this being moved onto a chip, keeping coherency while moving data back and forth from more places is becoming much more difficult.

Ecosystem coherency
One of the least addressed facets of the coherency stack involves business and communication issues across a supply chain for a particular SoC rather than the actually technology itself. Even where competitive suspicions can be overcome, the very different approaches taken for designing components, IP and software, as well as language barriers, create one of the more difficult and less tangible challenges in the coherency stack.

“The challenge going forward is that you have a bunch of people who may not be that skilled in system development driving the chip and spec for one design, and other supplier trying to orchestrate things,” said Mike Gianfagna, vice president of marketing at Atrenta. “So you bring them together to solve a problem for one customer in 12 weeks and then they move on. You’ve got corporations coming together and bringing all these pieces together almost like the way a movie is done. But is there a coherent way to communicate data and information risks and still provide good visibility from a power/performance/area point of view?”

For decades this task has been handled by IDMs, but in the SoC world there are far fewer IDMs these days. Many of these chips are built using third-party IP such as cores from ARM or MIPS, DSPs from companies such as Tensilica, and standard IP from the Big Three EDA vendors.

Coherency in stacked die
It’s uncertain whether stacking of die, either in 2.5D or 3D configurations will make coherency easier or harder. The answer is likely to be a little of both.

“With 2.5D and 3D, you’re looking at low-power memory access,” said Arteris’ Shuler. “You put the DRAM closer to the CPU, the addressing is wider and you get rid of some of the latency. But you also need coherency across all of this.”

No one is sure yet how multiple high-speed communication channels between die will affect coherency. If the channel between the core is wider and shorter that will improve data speed, but if processors and DRAM are scattered on multiple die, with some of them shut down, some partially shut down, and others fully active, it may make it harder to keep track of data and make sure it is all synchronized.

By Ed Sperling
There are two big issues when it comes to through-silicon vias. One involves cost. The second involves heat—in particular, how to get heat out of a stacked die and what the thermal coefficient of the TSV will be to make sure it expands at a rate consistent with the SoCs in a package.

To address these issues, System-Level Design caught up with Rao Tummala, professor of electrical and computer engineering and material sciences, as well as the director of the 3D Systems Packaging Research Center at Georgia Institute of Technology, where work has been under way for several years to address these issues. What follows are excerpts of that conversation.

SLD: Why use glass?
Tummala: There are a number reasons. One is that it can be done pinless. A second reason is that it’s highly insulating, with extremely high resistivity, as opposed to silicon. We also know how to handle thin glass for embedded applications. The infrastructure is already available. And we know how to metallize glass. So it’s the best material except for one problem.

SLD: What’s the problem?
Tummala: We have to make holes in glass that are very small, with very high throughput, at very low cost. That’s the main problem we see with glass. But if you solve that problem, then it becomes an ideal material for semiconductor applications.

SLD: So how close are you to solving that?
Tummala: We’ve actually solved most of it. Like everything else, we know how to make glass thin—from 30 to 75 microns in thickness. We developed the process in partnership with the companies we work with to make small holes very fast. We can make more than 1,000 holes in one step. And we know how to metallize. We actually formed an electronic substrate by putting in thin wires and other metal layers, and through-via metallization so we can add components on both sides.

SLD: Who’s behind this effort?
Tummala: We have about 15 companies funding this research. Now we are looking to replace organic packages that are used by companies like Intel, AMD and IBM and almost everyone else. All the smart phones are going to very high-speed images, which will require extremely high logic-to-memory bandwidth. Everyone is moving toward through-silicon vias in every chip. All the semiconductor companies are betting on that technology. I’ve been promoting interposer technology. With glass we think we can substitute for silicon with no TSV in the logic chip and interconnect that with an interposer using extremely high bandwidth. We are looking at other applications, too. I cannot go into the details. But we are running an IEEE workshop here in November on this topic.

SLD: What’s the difference in the thermal coefficient of glass versus silicon?
Tummala: In the case of silicon it’s fixed. It’s 3ppm (parts per million per degree Celsius), plus or minus. In the case of glass, you have options depending on the type of glass you pick. You can go from 3ppm to 9ppm. We think that picking glass at 8ppm, which is between the 3ppm of chips and the organic board at 17 ppm, would put the interposer right in between. That’s the best way to solve that problem.

SLD: Doesn’t that vary depending upon the packaging, as well?
Tummala: Yes, in the case of 3D chips, if you take a lot of real estate with copper vias, you could end up with maybe 6 to 8 ppm for that 3D stack. If you put 5 micron vias on 16 micron centers, which is roughly a third of that area, that’s about 8 ppm.

SLD: Can glass also be a channel for heat or ESD?
Tummala: You can use glass in two ways. One is to isolate, so if you put logic and memory all in one stack you end up heating the memory chips, as well. You don’t want to heat the memory, but you have no choice. If you put logic on one side of glass and memory on the other, the glass works as an insulator. You also can use glass for conductivity. Right now you get rid of heat with heat sinks. We expect our technology of making holes will be so chip compared with silicon that we should be able to metalize a lot of those holes with copper and be able to use that for thermal conductivity. It will be even better than a silicon chip. In theory we should be able to get very high conductivity locally, if you need it, by having copper vias through glass.

SLD: So the glass becomes an insulator around the copper via?
Tummala: Yes, exactly. You end up with a better signal.

SLD: What’s the timing for glass TSVs?
Tummala: We have demonstrated the technology. We know how to make holes and metallize. Now we’re dealing with some of the liabilities and demonstrating them. I would say a two-year time frame is realistic for it to be commercially available.

SLD: Are all the major foundries and chip companies looking at this?
Tummala: Yes. In the last six months, we have moved all these technologies into glass. The next step will be to use glass for chips. We think wafers are good, but they’re too expensive, so we’re looking at panels that are 700mm to 900mm. That will provide hundreds or thousands of interposers. We started looking at glass for cost, but we’re also seeing performance improvements. You get both with glass.

SLD: Is defect density easier to control in glass than silicon?
Tummala: Glass is super smooth. Unlike silicon, which needs to be polished, glass comes out smooth.

SLD: So you don’t need CMP?
Tummala: No, that’s not necessary.

By David Lammers
Intel Corp. dropped a rock into the pond of transistor technology when it announced its 22nm tri-gate technology in San Francisco earlier this month. The ripples continue to move out from that event, with impacts on IDMs, foundries, and fabless semiconductor companies being closely studied.

Now that Intel has come out of the closet with its tri-gate technology, “the foundry customers are all going to ask, ‘When am I going to get a FinFET? What does it look like?’” said one source, who asked not to be identified.

What they may find is a transistor that is rather difficult to build, at least for the companies that lack the resources to make the jump from planar to vertical structures. “Intel’s competitors will all be taking that thing (the tri-gate device) apart. They will learn from it. They will catch up, but it is not automatic and takes time. Intel has shown its technology leadership, but of course they have to invest an enormous amount of money to stay ahead and the competitors have to spend a much smaller amount to copy,” the source said.

Opinions differ on how quickly finFETs will enter the SoC space. At the Intel tri-gate rollout, Intel architecture general manager Dadi Perlmutter said Intel’s goal is to achieve “parity,” rolling out MPUs and SoC products on the latest technology at the same time. The lag is declining node by node, he said.

Planar vs. FinFET

Analyst Nathan Brookwood, sees Intel introducing tri-gate-based, 22nm, Atom-based SoCs for smartphones and tablets in the fourth quarter of 2012. Those “Silvermont” SoCs would be supplanted in 2014 by the 14nm-based “Airmont” SoCs. If that scenario proves accurate, Intel will be on the market with Atom-based and MPU products at the same time in 2014.

If Intel meets its target, and if TSMC rolls its finFET technology in 2015 at the 14nm node, at least two companies would be on vertical transistors for SoCs. There is speculation that TSMC might pursue a planar transistor for low-cost applications at the 14nm generation, using finFETs for the high-performance graphics MPUs, FPGAs, and others. And some believe that Intel will be more active in the foundry space, partly as a way to monetize the estimated $2 billion it took to develop the 22nm tri-gate technology.

Dean Freeman, a manufacturing technology analyst at Gartner Inc., said Intel’s tri-gate technology is impressive. “However, the SOI group won’t give up any ground.” The SOI consortium is working closely with ARM to demonstrate lower power consumption, at 1 to 2 GHz performance, for smart phones. But Freeman said most of those smartphone chips are produced on bulk wafers today, and they will be reluctant to spend much on the additional wafer cost represented by UTB-SOI wafers. Even AMD has switched to bulk (non-SOI) technology for its low-cost Fusion products, he noted.

On the other hand, Freeman said the vertical devices require a big change in the design tools, and a complete redesign of a company’s proprietary intellectual property. “Not all devices need 3D. Tri-gate will be used for Intel’s X86 products, and IBM will go 3D for its high-performance devices. Some high-performance ASSPs might need 3D as well. I am not certain about the ARM devices,” he said.

Gary Patton, an IBM vice president who manages the Fishkill Alliance including Samsung, Toshiba, STMicro, and GlobalFoundries, said the alliance is developing several different transistors for the 14nm node. IBM will continue to develop an SOI technology with finFET transistors, adding its on-chip SOI-based embedded DRAM technology. Other members of the alliance need a bulk FinFET, and others, including STMicroelectronics, are pursuing a planar UTB-SOI approach (which IBM refers to as Extremely Thin (ET)-SOI) using back-gate biasing underneath the planar channel to boost performance or reduce power consumption.

“ET-SOI with a back-bias operation is pretty comparable with finFETs for certain applications. FinFETs are pretty complex, and ST Micro is pretty confident in ET-SOI,” Patton said during a brief interview at the Advanced Semiconductor Manufacturing Conference, held in Saratoga Springs, N.Y., this month. Patton said members of the Fishkill Alliance and IBM Albany will give three papers at the upcoming VLSI Symposium, planned for early June, on SOI finFETs, bulk finFETs and ET-SOI.

“FinFETs have some performance advantages, but Intel and others will have to show that they can control the tolerances, including at the source and drain regions. On the other hand, ET-SOI appears to have some resistance problems, so we’ll have to see how it plays out,” Patton said.

Freeman said the Fishkill Alliance has been a huge success, but warned that the shift to a tri-gate transistor “does give Intel a crack at the mobile device market, as the power consumption is very good.”

The Gartner analyst added, “What IBM needs to look out for is an Intel alliance forming. You already have Toshiba and Samsung working with Intel on some transistor technology, so there could be some cracks forming. There is the possibility of two camps, but Intel is so protective of its IP it will be interesting to see how this plays out.”

Chenming Hu, who led a UC Berkeley team that did much of the early work on both finFETs and UTB-SOI a dozen years ago, said he believes for finFETs and UTB-SOI technology will be deployed. Manufacturing finFETs, with the need for a very thin fin at close tolerances, is challenging for all but the largest companies such as Intel and TSMC.

“If the interface with the design team is close, and the resources are large enough, the lure of finFETs is that they can be scaled. But it does take investments. UTB-SOI does not take as much technology development investment,” Hu said.

UC Berkeley's Hu

“I remain steadfast in my belief that both FinFETs and UTB-SOI will be going to manufacturing,” Hu said. “I expect both to go into production. The very large companies, such as Intel and TSMC, will have the resources to go to FinFETs. Some other companies may go to UTB-SOI. ST Microelectronics is probably the closest to using UTB-SOI. FinFETs may be more versatile in performance and power. On the other hand, FinFETs take a lot more development resources, in terms of the manufacturing control, the layouts, and the libraries. In FinFETs, the gate widths are discrete, rather than continuous. And the thickness of the fin needs to be scaled, along with the gate length.”

Scott Thompson, a professor at the University of Florida, said the manufacturing challenges of finFETs may provide Intel with a five-year lead, or longer.

“Developing a complex technology like tri-gate requires significant investment in silicon resources and manpower—development teams of perhaps more than 1,000 people. The complexities for development mean that hundreds of thousands of wafers have to be run to solve the issues. The tri-gate development is at least an order of magnitude more complex than strained silicon at 90nm, or HKMG at 45nm. That is why it took Intel eight years to implement, and why I don’t think anyone else will have in market for more than five years,” said Thompson, who spent two decades in technology development at Intel’s technology and manufacturing group at Hillsboro, Ore.

Manufacturing perfect fins over billions or trillions transistors is quite a challenge, Thompson said, adding that “it can be done in a fab that runs a single process, with equipment and settings that are kept constant. The manufacturing flow has unique advantages for high-end processors but does have problems supporting several key features needed for SOCs: multiple threshold voltages, and thin and thick oxides in support of analog.”

By Pallab Chatterjee
In the enterprise it’s all about speed and power—as in more speed and less power—and those changes are forcing shifts in the chip architectures as well as the processes used to develop those chips.

At the Linley Data Center Conference the next generation of network control chips were discussed. The keys for the new networks are 10G data lanes to be used with 10G/40G and 100G applications. For 100G the alternate configuration from 10 lanes of 10G was 4 lanes of 25Gb/s also being designed with 40nm.

The 40nm processes give the advantage of the data speed that was needed, plus power savings that are required to keep the reliability of the die and package. The trend is that these high-speed switches need to be available not as single PHYs, but as duals and quads. The 40nm node allows for target power at about 3W for these parts, which will enable 24- and 48-channel switch products.

The PHY that is being provided by most of the vendors can, with the 40nm process, support security data processing. The architecture for many of the high-throughput data systems includes local data analysis, decryption, policy and authentication testing off the early data bus just after the transceivers. These application processors can be on the same die or separate die from the PHY.

In applications where there are separate server processor chips, the trend is toward 32nm processes with multicore configurations. Intel is offering 6- and 10-core products under the Westmere architecture. For the upcoming Sandy Bridge architectures, they are featuring 8 and 12 cores using the 32nm process. On the server processor side, there also are 32nm products from AMD using the new “Bulldozer” architecture. Rounding out the server side there are also new cores from ARM with the Cortex A-15.

For dedicated application processors, a number of multicore processors are now available using 40nm processes. These include the 16-core Octeon from Cavium Networks, the 8-core QorIQ from Freescale, the 4-core ACP3448 from LSI, and the 8-core XLP family of processors from Netlogic Micro. Also in this space is the Netronome NFP-3240, which is a 40-core 40Gbps flow processor that is a co-processor to the Xeon main processor for network traffic handling.

One of the power/performance drivers is the security aspects of the networks. The Federal Information Processing Standards (FIPS) 140 is focused on cryptography and security systems, not on items such as firewalls, Web filters, spam and virus protection, or content and flow control. The cryptographic modules are constantly increasing in complexity of their algorithms and degree of touch of the data.

By Ed Sperling
Mentor Graphics is integrating 6WINDGate software with its embedded Linux platform, which chops a big step out of the development process. It allows developers using Freescale and NetLogic multicore processors to optimize packet-processing performance without re-verifying applications. In the race for re-use, this is a big step forward.

Synopsys expanded its DesignWare Sonic Focus IP, which it picked up with its acquisition of Virage Logic. The IP greatly improves sound quality in low-power DSP-based devices.

MIPS took advantage of the Consumer Electronics Show to roll out a bunch of new products and announcements. From a consumer standpoint, the first MIPS-based smartphones and tablets hit the market based upon SoCs from Actions Semiconductor and Ingenic Semiconductor. MIPS also won a deal to provide its 1004K and 74K cores to MStar Semiconductor for use in DTV. MStar, based in Taiwan, is the No. 1 supplier of ICs for TVs and monitors.

And MIPS introduced its SmartCE—the CE stands for connected entertainment—platform, which integrates Android, Adobe Flash for TV, Skype, Home Jinni ConnecTV and social media on everything from digital TVs to set-top boxes and Blu-ray players. The macro story about Google buddying up with Adobe–Flash still isn’t available in the iPhone, although work is underway—is interesting.

Microsoft announced support for SoC architectures from Intel, AMD and ARM for its next version of Windows. But unless Microsoft can slim down its OS this effort will face the same kinds of power/performance/efficiency issues that have plagued Intel trying to run an x86 OS. What’s particularly interesting here is the emphasis on SoCs, not just processors. Most of the press coverage has been about the dissolution of the Wintel duopoly, but the bigger story is about the growing importance of SoCs. Intel has been talking about this approach for several years, but so far no one outside of Intel has seen much progress. ARM’s whole pitch has been SoC ecosystems, while AMD has fit somewhere in the middle with third-party IP built into its processors.

By Ed Sperling
Synopsys expanded its DesignWare MIPI IP portfolio with support for a handful of new PHY protocols. The trend is an interesting one—big IP companies adding lots of support and configurability, making it far harder for small IP companies to keep pace.

In a similar vein, MIPS joined the MIPI alliance to support standard interfaces for mobile handsets.

SMIC adopted Cadence’s DFM and low-power silicon realization technology for its 65nm reference flow. The silicon realization technology includes a slew of different tools. Across the East China Sea, Fujitsu is supporting Cadence’s C-to-Silicon compiler for high-level synthesis.

Mobileye, which makes camera-based driver assistance systems, is using Arteris’ network on chip IP for its next-gen EyeQ SoCs. This stuff is really cool.

TSMC said its net sales for November dropped 4.4% from October, but before you hit the panic button that’s still up 21.7% from November 2009. One month does not make a trend even though it can cause sleep deprivation.

On the big picture side—literally—AMD, Dell, Intel, Lenovo, Samsung, and LG all said they would phase out analog display technology and move entirely to scalable and lower-power digital interfaces. That spells the end for VGA and LVDS panel interfaces. It might be time to trade in that old monitor.

By Ann Steffora Mutschler
Standards body Accellera is sounding the gong to summon all verification IP providers to check out its efforts in connection with IP-XACT — IEEE 1685, “Standard for IP-XACT, Standard Structure for Packaging, Integrating and Re-Using IP Within Tool-Flows” – with verification IP.

The IP-XACT technical committee has been busy over the past year. Formerly an effort of The SPIRIT Consortium, which merged with Accellera in April, the standard was ratified by the IEEE in June, and has since been downloaded hundreds of times, according to Accellera vice-chair Dennis Brophy, who also serves as director of strategic business development at Mentor Graphics Corp.

“In the first few months of operation we have had several hundred copies downloaded for free,” he noted. “We can predict a very good multi-year trajectory for making the standard easily available to users and consumers, and will help also promote a healthy SoC design environment enabled with IP-XACT.”

IP-XACT, which is an XML schema for meta-data documenting IP and an API that allows tools to access the meta-data, has its roots at STMicroelectronics dating back to 2003. Other vendors involved at a highly visible level include Atrenta, Semifore, NXP Semiconductors, Cadence, Duolog and AMD.

Accellera is well aware what work is not done, and one of the groups inside the standards body is a verification IP technical subcommittee, “whose initial task was to find a way to bring multiple methodologies together so that you could author in one environment and use in another. We proved that through bringing VMM and OVM together so that they could actually work side-by-side and users could author in one and use in the other. We had an open-source kit that users could download in conjunction with their preferred methodology to use and then promote verification IP interoperability,” Brophy explained.

That group took the next step of asking why there isn’t a single standard methodology and have begun work on UVM (universal verification methodology), which intends to bring together the best of all technologies to focus the industry development resources around one methodology – and this is where IP-XACT comes in, he continued.

As a result, the IP-XACT committee relaunched itself over the summer to determine where to go next and are now in the beginning phases of asking themselves that question and inviting other industry participants to join with the committee to start the next phase of development. One of those, interestingly enough, is what can be done to cross-pollinate between the UVM work that is going on, and what impact it will have on IP-XACT. “We know it should have some. IP-XACT has been what I would characterize as a very strong support for design IP that facilitates the design process, but has been a bit weaker in terms of delivery of verification IP,” Brophy observed.

“What Accellera sees is that we really need to have both comprehended in an IP-XACT so we have an ongoing cross-relationship between the technical subcommittees–the IP-XACT group and the VIP group in Accellera. The elements of development that are underway for UVM are, we hope, going to have a positive impact in being able to extend the IP-XACT definition to also comprehend use of verification IP just as the community has done so with design IP. And that is just at its very beginning stages right now,” he said.

While not making any 2011 predictions as to deliverables, Brophy stressed that participants are interested to move forward sooner rather than later, and expects more verification IP companies to join in as they learn about the effort.

For more information, or to download the standard, click here.

By Ed Sperling
Cadence completed its acquisition of Denali, moving the company squarely into the IP business for what amounts to an all-out IP arms race. Several sources have confirmed Cadence bid for Virage Logic first, but was outbid by Synopsys. Cadence subsequently made the $315 million offer for Denali. The selling price has lots of companies hanging out a “for sale” sign. The big question is who’s next?

ARM, the Common Platform companies (IBM, Samsung and GlobalFoundries) and Synopsys introduced a 32/28nm high k/metal gate that is “vertically optimized.” Exactly what “vertically optimized” means is something of a mystery, however. You won’t find any additional information about this in the release or in any of the links.

Mentor Graphics and Synopsys both updated some of their top tool suites at DAC, not to mention their relationships with foundries. Mentor is collaborating with GlobalFoundries on an advanced design and manufacturing flow using Calibre.  It also added verification, extraction and DFM support for TSMC’s AMS 1.0 flow, as well as ESL, integrated design, and manufacturing closure for TSMC’s Reference Flow 11.  In addition, Mentor’s Olympus SoC place and route is now supported by X-FAB.

Synopsys improved its PrimeTime performance for static timing analysis, migrated its Ly-nx pre-validated design environment for the Common Platform’s 32/28nm nodes. It also introduced a Galaxy characterization solution for standard cells, complex macros and memories, and it added StarRC custom 3D extraction for sub-45nm designs.

Cadence also provided its contribution to the Universal Verification Methodology, aka UVM—an open-source reference flow for SoC verification.

Atrenta introduced SpyGlass-Physical for physical implementation modeling. There was a lot of talk about tradeoff analysis and what-if approaches at DAC this year.

http://www.atrenta.com/atrenta-news/96.news

AMD inked a deal for Apache Design Systems’ power supply noise and reliability sign-off tools. Considering the close relationship between AMD and GlobalFoundries, this becomes particularly interesting.