By Ed Sperling
There are two big issues when it comes to through-silicon vias. One involves cost. The second involves heat—in particular, how to get heat out of a stacked die and what the thermal coefficient of the TSV will be to make sure it expands at a rate consistent with the SoCs in a package.

To address these issues, System-Level Design caught up with Rao Tummala, professor of electrical and computer engineering and material sciences, as well as the director of the 3D Systems Packaging Research Center at Georgia Institute of Technology, where work has been under way for several years to address these issues. What follows are excerpts of that conversation.

SLD: Why use glass?
Tummala: There are a number reasons. One is that it can be done pinless. A second reason is that it’s highly insulating, with extremely high resistivity, as opposed to silicon. We also know how to handle thin glass for embedded applications. The infrastructure is already available. And we know how to metallize glass. So it’s the best material except for one problem.

SLD: What’s the problem?
Tummala: We have to make holes in glass that are very small, with very high throughput, at very low cost. That’s the main problem we see with glass. But if you solve that problem, then it becomes an ideal material for semiconductor applications.

SLD: So how close are you to solving that?
Tummala: We’ve actually solved most of it. Like everything else, we know how to make glass thin—from 30 to 75 microns in thickness. We developed the process in partnership with the companies we work with to make small holes very fast. We can make more than 1,000 holes in one step. And we know how to metallize. We actually formed an electronic substrate by putting in thin wires and other metal layers, and through-via metallization so we can add components on both sides.

SLD: Who’s behind this effort?
Tummala: We have about 15 companies funding this research. Now we are looking to replace organic packages that are used by companies like Intel, AMD and IBM and almost everyone else. All the smart phones are going to very high-speed images, which will require extremely high logic-to-memory bandwidth. Everyone is moving toward through-silicon vias in every chip. All the semiconductor companies are betting on that technology. I’ve been promoting interposer technology. With glass we think we can substitute for silicon with no TSV in the logic chip and interconnect that with an interposer using extremely high bandwidth. We are looking at other applications, too. I cannot go into the details. But we are running an IEEE workshop here in November on this topic.

SLD: What’s the difference in the thermal coefficient of glass versus silicon?
Tummala: In the case of silicon it’s fixed. It’s 3ppm (parts per million per degree Celsius), plus or minus. In the case of glass, you have options depending on the type of glass you pick. You can go from 3ppm to 9ppm. We think that picking glass at 8ppm, which is between the 3ppm of chips and the organic board at 17 ppm, would put the interposer right in between. That’s the best way to solve that problem.

SLD: Doesn’t that vary depending upon the packaging, as well?
Tummala: Yes, in the case of 3D chips, if you take a lot of real estate with copper vias, you could end up with maybe 6 to 8 ppm for that 3D stack. If you put 5 micron vias on 16 micron centers, which is roughly a third of that area, that’s about 8 ppm.

SLD: Can glass also be a channel for heat or ESD?
Tummala: You can use glass in two ways. One is to isolate, so if you put logic and memory all in one stack you end up heating the memory chips, as well. You don’t want to heat the memory, but you have no choice. If you put logic on one side of glass and memory on the other, the glass works as an insulator. You also can use glass for conductivity. Right now you get rid of heat with heat sinks. We expect our technology of making holes will be so chip compared with silicon that we should be able to metalize a lot of those holes with copper and be able to use that for thermal conductivity. It will be even better than a silicon chip. In theory we should be able to get very high conductivity locally, if you need it, by having copper vias through glass.

SLD: So the glass becomes an insulator around the copper via?
Tummala: Yes, exactly. You end up with a better signal.

SLD: What’s the timing for glass TSVs?
Tummala: We have demonstrated the technology. We know how to make holes and metallize. Now we’re dealing with some of the liabilities and demonstrating them. I would say a two-year time frame is realistic for it to be commercially available.

SLD: Are all the major foundries and chip companies looking at this?
Tummala: Yes. In the last six months, we have moved all these technologies into glass. The next step will be to use glass for chips. We think wafers are good, but they’re too expensive, so we’re looking at panels that are 700mm to 900mm. That will provide hundreds or thousands of interposers. We started looking at glass for cost, but we’re also seeing performance improvements. You get both with glass.

SLD: Is defect density easier to control in glass than silicon?
Tummala: Glass is super smooth. Unlike silicon, which needs to be polished, glass comes out smooth.

SLD: So you don’t need CMP?
Tummala: No, that’s not necessary.

By David Lammers
Intel Corp. dropped a rock into the pond of transistor technology when it announced its 22nm tri-gate technology in San Francisco earlier this month. The ripples continue to move out from that event, with impacts on IDMs, foundries, and fabless semiconductor companies being closely studied.

Now that Intel has come out of the closet with its tri-gate technology, “the foundry customers are all going to ask, ‘When am I going to get a FinFET? What does it look like?’” said one source, who asked not to be identified.

What they may find is a transistor that is rather difficult to build, at least for the companies that lack the resources to make the jump from planar to vertical structures. “Intel’s competitors will all be taking that thing (the tri-gate device) apart. They will learn from it. They will catch up, but it is not automatic and takes time. Intel has shown its technology leadership, but of course they have to invest an enormous amount of money to stay ahead and the competitors have to spend a much smaller amount to copy,” the source said.

Opinions differ on how quickly finFETs will enter the SoC space. At the Intel tri-gate rollout, Intel architecture general manager Dadi Perlmutter said Intel’s goal is to achieve “parity,” rolling out MPUs and SoC products on the latest technology at the same time. The lag is declining node by node, he said.

Planar vs. FinFET

Analyst Nathan Brookwood, sees Intel introducing tri-gate-based, 22nm, Atom-based SoCs for smartphones and tablets in the fourth quarter of 2012. Those “Silvermont” SoCs would be supplanted in 2014 by the 14nm-based “Airmont” SoCs. If that scenario proves accurate, Intel will be on the market with Atom-based and MPU products at the same time in 2014.

If Intel meets its target, and if TSMC rolls its finFET technology in 2015 at the 14nm node, at least two companies would be on vertical transistors for SoCs. There is speculation that TSMC might pursue a planar transistor for low-cost applications at the 14nm generation, using finFETs for the high-performance graphics MPUs, FPGAs, and others. And some believe that Intel will be more active in the foundry space, partly as a way to monetize the estimated $2 billion it took to develop the 22nm tri-gate technology.

Dean Freeman, a manufacturing technology analyst at Gartner Inc., said Intel’s tri-gate technology is impressive. “However, the SOI group won’t give up any ground.” The SOI consortium is working closely with ARM to demonstrate lower power consumption, at 1 to 2 GHz performance, for smart phones. But Freeman said most of those smartphone chips are produced on bulk wafers today, and they will be reluctant to spend much on the additional wafer cost represented by UTB-SOI wafers. Even AMD has switched to bulk (non-SOI) technology for its low-cost Fusion products, he noted.

On the other hand, Freeman said the vertical devices require a big change in the design tools, and a complete redesign of a company’s proprietary intellectual property. “Not all devices need 3D. Tri-gate will be used for Intel’s X86 products, and IBM will go 3D for its high-performance devices. Some high-performance ASSPs might need 3D as well. I am not certain about the ARM devices,” he said.

Gary Patton, an IBM vice president who manages the Fishkill Alliance including Samsung, Toshiba, STMicro, and GlobalFoundries, said the alliance is developing several different transistors for the 14nm node. IBM will continue to develop an SOI technology with finFET transistors, adding its on-chip SOI-based embedded DRAM technology. Other members of the alliance need a bulk FinFET, and others, including STMicroelectronics, are pursuing a planar UTB-SOI approach (which IBM refers to as Extremely Thin (ET)-SOI) using back-gate biasing underneath the planar channel to boost performance or reduce power consumption.

“ET-SOI with a back-bias operation is pretty comparable with finFETs for certain applications. FinFETs are pretty complex, and ST Micro is pretty confident in ET-SOI,” Patton said during a brief interview at the Advanced Semiconductor Manufacturing Conference, held in Saratoga Springs, N.Y., this month. Patton said members of the Fishkill Alliance and IBM Albany will give three papers at the upcoming VLSI Symposium, planned for early June, on SOI finFETs, bulk finFETs and ET-SOI.

“FinFETs have some performance advantages, but Intel and others will have to show that they can control the tolerances, including at the source and drain regions. On the other hand, ET-SOI appears to have some resistance problems, so we’ll have to see how it plays out,” Patton said.

Freeman said the Fishkill Alliance has been a huge success, but warned that the shift to a tri-gate transistor “does give Intel a crack at the mobile device market, as the power consumption is very good.”

The Gartner analyst added, “What IBM needs to look out for is an Intel alliance forming. You already have Toshiba and Samsung working with Intel on some transistor technology, so there could be some cracks forming. There is the possibility of two camps, but Intel is so protective of its IP it will be interesting to see how this plays out.”

Chenming Hu, who led a UC Berkeley team that did much of the early work on both finFETs and UTB-SOI a dozen years ago, said he believes for finFETs and UTB-SOI technology will be deployed. Manufacturing finFETs, with the need for a very thin fin at close tolerances, is challenging for all but the largest companies such as Intel and TSMC.

“If the interface with the design team is close, and the resources are large enough, the lure of finFETs is that they can be scaled. But it does take investments. UTB-SOI does not take as much technology development investment,” Hu said.

UC Berkeley's Hu

“I remain steadfast in my belief that both FinFETs and UTB-SOI will be going to manufacturing,” Hu said. “I expect both to go into production. The very large companies, such as Intel and TSMC, will have the resources to go to FinFETs. Some other companies may go to UTB-SOI. ST Microelectronics is probably the closest to using UTB-SOI. FinFETs may be more versatile in performance and power. On the other hand, FinFETs take a lot more development resources, in terms of the manufacturing control, the layouts, and the libraries. In FinFETs, the gate widths are discrete, rather than continuous. And the thickness of the fin needs to be scaled, along with the gate length.”

Scott Thompson, a professor at the University of Florida, said the manufacturing challenges of finFETs may provide Intel with a five-year lead, or longer.

“Developing a complex technology like tri-gate requires significant investment in silicon resources and manpower—development teams of perhaps more than 1,000 people. The complexities for development mean that hundreds of thousands of wafers have to be run to solve the issues. The tri-gate development is at least an order of magnitude more complex than strained silicon at 90nm, or HKMG at 45nm. That is why it took Intel eight years to implement, and why I don’t think anyone else will have in market for more than five years,” said Thompson, who spent two decades in technology development at Intel’s technology and manufacturing group at Hillsboro, Ore.

Manufacturing perfect fins over billions or trillions transistors is quite a challenge, Thompson said, adding that “it can be done in a fab that runs a single process, with equipment and settings that are kept constant. The manufacturing flow has unique advantages for high-end processors but does have problems supporting several key features needed for SOCs: multiple threshold voltages, and thin and thick oxides in support of analog.”

By Pallab Chatterjee
In the enterprise it’s all about speed and power—as in more speed and less power—and those changes are forcing shifts in the chip architectures as well as the processes used to develop those chips.

At the Linley Data Center Conference the next generation of network control chips were discussed. The keys for the new networks are 10G data lanes to be used with 10G/40G and 100G applications. For 100G the alternate configuration from 10 lanes of 10G was 4 lanes of 25Gb/s also being designed with 40nm.

The 40nm processes give the advantage of the data speed that was needed, plus power savings that are required to keep the reliability of the die and package. The trend is that these high-speed switches need to be available not as single PHYs, but as duals and quads. The 40nm node allows for target power at about 3W for these parts, which will enable 24- and 48-channel switch products.

The PHY that is being provided by most of the vendors can, with the 40nm process, support security data processing. The architecture for many of the high-throughput data systems includes local data analysis, decryption, policy and authentication testing off the early data bus just after the transceivers. These application processors can be on the same die or separate die from the PHY.

In applications where there are separate server processor chips, the trend is toward 32nm processes with multicore configurations. Intel is offering 6- and 10-core products under the Westmere architecture. For the upcoming Sandy Bridge architectures, they are featuring 8 and 12 cores using the 32nm process. On the server processor side, there also are 32nm products from AMD using the new “Bulldozer” architecture. Rounding out the server side there are also new cores from ARM with the Cortex A-15.

For dedicated application processors, a number of multicore processors are now available using 40nm processes. These include the 16-core Octeon from Cavium Networks, the 8-core QorIQ from Freescale, the 4-core ACP3448 from LSI, and the 8-core XLP family of processors from Netlogic Micro. Also in this space is the Netronome NFP-3240, which is a 40-core 40Gbps flow processor that is a co-processor to the Xeon main processor for network traffic handling.

One of the power/performance drivers is the security aspects of the networks. The Federal Information Processing Standards (FIPS) 140 is focused on cryptography and security systems, not on items such as firewalls, Web filters, spam and virus protection, or content and flow control. The cryptographic modules are constantly increasing in complexity of their algorithms and degree of touch of the data.

By Ed Sperling
Mentor Graphics is integrating 6WINDGate software with its embedded Linux platform, which chops a big step out of the development process. It allows developers using Freescale and NetLogic multicore processors to optimize packet-processing performance without re-verifying applications. In the race for re-use, this is a big step forward.

Synopsys expanded its DesignWare Sonic Focus IP, which it picked up with its acquisition of Virage Logic. The IP greatly improves sound quality in low-power DSP-based devices.

MIPS took advantage of the Consumer Electronics Show to roll out a bunch of new products and announcements. From a consumer standpoint, the first MIPS-based smartphones and tablets hit the market based upon SoCs from Actions Semiconductor and Ingenic Semiconductor. MIPS also won a deal to provide its 1004K and 74K cores to MStar Semiconductor for use in DTV. MStar, based in Taiwan, is the No. 1 supplier of ICs for TVs and monitors.

And MIPS introduced its SmartCE—the CE stands for connected entertainment—platform, which integrates Android, Adobe Flash for TV, Skype, Home Jinni ConnecTV and social media on everything from digital TVs to set-top boxes and Blu-ray players. The macro story about Google buddying up with Adobe–Flash still isn’t available in the iPhone, although work is underway—is interesting.

Microsoft announced support for SoC architectures from Intel, AMD and ARM for its next version of Windows. But unless Microsoft can slim down its OS this effort will face the same kinds of power/performance/efficiency issues that have plagued Intel trying to run an x86 OS. What’s particularly interesting here is the emphasis on SoCs, not just processors. Most of the press coverage has been about the dissolution of the Wintel duopoly, but the bigger story is about the growing importance of SoCs. Intel has been talking about this approach for several years, but so far no one outside of Intel has seen much progress. ARM’s whole pitch has been SoC ecosystems, while AMD has fit somewhere in the middle with third-party IP built into its processors.

By Ed Sperling
Synopsys expanded its DesignWare MIPI IP portfolio with support for a handful of new PHY protocols. The trend is an interesting one—big IP companies adding lots of support and configurability, making it far harder for small IP companies to keep pace.

In a similar vein, MIPS joined the MIPI alliance to support standard interfaces for mobile handsets.

SMIC adopted Cadence’s DFM and low-power silicon realization technology for its 65nm reference flow. The silicon realization technology includes a slew of different tools. Across the East China Sea, Fujitsu is supporting Cadence’s C-to-Silicon compiler for high-level synthesis.

Mobileye, which makes camera-based driver assistance systems, is using Arteris’ network on chip IP for its next-gen EyeQ SoCs. This stuff is really cool.

TSMC said its net sales for November dropped 4.4% from October, but before you hit the panic button that’s still up 21.7% from November 2009. One month does not make a trend even though it can cause sleep deprivation.

On the big picture side—literally—AMD, Dell, Intel, Lenovo, Samsung, and LG all said they would phase out analog display technology and move entirely to scalable and lower-power digital interfaces. That spells the end for VGA and LVDS panel interfaces. It might be time to trade in that old monitor.

By Ann Steffora Mutschler
Standards body Accellera is sounding the gong to summon all verification IP providers to check out its efforts in connection with IP-XACT — IEEE 1685, “Standard for IP-XACT, Standard Structure for Packaging, Integrating and Re-Using IP Within Tool-Flows” – with verification IP.

The IP-XACT technical committee has been busy over the past year. Formerly an effort of The SPIRIT Consortium, which merged with Accellera in April, the standard was ratified by the IEEE in June, and has since been downloaded hundreds of times, according to Accellera vice-chair Dennis Brophy, who also serves as director of strategic business development at Mentor Graphics Corp.

“In the first few months of operation we have had several hundred copies downloaded for free,” he noted. “We can predict a very good multi-year trajectory for making the standard easily available to users and consumers, and will help also promote a healthy SoC design environment enabled with IP-XACT.”

IP-XACT, which is an XML schema for meta-data documenting IP and an API that allows tools to access the meta-data, has its roots at STMicroelectronics dating back to 2003. Other vendors involved at a highly visible level include Atrenta, Semifore, NXP Semiconductors, Cadence, Duolog and AMD.

Accellera is well aware what work is not done, and one of the groups inside the standards body is a verification IP technical subcommittee, “whose initial task was to find a way to bring multiple methodologies together so that you could author in one environment and use in another. We proved that through bringing VMM and OVM together so that they could actually work side-by-side and users could author in one and use in the other. We had an open-source kit that users could download in conjunction with their preferred methodology to use and then promote verification IP interoperability,” Brophy explained.

That group took the next step of asking why there isn’t a single standard methodology and have begun work on UVM (universal verification methodology), which intends to bring together the best of all technologies to focus the industry development resources around one methodology – and this is where IP-XACT comes in, he continued.

As a result, the IP-XACT committee relaunched itself over the summer to determine where to go next and are now in the beginning phases of asking themselves that question and inviting other industry participants to join with the committee to start the next phase of development. One of those, interestingly enough, is what can be done to cross-pollinate between the UVM work that is going on, and what impact it will have on IP-XACT. “We know it should have some. IP-XACT has been what I would characterize as a very strong support for design IP that facilitates the design process, but has been a bit weaker in terms of delivery of verification IP,” Brophy observed.

“What Accellera sees is that we really need to have both comprehended in an IP-XACT so we have an ongoing cross-relationship between the technical subcommittees–the IP-XACT group and the VIP group in Accellera. The elements of development that are underway for UVM are, we hope, going to have a positive impact in being able to extend the IP-XACT definition to also comprehend use of verification IP just as the community has done so with design IP. And that is just at its very beginning stages right now,” he said.

While not making any 2011 predictions as to deliverables, Brophy stressed that participants are interested to move forward sooner rather than later, and expects more verification IP companies to join in as they learn about the effort.

For more information, or to download the standard, click here.

By Ed Sperling
Cadence completed its acquisition of Denali, moving the company squarely into the IP business for what amounts to an all-out IP arms race. Several sources have confirmed Cadence bid for Virage Logic first, but was outbid by Synopsys. Cadence subsequently made the $315 million offer for Denali. The selling price has lots of companies hanging out a “for sale” sign. The big question is who’s next?

ARM, the Common Platform companies (IBM, Samsung and GlobalFoundries) and Synopsys introduced a 32/28nm high k/metal gate that is “vertically optimized.” Exactly what “vertically optimized” means is something of a mystery, however. You won’t find any additional information about this in the release or in any of the links.

Mentor Graphics and Synopsys both updated some of their top tool suites at DAC, not to mention their relationships with foundries. Mentor is collaborating with GlobalFoundries on an advanced design and manufacturing flow using Calibre.  It also added verification, extraction and DFM support for TSMC’s AMS 1.0 flow, as well as ESL, integrated design, and manufacturing closure for TSMC’s Reference Flow 11.  In addition, Mentor’s Olympus SoC place and route is now supported by X-FAB.

Synopsys improved its PrimeTime performance for static timing analysis, migrated its Ly-nx pre-validated design environment for the Common Platform’s 32/28nm nodes. It also introduced a Galaxy characterization solution for standard cells, complex macros and memories, and it added StarRC custom 3D extraction for sub-45nm designs.

Cadence also provided its contribution to the Universal Verification Methodology, aka UVM—an open-source reference flow for SoC verification.

Atrenta introduced SpyGlass-Physical for physical implementation modeling. There was a lot of talk about tradeoff analysis and what-if approaches at DAC this year.

http://www.atrenta.com/atrenta-news/96.news

AMD inked a deal for Apache Design Systems’ power supply noise and reliability sign-off tools. Considering the close relationship between AMD and GlobalFoundries, this becomes particularly interesting.

By Ed Sperling

Actel’s ProASIC FPGAs are all over the new Boeing 787, which is supposed to be significantly more fuel-efficient than previous Boeing jets. Actel has been developing chips that use flash instead of SRAM to make them more resistant to single-event upsets caused by stray neutrons, which are about 150 times more prevalent at 35,000 feet than at sea level.

Synopsys began laying the groundwork for the next big market, namely India. The company’s VLSI design curriculum was adopted by five regional centers of excellence. This is similar to what many of the EDA players did in China at the beginning of the last decade.

AMD raked in $1.65 billion in sales in Q4, up 18% from the previous quarter and up 42% from the same period in 2008. The company also reported a profit of $1.18 billion. But dig a little further into the numbers and you find that Intel paid AMD $1.25 billion to settle its longstanding dispute. How long can AMD live on the Intel settlement and can it reach profitability on its own before the money runs out?

Rambus settled its longstanding patent infringement case against Samsung, taking home $900 million. But the bigger win may be a joint development deal between the companies to work together on a variety of new memory technologies.

By Ed Sperling

It was a bad week for law firms, a good week for system engineers. But then again, what week isn’t good for system engineers?

Arteris made NoCs available for the masses—or at least for any chip with a bus. Given the complexity of even simple designs these days as even they move down the Moore’s Law curve to finer and finer geometries, this certainly can’t hurt. And understanding interconnects at the front end can make lots of things easier at the back end.

Along those same lines of growing complexity, Cavium signed a definitive agreement to acquire MontaVista Software, which makes embedded Linux. This is somewhat comparable to Intel buying Wind River for its real-time operating systems. It’s all about writing software that fits the core—and making the core fit the software. So much for the homogeneous core approach.

Lawyers take note: All those billable hours are going away. TSMC settled its IP theft litigation with SMIC. In a rather bizarrely worded announcement, TSMC said “the litigation and settlement have resulted in the full protection of TSMC’s trade secrets in the possession of SMIC.” And unlike in the U.S. courts, where settlements are kept quiet, SMIC has agreed to pay TSMC $200 million, which is in addition to the $135 million it paid in 2005. TSMC’s chairman, Morris Chang, said the case had been “amicably resolved.” Compared to what?

Also on the side of calling off the lawyers, AMD and Intel settled their patent disputes. Could it be that the two companies are playing together nicely? Hardly. Intel agreed to pay AMD $1.2 billion, which is probably cheap considering how much attention AMD has called to Intel’s business practices.

On the communications front, Pigeon Point Systems is now including Polaris Networks testers for formal validation of new releases of its xTCA line. This gives new meaning to in-line testing.

By Ed Sperling

As the semiconductor industry digs out from one of the worst downturns in decades, the business of semiconductor design and engineering is changing. While the architecture and features are still being developed by chip companies, the actual work of developing the chip increasingly is being done by third parties.

Outsourcing is hardly new concept in business. In the early part of the 20th century, most automobile makers recognized that it was far more efficient to design a car than produce the parts needed to run it. Outsourcing the design itself, however, has never proven successful because otherwise there would be no differentiation from one manufacturer to the next.

Even within this outsourcing there is specialization and stratification.

IDMs as foundries

Over the past decade, almost all the major integrated device manufacturers have offered foundry services to customers to help offset these costs, usually within the bounds of very restrictive designs. IBM, AMD, Toshiba and now Intel have all taken this approach, and so far none has been particularly successful. Others, such as Texas Instruments, have handed their manufacturing over to major foundries and given up trying to keep pace with rising costs for digital or advanced mixed signal chips.

The latest player to put a stake in this market is Globalfoundries, the AMD joint venture with Advanced Technology Investment Company (ATIC), the investment arm of the Abu Dhabi government that recently announced its intention to buy Chartered Semiconductor. Globalfoundries’ approach is to become a virtual IDM, creating design kits, IP, processes, and even transistor tuning and metal stacks. It does not do the place and route, however, which some of the other IDM foundries have done in the past.

“What we’re doing differently is providing feedback to customers,” said Subramani Kengeri, vice president of design solutions at Globalfoundries. “The disaggregated supply chain model was broken. We’re able to provide very early access, certification for IP—that’s product grade qualification—and we can emulate an SoC so the building blocks are verified at almost the SoC level. We also have a ‘gate first’ approach, while Intel has a ‘gate last’ approach. That gives us more than two times the gate density, and we offer SOI for super high performance.”

This is no ordinary foundry play, and Intel’s approach is to focus on a menu of possible services ranging from power and memory choices to the number of layers and transistor strategy. (See Figure 1) Paul Otellini, Intel president and CEO, said at the Intel Developer Forum last month that he expects SoCs to surpass processors as the company’s revenue stream over the next decade.

Figure 1: Intel's SoC offering.

IBM, meanwhile, has been offering what it calls end-to-end integration from design to manufacturing to characterization and test, and Toshiba has been providing complete design services for the past several years.

How successful these ventures are is unknown. None of these companies break out their revenues for these operations.

Foundries as design houses

While the IDMs seek to recoup their development costs with design and manufacturing services, pure-play foundries aren’t looking so pure-play anymore, either.

The problem with the pure-play model is that majority of designs are being manufactured at older process nodes, which is not where foundries can generate the highest profit. It’s also not where they gain the money to develop new processors or the experience on those new processes to mature them, thereby simplifying the move to the most advanced nodes and amortizing the whole investment.

This explains why TSMC took a 49% stake in Global Unichip Corp. six years ago (it has since reduced that investment), and why the big names on the GUC board of directors are the same ones on TSMC’s board. In fact, looking at the two boards it’s hard to differentiate the companies.

Rival UMC, meanwhile, struck a design services agreement with Bangalore-based Wipro Technologies for the entire design cycle for ASICs and SoCs.

Until recently, when ATIC made a bid for Chartered, it was Chartered that was claiming it was the last major pure-play foundry because of these outside relationships.

Design houses as advanced chip engineers

The last piece to change in the supply chain is the one that was predicted first—but differently. As designs become more complicated and time-to-market pressures mount for companies, many thought they would outsource some of their older designs to companies that could churn them out relatively cheaply while focusing design work on the bleeding edge of Moore’s Law.

What’s happened, however, is quite different from the predictions. Companies like eSilicon and OpenSilicon are now developing much more complex designs than anyone would have guessed. In fact, eSilicon now views 40nm as mainstream, according to Prasad Subramaniam, the company’s vice president of design technology.

Subramaniam notes that complexity is becoming so great that it’s difficult for many companies to turn out a chip or two every year. Engineers don’t have enough experience with some of the tools and difficult techniques such as multiple power islands and complex verification to work at these nodes.

Open-Silicon has reached the same conclusion after initially pitching its design services for older process nodes.

“The downturn convinced people to outsource,” said Naveed Sherwani, Open-Silicon’s president and CEO. “Three years ago our customers were startups. Now they’re large companies. We’re finding that our real competition now is the internal teams within these companies. The VP of engineering services now sees us as competition. We’re writing RTL for them.”