By Ed Sperling

Actel’s ProASIC FPGAs are all over the new Boeing 787, which is supposed to be significantly more fuel-efficient than previous Boeing jets. Actel has been developing chips that use flash instead of SRAM to make them more resistant to single-event upsets caused by stray neutrons, which are about 150 times more prevalent at 35,000 feet than at sea level.

Synopsys began laying the groundwork for the next big market, namely India. The company’s VLSI design curriculum was adopted by five regional centers of excellence. This is similar to what many of the EDA players did in China at the beginning of the last decade.

AMD raked in $1.65 billion in sales in Q4, up 18% from the previous quarter and up 42% from the same period in 2008. The company also reported a profit of $1.18 billion. But dig a little further into the numbers and you find that Intel paid AMD $1.25 billion to settle its longstanding dispute. How long can AMD live on the Intel settlement and can it reach profitability on its own before the money runs out?

Rambus settled its longstanding patent infringement case against Samsung, taking home $900 million. But the bigger win may be a joint development deal between the companies to work together on a variety of new memory technologies.

By Ed Sperling

It was a bad week for law firms, a good week for system engineers. But then again, what week isn’t good for system engineers?

Arteris made NoCs available for the masses—or at least for any chip with a bus. Given the complexity of even simple designs these days as even they move down the Moore’s Law curve to finer and finer geometries, this certainly can’t hurt. And understanding interconnects at the front end can make lots of things easier at the back end.

Along those same lines of growing complexity, Cavium signed a definitive agreement to acquire MontaVista Software, which makes embedded Linux. This is somewhat comparable to Intel buying Wind River for its real-time operating systems. It’s all about writing software that fits the core—and making the core fit the software. So much for the homogeneous core approach.

Lawyers take note: All those billable hours are going away. TSMC settled its IP theft litigation with SMIC. In a rather bizarrely worded announcement, TSMC said “the litigation and settlement have resulted in the full protection of TSMC’s trade secrets in the possession of SMIC.” And unlike in the U.S. courts, where settlements are kept quiet, SMIC has agreed to pay TSMC $200 million, which is in addition to the $135 million it paid in 2005. TSMC’s chairman, Morris Chang, said the case had been “amicably resolved.” Compared to what?

Also on the side of calling off the lawyers, AMD and Intel settled their patent disputes. Could it be that the two companies are playing together nicely? Hardly. Intel agreed to pay AMD $1.2 billion, which is probably cheap considering how much attention AMD has called to Intel’s business practices.

On the communications front, Pigeon Point Systems is now including Polaris Networks testers for formal validation of new releases of its xTCA line. This gives new meaning to in-line testing.

By Ed Sperling

As the semiconductor industry digs out from one of the worst downturns in decades, the business of semiconductor design and engineering is changing. While the architecture and features are still being developed by chip companies, the actual work of developing the chip increasingly is being done by third parties.

Outsourcing is hardly new concept in business. In the early part of the 20th century, most automobile makers recognized that it was far more efficient to design a car than produce the parts needed to run it. Outsourcing the design itself, however, has never proven successful because otherwise there would be no differentiation from one manufacturer to the next.

Even within this outsourcing there is specialization and stratification.

IDMs as foundries

Over the past decade, almost all the major integrated device manufacturers have offered foundry services to customers to help offset these costs, usually within the bounds of very restrictive designs. IBM, AMD, Toshiba and now Intel have all taken this approach, and so far none has been particularly successful. Others, such as Texas Instruments, have handed their manufacturing over to major foundries and given up trying to keep pace with rising costs for digital or advanced mixed signal chips.

The latest player to put a stake in this market is Globalfoundries, the AMD joint venture with Advanced Technology Investment Company (ATIC), the investment arm of the Abu Dhabi government that recently announced its intention to buy Chartered Semiconductor. Globalfoundries’ approach is to become a virtual IDM, creating design kits, IP, processes, and even transistor tuning and metal stacks. It does not do the place and route, however, which some of the other IDM foundries have done in the past.

“What we’re doing differently is providing feedback to customers,” said Subramani Kengeri, vice president of design solutions at Globalfoundries. “The disaggregated supply chain model was broken. We’re able to provide very early access, certification for IP—that’s product grade qualification—and we can emulate an SoC so the building blocks are verified at almost the SoC level. We also have a ‘gate first’ approach, while Intel has a ‘gate last’ approach. That gives us more than two times the gate density, and we offer SOI for super high performance.”

This is no ordinary foundry play, and Intel’s approach is to focus on a menu of possible services ranging from power and memory choices to the number of layers and transistor strategy. (See Figure 1) Paul Otellini, Intel president and CEO, said at the Intel Developer Forum last month that he expects SoCs to surpass processors as the company’s revenue stream over the next decade.

Figure 1: Intel's SoC offering.

IBM, meanwhile, has been offering what it calls end-to-end integration from design to manufacturing to characterization and test, and Toshiba has been providing complete design services for the past several years.

How successful these ventures are is unknown. None of these companies break out their revenues for these operations.

Foundries as design houses

While the IDMs seek to recoup their development costs with design and manufacturing services, pure-play foundries aren’t looking so pure-play anymore, either.

The problem with the pure-play model is that majority of designs are being manufactured at older process nodes, which is not where foundries can generate the highest profit. It’s also not where they gain the money to develop new processors or the experience on those new processes to mature them, thereby simplifying the move to the most advanced nodes and amortizing the whole investment.

This explains why TSMC took a 49% stake in Global Unichip Corp. six years ago (it has since reduced that investment), and why the big names on the GUC board of directors are the same ones on TSMC’s board. In fact, looking at the two boards it’s hard to differentiate the companies.

Rival UMC, meanwhile, struck a design services agreement with Bangalore-based Wipro Technologies for the entire design cycle for ASICs and SoCs.

Until recently, when ATIC made a bid for Chartered, it was Chartered that was claiming it was the last major pure-play foundry because of these outside relationships.

Design houses as advanced chip engineers

The last piece to change in the supply chain is the one that was predicted first—but differently. As designs become more complicated and time-to-market pressures mount for companies, many thought they would outsource some of their older designs to companies that could churn them out relatively cheaply while focusing design work on the bleeding edge of Moore’s Law.

What’s happened, however, is quite different from the predictions. Companies like eSilicon and OpenSilicon are now developing much more complex designs than anyone would have guessed. In fact, eSilicon now views 40nm as mainstream, according to Prasad Subramaniam, the company’s vice president of design technology.

Subramaniam notes that complexity is becoming so great that it’s difficult for many companies to turn out a chip or two every year. Engineers don’t have enough experience with some of the tools and difficult techniques such as multiple power islands and complex verification to work at these nodes.

Open-Silicon has reached the same conclusion after initially pitching its design services for older process nodes.

“The downturn convinced people to outsource,” said Naveed Sherwani, Open-Silicon’s president and CEO. “Three years ago our customers were startups. Now they’re large companies. We’re finding that our real competition now is the internal teams within these companies. The VP of engineering services now sees us as competition. We’re writing RTL for them.”

By Ed Sperling

It was the best of times, it was the worst of times, but for the overall EDA industry it was clearly the latter. For the first time in its history, EDA suffered two successive quarters of negative sales compared with the previous year. There were a few bright spots—signal integrity tools, hardware-assisted verification and resolution enhancement—but the overall market had the Dickens beaten out of it.

Intellectual property, meanwhile, had a good week. Virage Logic capitalized on its relationship with AMD—and AMD’s intense focus on its core business—introducing a new line of IP for a variety of interfaces such as PCI Express and HDMI. This also moves Virage squarely into the IBM ecosystem, where AMD is a key development partner.

Accellera, meanwhile, approved a verification IP standard best practices guide, based upon the work of its VIP technical subcommittee in May 2008. The guide provides details about how to use VIP components developed with SystemVerilog testbenches based upon both OVM and VMM. That should make the dueling parties happy—even though everyone at the standards groups insists it doesn’t matter and there is no rift between OVM and VMM.

Also in the IP world, Broadcom licensed the latest ARM Cortex A9 multiprocessor technology. In the ARM vs. Intel war, this is one place that Intel hasn’t made many inroads yet.

The Common Platform qualified Synopsys’ IC validator for 32nm design rule checking. Considering the Common Platform has been narrowing down the number of technology suppliers lately rather than offering multiple choices to chipmakers, this is significant.

Cadence updated its product line to include multicore support. That follows the Rambus-Kingston announcement last week of parallel memory. Now if only the application software could take advantage of all those cores we’d be set.

By Ed Sperling

It was a good week for those companies—and countries—with cash.

The Abu Dhabi government’s $5.6 billion bid for Chartered Semiconductor took top billing this week as the deal to watch. The Advanced Technology Investment Company made the bid, but the company is entirely owned by the government. This is the same group that set up a joint venture with AMD to create Globalfoundries.

Synopsys also announced that it would repurchase $500 million in stock, which is what companies do when they want to boost the price of their shares. It’s simple math. The fewer shares, the more they’re worth. IBM has been doing this for years.

Meanwhile, back at the foundries, Cadence announced a broad multi-year technology agreement with Globalfoundries for design, verification and manufacturing. Well, at least we know there’s plenty of money to pay for the tools.

There’s also more money in the works for Magma. The company’s offer to exchange outstanding convertible notes was greeted positively by the majority of bondholders. To paraphrase Mark Twain, news of this company’s death are greatly exaggerated.

So with all this positive activity going on, why did TSMC’s sales drop last month? The top foundry’s numbers show sales in August 2009 were $887 million (U.S.), versus $922 million in August 2008. Sales were down year over year for the first eight months, as well. Aren’t all signs supposed to be pointing to the end of a protracted downturn?

Synopsys introduced DDR3 PHY and digital controller IP with support for the newest 2133 Mbps data rates from JECEC and the anticipated new low-power 1.35 volt standard (compared with the existing 1.5 volts). The company is the first to get there—even ahead of the new standards—but it certainly won’t be the only one.

Also on the IP front, Cypress licensed a broad array of ARM’s intellectual property for its programmable line. Expect to see a lot more in the programmable space in coming months as business concerns begin infiltrating what formerly were technology-only decisions.

By Ed Sperling

Actel introduced the first radiation-tolerant FPGA with embedded radiation-protected mutiply-accumulate blocks for use in outer space. With increased density at each node, the number of single-event upsets increases proportionately due to cosmic radiation. In some cases, these kinds of events can destroy a chip, leading to all sorts of complicated error-correction designs.

Mentor Graphics pushed further into the IP world, rolling out its configurable Precise-IP independent IP platform for FPGA design that links to categorized third-party IP from a variety of vendors including ARC (soon to be part of Virage Logic), ARM, Aeroflex Gaisier, CAST, Eureka, Hellon, IPextreme, Innovative Logic and OptNgn. This is like an instant ecosystem. Just add water.

That comes on the heels of a couple of major product adoptions for Mentor—Catapult C Synthesis by Fujitsu and Veloce Emulation by MIPS. Sounds like business is starting to pick up again.

Speaking of Fujitsu, the company seems to be in technology acquisition mode. ARM licensed its Cortex-M3 processor to Fujitsu for future low-power applications.

Synopsys, meanwhile, was making noise about one of its customers, Ubixum. The company used Galaxy Custom Designer to achieve first silicon for its sensor chip. Coming on the heels of multiple customer wins, this is yet another sign of life in the chip world.

Cadence inked a multi-year deal with GlobalFoundries, the AMD spinoff, to incorporate Cadence technology across the flow from design to manufacturing. Given the source of the money behind this deal, it’s a …well…big deal.

Magma announced it is offering a 6% conversion price for restructuring its debt. This will surely feed into lots of speculation about whether that is high, low, normal, and indicative of the company’s future. We’re staying blissfully neutral on this one.

By Ed Sperling

The general consensus among software developers is that some applications will never be able to take advantage of multiple cores, but that certainly doesn’t mean system designers can’t figure out ways to use more cores.

Nor does it mean that all cores are created equal. The picture that is emerging from multiple chipmakers shows the following trends:

1. More cores have limitations for performance gains of many applications, but they can run multiple applications better simultaneously;
2. Hardware accelerators can be added to some cores to boost performance of applications that are difficult to write in parallel;
3. Advanced process nodes provide more on-chip resources to reducee some of the bottlenecks that existed in early iterations of multicore chips, and
4. Scaling of cores to specific applications or functions can save huge amounts of power and boost overall performance of a system.

One of the most telling signs of what’s changing is evident in IBM’s Power7 architecture, which includes embedded DRAM (EDRAM) on the same chip as the processor cores rather than on a separate chip or somewhere else on the printed circuit board. For the portion of IBM’s customer base that includes datacenters, this is a significant shift in processor design because it speeds up overall performance by dramatically reducing the distance between the core and the memory.

Even without adjusting clock speeds, there are still performance gains by moving more functionality onto the chip and reducing the distance between various components. The speed of electricity and light are limiting factors in a processor, and the more that can be loaded onto a chip the better the performance. Memory is merely the first step. IBM is also looking at moving I/O functions onto the main processor, as well.

Percy Gilbert, vice president of silicon technology for IBM Semiconductor’s R&D center in Fishkill, N.Y., said that the addition of high k/metal gate technology at 32nm provided 2.8 times the performance and a 2x gain in performance in a dual core CPU vs. a single-core chip running at 45nm. He also noted that high k/metal gate will allow mobile processors—including multicore mobile processors—to run at clock speeds of greater than 1GHz.

“High k/metal gate is a game changer,” Gilbert said. “It can reduce gate leakage by more than 100 times and improve performance. We’ve seen a 70% improvement on PMOS (PFET) and a 47% improvement on NMOS (NFET). And by not putting in complex elements, you also increase overall reliability.”

Doing all of those things plus boosting clock speeds provides both energy savings plus performance gains. Intel, for example, has been steadily raising clock speeds since it first introduced multicore designs. In the past couple years, speeds of cores in multicore designs have risen from less than 1GHz to as high as 2.6GHz.

Sidestepping bottlenecks

Nevertheless, each process node brings new tradeoffs in design. When there was only one application using one core at a time, the bottlenecks were manageable—at least within the chip. Running multiple applications on multiple cores, using shared resources on the chip, adds a whole new level of complexity.

“The problem is that you have to increase bandwidth overall,” said Markus Levy, president of EEMBC, an independent benchmarking organization. “If you have two data intensive applications running at the same time, it can choke up the chip. You might have to time slice the application so the data intensive parts aren’t running at the same time. You may have one part that’s data intensive and another part that’s computationally intensive.”

He said the solution may look like load balancing on a chip or a series of distributed chips. Unfortunately, there is no standard for doing that kind of work and no public discussion at the moment about how it should even happen.

At least part of the issue also is that many attempts to solve this problem from a software standpoint involve legacy applications. In a relatively mature market for software, the number of new applications hitting the market and winning major market share is slim.

It’s possible to re-think applications from the ground up, but there needs to be resources applied to them and a clear business case for doing that. In many cases, it means risking market share with uncertain rewards at a time when other alternatives such as dedicated cores and better resource sharing offer significant gains. As with energy-efficient cars, change didn’t come quickly until the price of gas more than tripled and there was a clear business case for making those changes.

By Pallab Chatterjee

The game has changed for processors. The goal now is data throughput, not higher gigahertz and more watts.

That shift dominated the presentations at the Hot Chips conference this week. In previous years, the theme was higher single-core performance, more power and smaller geometries processes. This year it was all about multi-core and multi-power options as the realities of process technologies, economic viability—as well not having higher power density design melt the silicon and package—begin taking hold.

The new server platforms in the enterprise arena are targeting multicore, multithreaded processors with a high-speed multi-chip data bus. AMD’s Opteron processor family, for example, now includes the new “Magny-Cours.” This is a two-die MCM configuration of the 45nm SOI six-core Istanbul processor using the Greyhound architecture. It comes with a 64-bit core with 4x 6.4GT/s Hypertransport interface and a new low-power DDR3 memory interface.

The core architecture of the die (see figure 1) includes a distributed L2 cache for each of the six-core units, a common L3 cache and then a centralized DDR memory controller interface.

Figure 1

The finalized two-die configuration for the MCM (see figure 2) is a new processor optimized for the enterprise by supporting a 2P/4P configuration in a standard rack unit. It can support high speed DRAM access without needing to cache probe the status of the other cores.

Figure 2

Intel highlighted the architecture of the Nehalem-EX enterprise processor. This is a 45nm eight-core processor with four QPI channels and a DDR interface. Similar to the application addressed by the AMD part, the Nehalem-EX is targeted at minimizing latency and maximizing data throughput without raising the clock rate of the part. The die photo (see figure 3) shows the distributed cache by the 8 cores, and a common “uncore” area. The chip is flanked by the QPI and SMI interfaces.

Figure 3

To reduce memory latency there are two DDR3 channels, a ring protocol for the distributed LLC caches, and a scheduler that can support 32 simultaneous requests (see figure 4).

Figure 4

The use of the QPI interface allows high-speed communication between the die and can result in a very high thread and core count server module (see figure 5). This configuration contains eight sockets and four I/O hub support chips.

Figure 5

TI presented an OMAP processor, a multi-media core design that features distributed processing and high-speed memory interfaces. For the multicore processing, it is a large structure with both analog and digital modules. This chip architecture is optimized for standard-function, non-graphic content creation tasks. It features two Cortex A9 cores, two Cortex M3 task processors, and a general purpose 64x-Lite DSP core. To support the processor cores and the multi-media (audio and video), a power management and scheduling function is part of the chip making sure that sections not used are powered down.

Nvidia presented a keynote about the new uses of the GPU as a general-purpose data processing engine. The company presented a high-performance platform and in the later sections, executives presented a minimum configuration engine and a fill PC feature set IC called the ION. The ION is available now as an option for small format embedded PCs and as a companion chip to the Intel Atom Processor. The Ion Processor features both hardware and software power management control. This includes having the software turn on and off aspects of the core block without being tied to a fixed clock time based application. In this scenario, the power conditioning is data-based, rather than based on a fixed task.

Day one continued with additional processor applications and more details on the Intel design, including multicore processor architectures. The common trend on these designs with embedded cache is the focus on switched and gated power for unused blocks.

The highlight for day two of the conference was the introduction of the IBM Power7 processor, a monolothic 45nm SOI eDRAM process design with eight cores and 32 threads per chip. The design features distributed L2 caches with a centralized L3 cache and a common DDR3 interface. Rather than the QPI interface, it has its own instruction pre-fetch interface for high bandwidth communication. The design is targeted at standard single-die applications and quad-chip MCM modules for compute-intensive datacenters. The applications of the hardware are architected to support up to 32 of the chips (8 quad chip MCMs) in a single configuration and memory structure.

All of the processors and chips discussed were showing their low-power characteristics. These included the standard, synthesis-able low-power solutions of multiple synchronous clock paths based on a master, gated power, multimode and power-down feature under software control, and reduced operating voltage on the core vs. I/O. There were no real innovative custom power handling solutions that were put into the architecture, just the widespread use of the known solutions the last few years. The trend appears to be multicore and multi-die data passing as the first goal; after this is figured out, then extensive power handling will be addressed. The GPU as a compute engine is working with a different power/performance curve over the standard multicore engines and its power solutions will end up improving under different solution paths as products move forward.

By Ed Sperling
The decades-old approach of powerful processors with ever-faster clock speeds is changing. Performance matters in some settings, but the real concern is adding more functionality within power budgets.

The most pressing tradeoff is now performance vs. power, which has forced processor architects at AMD, Intel and IBM to take into account everything from application software to the firmware that manages some of the functions on a chip and the middleware that makes it all work together.

“One phenomenon we’re seeing is that a number of customers claim their data centers are full but when we go out to see them they’re only half full of hardware,” said Margaret Lewis, product marketing director at AMD, “They can’t draw any more power in places like the Northeastern United States, California or Germany.”

Part of that is due to virtualization, which has been pushed on data centers in particular as the way to boost utilization of a server. According to McKinsey & Co., datacenter server utilization is as low as 5%, which has made virtualization a natural way to improve efficiency and cut costs. And with many software applications unable to utilize more than a couple cores of a server, it’s sometimes only way to boost utilization of multicore servers.

That is about to change, however. “Most of the software hasn’t made it over to multithreading,” Lewis said. “So instead of just using cores for applications, there are other switches we can turn on processors to do things like balance memory or have better I/O.”

The software also can be tweaked to boost optimization lower down on the stack so that instead of tuning each Java virtual machine running on a separate core they all can be optimized so that every Java applet benefits.

“We are seeing a number of new software models,” Lewis said. “The only thing that keeps everything around is that the legacy software people don’t want to give up what they have. It’s easy to multithread to two to four cores. After that, debugging becomes too difficult. A different approach is multitasking, so you do different tasks on different cores. What’s being done with the CPU and the GPU is the first big example of that.”

Intel, meanwhile, has been working with Microsoft to improve the efficiency of its processors.

“Performance was always the focus, but power savings are now part of the methodology,” said George Alfs, program manager at Intel. “For years we have been working with Microsoft to make sure that the operating system isn’t spinning wildly waiting for the next keystroke. We’re now putting the operating system into a sleep state even between keystrokes. There are seven sleep states and a variety of ways to take advantage of power.”

Part of Intel’s road map also calls for more threading. Windows 7 is expected to offer better scheduling than Vista, allowing more than one application to run at the same time on different cores. It also calls for power flexibility to provide more thermal headroom for either boosting performance or lowering power at 32nm.

Intel also is building basic graphics processing into the processor, which will further utilize some of the cores. How many cores depends on the graphics requirements. The first Larrabee chip, due out next year, has a discrete graphics card for ray tracing, but there is certainly a possibility that Intel could integrate some of those graphics into its processors.

Intel also will be using a combination of homogeneous and heterogeneous cores, Alfs said, which is a different direction than the company said it would take several years ago. Some of those cores could be for I/O and graphics, Alfs said, similar to the approach taken by AMD. Intel also plans to use some cores for encryption/decryption, which has been a drag on system performance in the past.

It was a good week for team approaches and an overall brighter outlook for the industry.

Synopsys teamed up with ARM to boost efficiency for ARM’s AMBA 3 interconnect, configuring the interconnect to eliminate unnecessary logic. That ripples down into better performance, lower power and less routing on an SoC. So now what do you do with all that space you’ve just opened up? See below.

Speaking of team approaches, TSMC and Cadence teamed up to provide a 65nm mixed signal/RF reference design kit focusing on behavioral models and a reference flow. Included in the release is a phase-locked loop noise-sensitive reference design. This is the most recent in what is expected to be a flood of tools aimed at the analog and mixed signal market, something that will become critical in SoCs that incorporate more and more functions to soak up all that extra space each process node provides. While the digital engineers will likely use whatever comes their way, the analog engineers are a lot pickier about these things. A big plus is that the reference design kit will help with mixed signal verification, which is where the real time savings are needed.

The auto industry may be down, but that doesn’t mean you don’t make tools to improve its efficiency. Mentor Graphics rolled out an integrated design environment for the Automotive Open System Architecture (AUTOSAR) system that uses standard interfaces and components dictated by AUTOSAR. Anything that helps Detroit regain its footing is good for the entire industry, given the number of electronics components that are finding their way into cars these days.

ARM unveiled physical IP for TSMC’s 40nm G process, balancing performance with lower power. The target markets are consumer devices like set-top boxes, disk drives, mobile computing devices, HDTV and graphics processors. Included is a power management kit and ECO kit library extensions for addressing current leakage by replacing or complementing the HVt, RVt or LVt implant layers with long channel-length devices.

Handset sales are stabilizing. TriQuint Semiconductor posted 7% gains in total revenues in the first quarter of 2009 compared to the same period in 2008, including a 24% growth in handsets. Given the fact that no one likes to be locked into a contract for more than two years, and the ongoing recession has been under way for 16 months, it’s getting to be that time for many people.

Computer sales revived in the past quarter. Intel posted Q1 revenue of $7.1 billion, along with a statement from CEO Paul Otellini that the industry is “returning to normal seasonal patterns.” There’s only so long you can keep an old laptop computer or server blade going before it starts costing you big bucks in productivity loss. The big question is whether the replacement is a new computer or a netbook or smart phone—or whether it’s some combination of those.

AMD reported revenue of $1.8 billion during Q1, which was flat compared to the fourth quarter of 2008. While it was down 21 percent from Q1 of 2008, it’s not exactly an apples-to-apples comparison because AMD no longer has an in-house fab. Still, it was better than anyone expected, even with an operating loss of $308 million. 

And finally, the whole market continued its drive upward. Both the Dow and the Nasdaq have been posting gains for weeks. While it’s too early to tell if this upward trend will stick, the market usually runs 6 to 12 months ahead of the overall economy, depending upon who you listen to. At the very least, it’s a signal for the foundries to begin starting up their machinery again and for companies to begin developing products for next holiday season.

–Ed Sperling