By Ed Sperling
Mentor’s Colin Walls examines the use of signatures in embedded software—code sequences that cannot occur randomly. This is like turning prime numbers—ones and zeroes—into prime sequences.

Cadence’s Tom Anderson looks at assertions in everyday life, touching on everything from bookstores to Alfred Hitchcock to Chicken Kiev. This is alternatively known as work-life balance.

Synopsys’ Allen Watson questions whether proprietary RTOSes can survive. It’s a good question, and one that deserves some serious thought—by the companies that still write them as well as the designers who use them.

DeepChip’s John Cooley looks at the possible outcomes of the Icahn incursion into Mentor’s board. (In case you were trapped in an elevator shaft, three of Icahn’s candidates were elected to Mentor’s board last week.) Our guess is things will get loud, but not much will change.

Mentor’s Harry Foster pitches in with part eight of his verification study, the part focused on design and verification language trends. Foster has become the Tolstoy of verification.

Cadence’s Richard Goering reports on a panel about hardware-software co-design and co-verification—what’s real, what’s missing and what are the barriers to adoption.

Semico’s Morry Marshall and Michell Prunty take different views on whether Apple’s strategy is the same Mac OS disaster it waged against Microsoft or whether the company is really driving a new and different vision. Time will tell.

Analog Devices’ Ashok Chandran, writing in Synopsys’ VMM Central, provides some deep technology tips about pipelined RAL access. If you work with this stuff, this is good info.

DAC season is upon us. (Rabbit season. DAC season. Slap.) Mentor’s Dennis Brophy details all the standards updates that will occur at the conference, ranging from UVM to SystemC.

Cadence’s Suni Gokhale offers up some tips on how to control power switch rush current. This is important information for advanced SoC designs, where power is now the 800-pound gorilla.

And in case you missed the most recent Low-Power Engineering newsletter, here are some standout blogs:

– Mentor’s Barry Pangrle looks at Intel’s new machine, complete with FinFETs well ahead of schedule.

– Synopsys’s Cary Chin takes a look at the Intel FinFETs, as well, but from the standpoint of a confusing press release and press reports.

– Cadence’s Luke Lang examines the real value of a low-power methodology—and what exactly a methodology is. This is something every designer needs to know.

– And Apache’s Matt Elmore takes an incisive look at the top five reasons for power delivery failure. This is a superb bit of reporting.

By Ellen Konieczny

As active devices and interconnect wires shrink and are placed closer together with the march of Moore’s Law, signal integrity is becoming a huge concern. If it is not maintained, a design’s future may be marred by lower yields, unreliable performance, and failure to work efficiently—if at all.

For low-power and radio-frequency (RF) designs, which are being produced at a steady climb, this challenge is even more daunting. Such designs involve numerous aspects that make it more difficult to ensure signal integrity. Due to their very nature, RF designs also face more severe consequences if signal-integrity rears its head in the form of problems like interference and noise.

Among the design aspects that threaten low-power designs, for example, are multiple power operating modes, multiple voltage supplies, voltage and frequency scaling, and voltage islands. As noted by Shekhar Kapoor, Synopsys’ senior product marketing manager for the Galaxy Signoff Solution, “The use of low-power techniques, such as power islands and on-off switching behavior, can exacerbate signal-integrity issues. The potential issues to worry about include dynamic voltage drop, power-grid electromigration, and electromagnetic-interference (EMI) noise. All these effects could worsen if care is not taken to manage the in-rush current in turning on power switches, for example.”

To overcome this challenge, Kapoor recommends a holistic approach to handling signal integrity that has in-design and signoff analysis working together. To mitigate the signal and power-grid integrity issues, place-and-route tools must provide various optimization and fixing techniques. Examples include wire-width adjustments, multiple via insertions, and buffering. In addition, the signoff parasitic extraction and timing/signal-integrity solutions must offer detailed debug and fixing to address any undetected problems before tapeout. At smaller nodes—especially below 40-nm process technologies—the parasitics have become context-specific (i.e., layout-dependent). To ensure silicon accuracy, the extraction tools must model the context-specific device parasitics as part of the extraction process. They can then account for the amplified effects of the MOS device parasitics at smaller nodes.

Beyond a winning approach, the key to successful low-power design is really a mindset. The techniques used to achieve low-power design introduce a high level of complexity at the levels of system design, functional verification, IC physical design, and IC testing. To achieve success, it is therefore essential that the designer keep the low-power aspect in mind beginning with the earliest stages of design. According to Michael Buehler-Garcia, director of marketing at Mentor Graphics’ Design to Silicon Division, “Engineers need ways to evaluate different architectural approaches to power reduction early in the design process, at the system level. They also need to verify functionality in detail, ensuring that transitions between power modes do not create logical errors and that state retention is handled correctly when parts of a chip are temporarily powered down.”

RF Design Poses Further Hazards
The RF aspect of a design adds a much more complex set of challenges, as it is essential that the integrity of the communication path be maintained. Among the chief concerns are electromagnetic (EM) degradation and EM-interference (EMI) noise. Dave Robertson, vice president of analog technology for Analog Devices, says his company sees the maintenance of signal integrity being comprised of two elements: Amplifying, processing, and transmitting the signal with minimal degradation due to distortion or device noise, and minimizing the effects of induced external signals from crosstalk, power-supply noise, or other external interference

The simplicity with which those two goals can be stated belies their complexity—especially considering the short time to market for RF products. This issue is compounded by the fact that signal integrity traditionally has been a concern in the digital-circuit rather than the RF domain. Thankfully, as signal-integrity issues began to rear their heads in high-speed communications designs, software developers have pruned signal-integrity analysis environments to address both device and circuit models. With today’s shrinking ICs interacting more with both active neighboring devices and interconnects, it is crucial that such interactions are modeled accurately.

During analog design, custom IC layout and simulation tools are used to accurately model the behavior of an RF or other analog circuit. The designer can therefore determine if signal integrity will be compromised by interactions within the cell itself. Yet Mentor’s Buehler-Garcia notes the designer also must avoid signal-integrity problems when the RF cell is placed within the context of a full mixed-signal IC, which may interact with other circuits including digital signals.

Once active and passive device models have explored all of the high-frequency effects, signal integrity may be ensured by using a comprehensive set of analysis engines that leverage that modeling capability. According to Ted Mido, senior staff engineer for Synopsys’ circuit simulation product line, designers must be sure to exercise both of these options. He notes that most designers rely on time-domain analysis for final behavioral verification. Therefore, the baseline would be to have high-performance, high-capacity transient and transient noise analyses.

In the early design phase, Mido notes that system or subsystem behaviors may be predicted by using small-signal frequency-domain analysis to predict system S-parameters, small-signal noise parameters, transfer functions, and so on at a particular operating point. In addition, a statistical eye-diagram simulation can predict deterministic channel noises like inter-symbol interference, duty cycle distortion, and periodic noise. Finally, large-signal steady state analysis may be used to predict nonlinear and modulation effects. Of course, these analysis engines must be able to accurately accommodate all of the high-frequency effects originally modeled.

Although electronic-design-automation (EDA) tools are clearly working to ensure signal integrity in RF designs, a lot may be gained in the hardware design as well. As ADI’s Robertson notes, “There are CAD tools for capturing and analyzing parasitic resistance and capacitances, but it can be difficult to come up with models of sufficient accuracy, and for large chips it is generally impractical to exhaustively capture and simulate these parasitics. Different circuit topologies and architectures may make the problem much better or much worse, so circuit innovation can often relieve what was perceived as a ‘hard physical constraint.’”

Beyond Moore’s Law, ADI recognizes a number of challenges spawned by the functional density involved in mixed-signal and RF integration. Although active power density is a fundamental challenge, some relief may be found in advanced packaging solutions. Similarly, powering down idle blocks offers advantages when dealing with inactive power density from leakage currents in very deep-submicron CMOS. It should be noted that this benefit does come at the cost of more sophisticated power management circuits and systems.

In terms of current density, the fine metal pitch and increasing functional densities can cause electromigration and IR drop problems in the on-chip interconnect. The process solution is to use copper and thick copper interconnect. Yet bump and flip-chip packaging can provide a 2D bonding approach so these currents do not need to be routed all the way across the chip. Such approaches also reduce the inductance of these connections.

The signal-integrity puzzle will only grow more complex as designs continue to shrink while consuming less power and incorporating more wireless capability. Going forward, for example, it is critical for designers to realize that signal integrity will need to be considered between chips as well as on chips. Mido states, “The massive integration of cores on vertically stacked chips (3D ICs) that don’t necessarily feature the latest transistor technology node is becoming common. Therefore, high-speed communication between cores/chips is becoming important. With the increasing operational frequencies of these digital communication bus/links, bit-error-rate (BER) prediction is also becoming important (See Figure 1).”

Figure 1: For accurate bit-error rate predictions in high-speed digital communications, it is critical to account for aspects like high-frequency loss mechanisms, millions of possible bit patterns, special techniques for equalizing digital signal shape both in transmitter and receiver side, and multiple noise mechanisms.

By Ed Sperling

Technology convergence and market consolidation have always gone hand in hand, although not necessarily in ways everyone expects.

The confluence of video and audio was first exhibited by AT&T at the 1964 World’s Fair. The rather crude videophone demonstration promised a future where people could actually see the person they were talking with. Fast forward 45 years and AT&T provides the backbone cabling infrastructure for some of that technology, but the technology has progressed far beyond anything that AT&T could have predicted at the time. And perhaps more important, AT&T no longer has the monopoly on communication.

Much has changed since then. When AT&T introduced the videophone concept, companies such as Cisco didn’t even exist to exploit the capabilities of high-definition multi-way videoconferencing. The founders of Skype—Niklas Zennstrom and Janus Friis—weren’t even born.

But what became painfully obvious to many companies is that the founders of the market weren’t necessarily the long-term beneficiaries. In the consumer space, Apple is the modern-day example. It didn’t create MP3 players, but it did win the lion’s share of the market by setting up a system of micropayments for music—an economic model that that first came into widespread use in public transportation. It also didn’t create the smart phone, but the iPhone has emerged as the one of the most popular.

At the component level, much of this convergence has been enabled by Moore’s Law and the increasing amount of real estate on a piece of silicon when everything is shrunk at each new process node. The fact that a single chip can now contain everything from a cell phone to an MP3 player and GPS system, and still work within a strict power budget to extend battery life would have been considered science fiction a couple decades ago, and highly improbable at the start of this decade. But, then again, so would being able to see and count the atoms of insulation between the wires on a chip.

Blurred lines

The ability to cram more functionality onto a single piece of silicon is now changing our perception of what exactly a chip should be is called. While it was pretty obvious that multicore chips would share the same bus and memory—basically a mini array of processors that could be used by applications that could either run in parallel or be virtualized—it becomes much harder to define when those cores are doing completely different functions and may or may not use the same memory.

Intel and ARM are both targeting the same market using a variety of strategies ranging from 32-bit microcontrollers on ARM’s side to Intel’s scaled down Atom processor. The differences between the two of them is becoming harder to discern, however. The previous definition of a microcontroller was that it had memory on the same chip, while for processors it was external. That definition no longer applies, particularly with systems on chip. In fact, one chip can contain multiple 32-bit microcontrollers, said Dominic Pajak, product manager for ARM’s new M0 microcontroller. He noted that a 32-bit microcontroller actually uses less power than an 8-bit microcontroller doing multiple functions because it involves fewer duty cycles.

“This works exceptionally well in Zigbee applications where you have remote sensors such as utility meters, tire pressure sensors, voltage monitors, as well as in smart phones, cameras, and a whole range of consumer goods,” Pajak said. “There’s even an integrated interrupt controller so you can write routines in C and you don’t have to write assembly code. That makes time to market much faster. And in the design you can have multiple power domains so you can power down a part of the chip.”

Intel’s argument is roughly the same, although its approach is to leverage the Intel Architecture and the code—or at least the coding process—with which many software developers are very familiar. Jonathan Luse, director of marketing for the low-power embedded products division of Intel, said Intel has targeted a variety of new markets now dominated by 32-bit microcontrollers.

So far Intel’s biggest challenge has been in the power budget. The Atom processor runs at about 2 watts, compared with some microcontrollers that supposedly run at a fraction of that number. But the real numbers are a bit fuzzier. A single-lane PCI express, for example, can add 0.5 watts to the number.

“There’s a whole space below where we are today that we have targeted,” said Luse. “That includes billions of units. Some of that is a space that would be relevant to the Intel Architecture. There are also other markets where it’s largely silicon by the pound. That’s not so interesting.”

He noted that at 2 watts, there is room to drive out some power. But he also noted that stripping out power isn’t as clean as it looks, because sometimes removing power at the processor level causes penalties at the board level.

New opportunities

For system-level design this opens up far greater opportunities, however, to play across a variety of markets that were largely off limits to many chip makers. Virtually all the major chip companies now have a presence in the 32-bit microcontroller space, whether it’s with microcontrollers, low-power FPGAs like Actel’s new 65nm platform, or Intel’s Atom processor.

There also is an opportunity to use technology differently. Smart grids, for example, have opened new markets for both 2.4GHz and 900MHz communications. Mark Strzegowski, senior product manager for Analog Devices’ metering group, said the 900MHz technology using Zigbee and powerline works better in multi-unit apartments because the reinforcing bars (rebar) used in the construction of commercial buildings interferes with 2.4GHz wireless signals.

Opportunities also have opened up in adding intelligence into meters, where both Analog Devices and Cypress Semiconductor have created solutions that merge discrete logic and communication with existing technology. Those opportunities will continue as convergence—or at least mashups of technology—continue on a grand scale. What is less obvious is how quickly those collisions will happen, in what markets, and what will be displaced by those changes.