By John Blyler
System-Level Design (SLD) sat down to discuss trends in analog and RF integrated circuit design with Ravi Subramanian, president and CEO of Berkeley Design Automation, (at the recent GlobalPress eSummit) and later with Trent McConaghy, Solido’s CTO. What follows are excerpts of those talks.

SLD: What are the important trends in analog and RF simulation?
Subramanian: I see two big trends. One is related to physics, namely, the need to bring in physical effects early in the design process. The second trend relates to the increased importance of statistics in doing design work. Expertise in statistics is becoming a must. One of the strongest demands made on our company is to help teach engineers how to do statistical analysis. What is required is an appreciation of the Design-of-Experiments (DOE) approach—common in the manufacturing world. Design engineers need to understand what simulations are needed for analog versus digital designers. For example, in a typical pre-layout simulation, you may want to characterize a block with very high confidence. Further, you may also want to do that block extracted in post layout with very high confidence. But what does ‘high confidence’ mean? How do you know when you have enough confidence? If you have a normally distributed Gaussian variable, you may have to run 500 simulations to get a 95% probability of confidence in that result. Every simulation waveform and data point has a confidence band associated with it.
McConaghy: As always, there is always a pull from customers for simulators that are faster and better. In general, simulators have been delivering on this. Simulators are getting faster, both in simulation time for larger circuits, and by easier-to-use multi-core and multi-machine implementations. Simulators are also getting better. They converge on a broader range of circuits, handle larger circuits, and more cleanly support mixed-signal circuits.
There’s another trend: meta-simulation. This term describes tools that feel like using simulators from the perspective of the designer. Just like simulators, meta-simulators input netlists, and output scalar or vector measures. However, meta-simulators actually call circuit simulators in the loop. Meta-simulators are used for fast PVT analysis, fast high-sigma statistical analysis, intelligent Monte Carlo analysis and sensitivity analysis. They bring the value of simulation to a “meta” (higher) level. I believe we’ll see a lot more meta-simulation, as the simulators themselves get faster and the need for higher-level analysis grows.

SLD: This sounds a lot like the Six Sigma methodology, a manufacturing technique use to find and remove defects from high volume productions—like CMOS wafers. Will design engineers really be able to incorporate this statistical approach into their design simulations?
Subramanian: Tools can help engineers incorporate statistic methods into their works. But let’s talk about the need for high sigma values. To achieve high sigma, you need a good experiment and a very accurate simulator. If you have a good experiment but you want to run it quickly and give up accuracy, you may have a Six-Sigma setup, but a simulator that has been relaxed so the Six-Sigma data is meaningless. This shows the difference between accuracy and precision. You can have a very precise answer but it isn’t accurate.
To summarize: Today’s low-node processes have associated physical effects that only can be handled by statistical methods. These two trends mean that new types of simulation must be run. Engineers need to give more thought as to which corners should be covered in their design simulations. Semiconductor chip foundries provided corners that are slow, fast and typical, based upon the rise- and fall-times of flip-flops. How relevant is that for a voltage-controlled oscillator (VCO)? In fact, are there more analog specific corners? Yes, there are.

SLD: Statistical analysis, design-of-experiments, and corner modes—designers already hear many of these terms from the yield experts in the foundries. Should they now expect to hear it from the analog and RF simulator communities?
Subramanian: Designers must understand or have tools that help them deal with statistical processes. For example, how do you know if a VCO will yield well? It must have a frequency and voltage characteristics that are reliable over a range of conditions. But if you only test it over common digital corners, you may miss some important analog corners where the VCO performs poorly. A corner is simply a performance metric, such as output frequency. You want to measure it within a particular confidence level, which is where statistics are needed. It may turn out that, in addition to the digital corners you’ll need to include a few analog ones.
McConaghy: These terms imply the need to address variation, and designers do need to make sure that variation doesn’t kill their design. Variation causes engineers to overdesign, wasting circuit performance, power and area or under design, hitting yield failures. To take full advantage of a process node, designers need tools that allow them to achieve optimal performance and yield. Since variation is a big issue, it won’t be surprising if simulator companies start using these terms with designers. The best EDA tools handle variation, while allowing the engineer to efficiently focus on designing with familiar flows like corner-based design and familiar analyses like PVT and Monte Carlo. But now the corners must be truly accurate, i.e., PVT corners must cause the actual worst-case behavior, and Monte Carlo corners must bound circuit (not device) performances like “gain” at the three-sigma level or even six-sigma level. These PVT and Monte Carlo analyses must be extremely fast, handling thousands of PVT corners, or billions of Monte Carlo samples.

SLD: Would a typical digital corner be a transistor’s switching speed?
Subramanian: Yes. Foundries parameterized transistors to be slow, typical and fast in terms of performance. The actual transistor model parameters will vary around those three cases, e.g., a very fast transistor will have a fast rise and switching time. So far, the whole notion of corners has been driven by the digital guys. That is natural. But now, analog shows up at the party at the same time as digital, especially at 28nm geometries.
The minimal requirement today is that all designs must pass the digital corners. But for the analog circuits to yield, they must pass the digital and specific analog corners, i.e., they must also pass the condition and variations relevant to the performance of that analog device. How do you find out what those other corners are? Most designers don’t have time to run a billion simulations. That is why people need to start doing distribution analysis for analog corners like frequency, gain, signal-to-noise ratios, jitter, power supply rejection ratio, etc. For each of these analog circuit measurements, a distribution curve is created from which Six-Sigma data can be obtained. Will it always be a Gaussian curve? Perhaps not.

SLD: How will this increase in statistical distribution analysis affect traditional analog electronic circuit simulators like Spice?
Subramanian: Spice needs to start generating these statistically-based distribution curves. I think we are at the early days of that frontier where you can literally see yourself having a design cockpit where you can make statistics simple to use. You have to make it simple to use otherwise it won’t happen. I think that is the responsibility of the EDA industry.
McConaghy: The traditional simulators will be used more than ever, as the meta-simulators call upon them to do fast and efficient PVT and statistical variation analysis up to 6-sigma design. The meta-simulators incorporate intelligent sampling algorithms to cut down the number of simulations required compared to brute force analysis. Today, many customers use hundreds of traditional SPICE simulator licenses to do these variation analysis tasks. However, they would like to be able to get the accuracy of billions of Monte Carlo samples in only thousands of actual simulations. These analyses are being done on traditional analog/RF, mixed-signal designs as well as memory, standard cell library and other custom digital design.

SLD: I know that the several of the major EDA tool vendors have recently released tools to make the statistical nature of low process node yields more accessible and useable by digital chip designers. Are their similar tools for the world of analog mixed signal design?
Subramanian: Analog and RF designs are now going through this same process, to move from an art to a science. That’s why I say that the nanometer mixed-signal era is here (see figure). Simulation tools are needed, but so are analysis capabilities. This is why our simulation tools have become platforms for analysis. We support the major EDA simulators but add an analysis cockpit for designers.

Figure 1: Mixed-Signal and RF designs are now part of the nanometer SoC design process.

SLD: Why now? What is unique about the leading-edge 28nm process geometries? I’d have expected similar problem at a higher node, e.g., 65nm. Is it a yield issue?
Subramanian: Exactly. At 65nm, designers were still able to margin their designs sufficiently. But now the cost of the margin becomes more significant because you either pay for it with area or with power, which is really current. At 28nm, with SerDdes (high frequency and high performance) and tighter power budgets, the cost of the margin becomes too high. If you don’t do power-collapsing, then you won’t meet the power targets.

SLD: Is memory management becoming a bigger market for simulation?
Subramanian: Traditionally, memory has had some traditional analog pieces like charge pumps, sensitivity chains, etc. Now, in order to achieve higher and higher memory density, vendors are going to multi-level cells. This allows storage of 2, 4 or 8 bits on a single cell. But to achieve this density you need better voltage resolution between the different bit levels, which means you need more accurate simulation to measure the impact of noise. Noise can appear as a bit error when you have tighter voltage margins. You might wonder if this is really a significant problem. Consider Apple’s purchase of Anobit, a company that corrected those types of errors. If you can design better memory, then you can mitigate the need for error correction hardware and software. But to do that, you need more accurate analog simulation of memory. You cannot use a digital fast Spice tool, which uses a transistor table look-up model. Instead, you must use a transistor BSIM (Berkeley Short-channel IGFET Model) model.

EDA revenue increased nearly 18% in Q2, rising to $1.44 billion compared with $1.22 billion in the same period in 2010, according to the latest EDA Consortium numbers. Revenue was down 0.6% sequentially from Q1.

All geographies were up, year over year, with double-digit growth in the Americas, Japan, and Asia/Pacific. In addition, EDA employment was up about 3% year over year, and 1% sequentially. In the Americas, revenue was up 21% year over year; 18% each in Japan and Asia/Pacific, and 9% in Europe, the Middle East and Africa.

By category, CAE grew about 20%; IC physical design and verification grew 6%; PCBs and MCMs grew 22%; intellectual property grew 23%, and services revenue increased 20%.

EDA companies weren’t the only ones showing optimism. Semico Research issued its forecast that analog within the computing consumer and communications markets will grow 14%, 9% and 13% in 2011, 2012 and 2013 respectively.

Semico anticipates the market for analog will reach $61.9 billion in 2015. What’s particularly interesting is the consumer market will only account for about 23% of that number in four years; it currently represents 33% of the total analog pie.

One-On-One with IDT CEO Ted Tewskbury: How IDT is bridging the analog and digital engineering worlds with a mixed-signal team approach.

By John E. Blyler
The huge RF radio observatory at Arecibo, Puerto Rico has all of the key ingredients for a high-tech adventure movie. First, its location is remote, as it’s buried deep within the rainforest of a Caribbean island. Second, the sheer size of the radio telescope renders it sublime. It measures 305 m (1001 ft.) in diameter and more than 500 m from the jungle floor to the top of the moveable radio feed platform (see Figure 1). Unlike other astronomic R&D facilities in the United States, the observatory at Arecibo also is more than just a radio telescope. It also is a complete R&D facility. Its mission – in part – is to search for the stuff of science fiction stories ranging from extraterrestrials and gravity waves to asteroids that could devastate the Earth.

We will return to the cool sci-fi aspects of Arecibo later. For now, let’s explore the technology that makes all of this possible—starting with an overview of the RF telescope and the critical electronics. Radio astronomy studies celestial objects using radio transmissions. Often traveling great distances, these radio waves are reflected from the objects of study. The returning signal is analyzed and developed into amazing images. Although this may seem like a straightforward task, the returning signal is typically so weak as to be almost indiscernible from the cosmic noise.

Thus, the successful detection of the returning signal requires the very best that modern electronics has to offer. Indeed, the noise generated by even the most modern low-noise amplifier (LNA) and other sources are orders of magnitude greater than the signals being examined. Dana Whitlow, research technician at Arecibo, estimates that the return signals may be over 40 dB below the overall system noise level—a factor of 10,000 lower!

Critical Sensitivity To Noise
Simply put, everything that can be done is done to maximize the sensitivity of the receivers. The front-end electronics are cytogenetically cooled in 99.99% pure Helium to between 10 and 15 Kelvin. These temperatures can only be achieved in a vacuum. As a result, all of the specially designed electronic systems must be evacuated before the cooling can begin.

The front-end electronic systems consist of amplifiers, filters, and mixers. The amplifiers are specifically designed to minimize noise. Toward that end, Ganesan Rajagopalan, a senior receiver engineer and head of the Electronics Deptartment at the observatory, has been improving the sensitivity of the receivers by slowly replacing the existing gallium-arsenide (GaAs) monolithic microwave integrated circuits (MMICs) with indium-phosphide (InP). MMICs are devices that operate at microwave frequencies between 300 MHz and 300 GHz.

InP-based amplifiers have lower noise and higher gain than their GaAs counterparts. Yet these circuits also must be customized for the lowest noise possible. The Cornell University-based team at Arecibo collaborated with the experts at CalTech’s JPL team to make these customized application-specific integrated circuits (ASICs) tailored to a cryogenic environment. The CalTech design also has been implemented at the Allen Telescope Array (ATA) in California. ATA is a “large number of small dishes” (LNSD) array that’s designed to be highly effective for simultaneous surveys of conventional radio-astronomy projects and Search for Extraterrestrial Intelligence (SETI) observations at centimeter wavelengths.

With such innovative LNA devices, it’s no wonder that the Arecibo Observatory is considered state of the art in receiver technology. In terms of the available bandwidth per receiver, however, the facility is playing catch-up. The receivers used at Arecibo are 2 GHz wide, ranging from 2 to 4 GHz and another from 4 to 8 GHz. The goal is to widen the current 2-GHz signals, which are being received using Ultra Wideband (UWB) technology. Here too, the R&D team is working with other scientists and engineers around the globe to develop a UWB feed that will operate from 1 to 10 GHz. Such a feed would reduce the number of existing receivers from 8 down to 1, which would further reduce the collective number of noise generators in the system.

A Noisy Planet
Reducing the noise sensitivity of the receiving electronics is critical to analyzing the radio signals returning from deep space. But another challenge exists closer to home— namely, the effective “noise” created by wireless devices ranging from cell phones to data devices. The RF telescope operates to 10 GHz and includes receivers in the S-, C-, and X-bands. Wi-Fi technology occupies a relatively small bandwidth centered around 2.4 GHz—right in the middle of the lower S-band space. Another source of radio interference comes from a much more powerful source—namely, the various airports on the island. These sources are mission critical and cannot be turned off at select times during the day.

To help reduce the opportunities for radio noise interference, the Arecibo team actively works with the Puerto Rico Spectrum users’ group. In cases involving mission-critical systems like airport radar, the team has coordinated the on-off time of the radar. The airport radar goes blank for a short period of time when it points in the direction of the Arecibo observatory. Unfortunately, this well-intentioned gesture has proven to be of limited value. The radar signal has more power located in the back lobes of the radar signature than in the front lobes.

Sci-Fi Becomes Reality
As fascinating as the engineering work at Arecibo is, does it really have any practical value? Can it turn science fiction into science fact? Some would suggest that the jungle-hidden facility will play an important role in saving humanity from near-earth objects (NEOs) like asteroids, which may be on a collision course with earth. The RF Observatory has the capability to pinpoint the orbit of NEOs as far away as Jupiter or Saturn and then calculate whether that object poses a threat to humanity. Such knowledge could be used to evacuate populations and move important property to a safe location. This is just one reason why the U.S. Congress is interested in keeping the Arecibo radar telescope working.

“We are also doing a lot of work on pulsars,” explains Rajagopalan. “Pulsar timing is very important in the detection of gravitational wave radiation.” Described as a fluctuation in the curvature of spacetime, which propagates as a wave, gravitational waves were predicted by Albert Einstein’s theory of general relativity. Sources of gravitational waves include binary star systems (e.g., white dwarfs, neutron stars, or black holes).

Pulsar astronomers believe that they can detect gravitational waves. Telescopes at Arecibo, PR and the mainland US, Europe, and Australia are all part of an array that’s being used to carefully time pulsars. All of these facilities make very long, simultaneous observations of the same deep-space source using long baselined interferometry (LBI). Precise synchronization timing among the global facilities is achieved using a hydrogen maser atomic clock. Thus, the research being done here is not just astronomy. It’s planetary radar science and ionospheric as well.

Signal Processing
What happens to the signal returning from the reflection off of nearby planets or from signals originating from a deep-space pulsar? The signal comes into the feed in a concentrated form after reflection from the big reflector (see Figure 3). An ortho-mode transducer (OMT) —some more than 3-ft. long—splits the signal into two separate channels. Noise-injection couplers are connected to one channel. These couplers inject a weak but carefully calibrated noise source into the main signal.

Figure 3: Antenna feed and electronics on platform suspended 500 ft above the main reflector dish floor.

The injected noise signal is switched on and off at a rapid rate that’s called a “winking” rate calibration, says Dana Whitlow, a senior receiver engineer. “By a measurement of the levels later in the system with the cal on and the cal off, we can determine the system noise temperature. Also, this calibration allows us to track unique time-dependent changes and gain of the amplifiers.”

The signal then travels through isolators, which flatten out the frequency response. Effectively, they remove reflections from the amplifiers back into the earlier part of the signal path. Finally, the signal is amplified in the LNAs mentioned earlier.

All of these electronics are contained with a dewar, which is used to cool the amplifiers down to 15 Kelvin. Cables connect the dewar to the next signal-conditioning module, which contains a pulse amplifier module to provide additional amplification. Computer-selectable filters are used to exclude unwanted frequency bands, limiting the bandwidth from radio-interference sources like Wi-Fi and airport radar.

What happens if the ionospheric, planetary, or deep-space phenomena that a researcher is trying to study occur at the same frequency as the radio-interference sources—perhaps centered at 2.4 GHz (same as Wi-Fi)? To study these signals, researchers would have to go to one of the other RF telescope facilities on the mainland United States. For example, the Robert C. Byrd Green Bank Telescope in West Virginia operates in a radio quiet zone.

Aside from rejecting unwanted interference signals, filters also help to prevent the interference from compressing the gain of the subsequent signal chain. If it’s strong enough, an interfering signal could drive an amplifier into saturation. This forces the gain to go down, says Whitlow. “If there’s anything that radio astronomers hate, it’s unexpected gain changes in their signal path. It’s difficult, if not impossible, to deal with from a perspective of obtaining calibrated data of their signal or source they are looking at.” After more filtering and amplification, just to increase the signal strength, the signal is then downconverted to a lower, intermediate frequency.

One might wonder if all of these filters don’t attenuate the signal even further—especially because they are passive filters, which contain no power source to help boost the signal strength. While it’s true that passive filters attenuate the signal slightly, these attenuations can be corrected by the numerous amplifiers. Active filters would have their own problems, such as the introduction of extra noise and distortion.

Finally, the conditioned signal is sent down from the receiver platform to the control-room area some 500 m below using analog optical fiber cable. Fiber-optic cable is used because it has a much broader frequency response. Plus, it doesn’t pick up electrical noise due to the imperfect shielding of coaxial cable. Fiber cables are typically much less lossy than coaxial—especially at the higher frequency ends.

Perhaps the most compelling reason for fiber over coaxial cable is that the former doesn’t conduct lightning down to the control room, explains Whitlow. “I haven’t been down here to see this firsthand, but I’ve been told by many people that in the early days of the observatory, when lightning struck the platform, there would be sparks jumping around things inside the control room.”

Coming in Part II: We’ll delve into the technology used in the control room and laboratory, where the data is digitized and analysis is performed. Of particular interest to chip and embedded designers will be the evolution taking place from ASIC- to FPGA-based systems.

By John Blyler

A just completed EDA tools and technology survey of 140 engineers conducted over the past several weeks shows a strong push into full-custom devices and FPGAs. In fact, 32% of the ICs being designed by engineers using EDA tools were building full custom devices, and another 24% were building FPGAs. Only 9% were working on ASICs, although the ASICs tend to be large and extremely complex chips.

About 14% were designing analog arrays and another 11% were using gate arrays. Another 10% were building ASSPs.

By Ed Sperling

For decades, analog and digital engineers have lived in completely separate worlds. The lines are blurring between those worlds, though, in complex SoCs. So far, the transition has been difficult, and most engineers predict it will get worse at future process nodes.

The basic problem is that each world has functioned independently of the other from the start. They use different tools, they work on different schedules and they generally think about problems from a different vantage point. There are some very good reasons for this. In the digital realm, designs typically last only a year or two. In pure analog, they can last a decade, with a major emphasis on having a specification that’s performance tuned to be just a notch better than the competition.

“These have been two very distinct markets,” said Ed Lechner, director of product marketing for custom design at Synopsys. “One is for standard analog parts, which is the world of Linear, Analog Devices and Fairchild. Their most popular node is 180nm and they tune for maximum performance. At the other end of the spectrum are the digital engineers who are working at 32nm and 45nm. They’re willing to forgo getting maximum performance for a quick and dirty solution so they can get the product out the door in time for the Christmas season.”

But pushing down to the leading edge of Moore’s Law also has opened up an enormous amount of real estate. That creates the opportunity to shrink a bill of materials, and therefore the cost, by combining functions that formerly were on multiple chips into a single chip. This is where analog meets digital, and the relationship—uneasy at a distance—is becoming even rockier when both functions are being forced to work in sync on the same development schedule.

Linda Fosler, marketing director in Mentor Graphics’ deep submicron division, just returned from a European tour where she met with 10 of Mentor’s top customers there. She said those companies want to be able to design mixed signal chips in the same time frame as digital chips and without having to boost the number of engineers to get the job done on schedule.

“One problem we’ve heard is that respins have made companies late to market, which is very costly to them,” Fosler said. “The problem is that the interface between the analog and digital blocks is not tested until the last minute because these teams aren’t working together. The industry needs to address implementation effects—basically the parasitics—of what affects the final qualification of silicon. It must be dealt with iteratively at the layout and schematic level, and built into the tools. We also have to build more intelligent manufacturing awareness into the tools.”

Failure to communicate

The fact that engineering teams are spread out around the globe doesn’t help matters. Even when analog and digital engineers are locked in the same building, they tend not to talk to each other. But none of the tools for developing chips have been constructed to deal with collaboration between teams, which is why most design is done in discrete units defined by the chip architects.

The problem is that in a mixed signal chip, it’s not just the teams that have to communicate. What they’re developing has to work well together, too.

“We’ve heard from some customers that to complete a chip in a compressed schedule, they tape out on tapeout day, whether they’ve finished the simulation or not,” said Bradley Geden, product marketing manager for AMS circuit simulation at Synopsys. “This is what causes re-spins. What’s needed is a formal methodology with sufficient verification and sufficient coverage in an AMS block.”

So far, that methodology doesn’t exist. Nevertheless, the amount of mixed signal content shows no sign of decreasing. Even with digital components there is growing analog content.

“As soon as you add analog onto a chip, the chance of respins increases three times,” said Mar Hershenson, vice president of product development in Magma’s custom design business unit. The schedule is more complex and the tools allow us to put more content on a chip. But they need to work much better. A lot of companies complain they don’t have enough analog designers, but the digital people and the analog people don’t speak the same language and they don’t have the same tools. When it comes time to integrate, that’s where the problem begins.”

Nevertheless, she said the real selling point for mixed signal chips is integration. The less work the customer has to do to integrate those functions, the more attractive a company’s technology looks.

Conclusion

Most tools vendors see mixed signal as an opportunity. They recognize that analog will never be completely automated because some functions will always be customized for a specific chip. But it can at least be enabled and integrated better into the complex design process that includes both digital and analog.

This becomes particularly important as analog engineers are forced to fit into digital design schedules. Getting a design out the door, relatively bug free and on schedule has been achievable so far primarily by ramping up the number of engineers working on those chips. There’s a bundle of money available to the tools vendors that can reduce that pain, and the race is already well under way.

System-Level Design sat down to discuss mixed signal design with Robert Hum, VP and general manager of Mentor Graphics’ Deep Submicron Division; Mar Hershenson, VP of product development in Magma’s custom design business unit; Eric Filseth, CEO of Ciranova, and John Stabenow, group director for solution and product marketing at Cadence. What follows are excerpts of that conversation.

By Ed Sperling
SLD: Analog has always been considered more art than science. How far has it come, and will it ever be automated?
Stabenow: It depends on your time frame. If you’re talking about the slide rule days, we’ve come a long way. If you’re talking about since 2001, we haven’t come that far.
Filseth: That’s right. The basic way of doing analog design hasn’t changed much over the last 15 years. The tools that support the original way of doing it have gotten incrementally better, but it certainly looks like we’ve hit a point of diminishing returns for how productive you can get the traditional methodology to be. The basic concept of how this is done—simulation, handcrafted layout, schematic layout, PDKs, parameter accels—have been there a long time. It isn’t likely to get twice as efficient under the current path.
Hershenson: The biggest change in the past 10 to 15 years has been in simulation and the capacity of the circuits it can handle today. But fundamentally it’s the same.

SLD: But how about the designs?
Filseth: They’ve changed dramatically. They are a lot more complicated. There are a lot more transistors in an analog/mixed signal design. We don’t see that much pure linear analog anymore. It’s all mixed signal.
Hershenson: The main tools for mixed signal are editors and simulators. That’s about it.
Filseth: If you think about the last major advancement, it’s shape-based routing, although arguably it’s used for assembly.
Hum: The digital domain has had the luxury of a unifying paradigm—RTL. That is the central idea that has driven abstract-to-specific automation. The digital side has parametrically focused on timing, but now that power has been added it’s getting more difficult. It’s hard to analyze timing and power. In the analog world there has not been, and there is unlikely to be, a unifying paradigm. The things that define phase lock loops are quite different from the things that make USB 2.0 PHY’s work.

SLD: So where will progress come from?
Hum: In the analog world, whatever progress there is will come from top-down, domain-specific approaches. What you used to do filter synthesis in the old days was a filter package. That doesn’t help for A-to-D conversion. In the analog world, the name of the game in automation is going to be tuned to vertical tracks, and it’s going to be pretty specific. In the next 10 years, there may not be any breakthroughs in this area. There is nothing happening in a coordinated way to create the automation for these small areas.
Filseth: That varies a little bit depending upon where you are in the flow. As you get closer to the architecture, you get more specialized. As you get closer to the silicon, things get more horizontal. And the level of horizontal-ness increases as you get closer to tapeout.

SLD: Is there room to do the different pieces separately?
Stabenow: It does have to be done together. We’re seeing mixed signal everywhere. But that doesn’t necessarily lead you to an analog automation path. You have this automation path on the digital side—things you can do with machines. But in the analog perspective, other than analog macros it’s all being done from scratch and by hand.
Hershenson: The A-to-D converters and phase lock loop are fundamentally different blocks, but they do share a lot of components. In a filter, a main block is a Gm cell or an Op Amp. It’s the same in some types of ADC. There is some commonality on the blocks being used in the different circuits. Otherwise in school we’d have to take 50 classes to become an analog designer. There are some concepts like linearity and gain that are common to different applications. The other thing we’re seeing is talk about integration shortening the design flow. It hasn’t happened. But one thing that has happened is that because of the complexity, there are many more data converters and PLLs on the chip. In digital blocks, high-speed I/Os have a ton of analog content.
Filseth: In the past half-dozen years there’s been a very interesting market split in analog/mixed signal. Traditionally, analog and mixed signal content was on a separate chip. If you were an analog/mixed signal IC company making data converters, you competed with another analog/mixed signal IC company on who had the best integral non-linearity spec on the data converter. Your chip would go onto a circuit board on an MRI system, and the lifespan would be seven years or more. In that sector, pure quality result is critical. Time to market was important, but not critical. You chose the best silicon technology for the job. If it was half-micron CMOS, that’s what you used. In the past half-dozen years, there’s been a different kind of analog/mixed signal chip. Anyone doing a networking chip needs a high-speed SERDES. People want to put PHY radios on a single SoC. The dynamics of the analog/mixed signal content is different. You’re not competing on specifications for your data converter. You’re competing on how fast you can get all this stuff out the door and will you be in time for Christmas? In this kind of market, what counts is good quality results. But top priority is getting all of this stuff integrated together. This is the part of the market that’s growing fastest.
Stabenow: I wonder if the automation won’t come in the form of macro IP. The big SoC guys will buy analog blocks. That means the design problem still exists back at the beginning where they’re generating the IP.

SLD: Is this a problem of people being used to doing things certain ways?
Hershenson: The new generation is different than the old generation. If you were working at Linear or Analog Devices and you got a 1% better gain in your Op Amp, you were king for a day. The major universities like Stanford and MIT have industry-funded programs to improve the analog design flow. Just having the core isn’t enough. You have to figure out how to put systems together. Systems are not just for cell phones. They’re for cars and bio-engineering. This is just beginning. It’s training analog designers plus CAD. The new people we interview know MATLAB and they’re not afraid of writing a Tcl script. I think that’s going to help a lot.

SLD: So what pieces can be automated?
Hum: There are several areas. There is a market developing for big D, little A, where little A is a hard analog block or some kind of malleable parameterized thing that’s a block generator. The problem is verifying that you’ve embedded the analog block and that it’s happy in its embedded location. We need the equivalent of analog assertions. In the digital world, you’ve got the digital assertion space, which looks at protocols between blocks. In the analog world, there is a set of assertions you can come up with. They’re clearly incomplete. Step one is to make sure it’s embedded right, that you understand the boundary and the handshake and transactions that go across it. Big D people wouldn’t know a transistor if it hit them. That’s not how they’re trained. They’re trained in finite state machines, complexity and how to do an 80-million gate design. All you want to know about your analog blog is that you’ve embedded it right. If you had a model that’s plus or minus 10% accurate, that’s enough.

SLD: So what’s the solution?
Hum: There are people working on these non-linear response surface models, which is one approach to it. There’s other work to look at automatic extraction mechanisms. Once you have a circuit and want to get a facsimile of that circuit in the digital domain, you need an interpolation function. There’s good work going on there in universities to generate interpolation functions. This is a different approach than synthesis. It’s de-synthesis. I have the polygons and the transistors and the SPICE mode

By Clive “Max” Maxfield

I’m a digital design engineer by trade. All of those wibbly-wobbly effects that are characteristic of the analog domain make me nervous, and if something makes me nervous I tend to look the other way and hope it will go away. But analog isn’t going anywhere. On the contrary, the increasing amounts of analog/mixed-signal (AMS) functionality that feature in today’s System-on-Chip (SoC) designs are making AMS the gating factor to success.

For those of us who come from a digital background, it can be difficult to wrap our brains around what’s happening in the analog realm with regard to design and physical implementation. So, just to set the scene, let’s start by considering a high-level view of the digital SoC design flow; we’ll then contrast this with its traditional analog counterpart; and finally we’ll consider some incredibly cool “stuff” with regard to analog design and physical implementation that’s heading towards us like a runaway express train.

One of the things that characterizes the digital portion of a modern SoC design flow is the extreme amount of automation that’s involved. The whole process starts when someone gets a capriciously cunning idea as to “the next big thing,” as illustrated in Figure 1.

  

Figure 1. A high-level view of the digital design flow.

There are two main concepts that are central to the digital flow: the use of intellectual property (IP) and the combination of high-level representations and synthesis technology. Early in the process, for example, the digital design team will select a bunch of IP blocks from their grab-bag of goodies—perhaps a CPU and/or a DSP, maybe a handful of peripheral and accelerator cores, possibly some interface functions, and so forth. This IP can account for a very large piece of the puzzle in terms of the SoC’s overall functionality.

When it comes to the “secret sauce” that will differentiate this product from its competition, the digital design engineers typically describe the required functions at the register transfer level (RTL) of abstraction (the IP blocks will also typically be specified in clear, encrypted, or obstruficated RTL).

Following a quick functional simulation (yes, I really am glossing over the complexities), synthesis technology is used to translate all of the high-level blocks forming the design into their gate-level equivalents. We then have access to incredibly sophisticated technology to generate a floorplan and to place the gates. This is followed by mind-bogglingly clever automated routing and optimization. In turn, this is followed by parasitic extraction, from which values are used to further refine simulation, timing analysis, signal integrity analysis, and so forth.

Once again, the above is a very high-level and simplistic view of the process that is intended only to illustrate the extreme amount of automation that permeates the digital portion of the flow.

This style of working – the use of IP along with RTL representations and synthesis technology – makes it relatively easy to capture and implement the digital portion of the design. (By “relatively easy,” I mean as compared to doing everything at the gate-level by hand. Can you imagine capturing a large SoC design as a bunch of logic gates and then placing and routing these gates by hand? As we shall see, that’s what the analog folks have to do.)

Furthermore, this style of working facilitates one’s ability to migrate a design from one foundry to another and/or one technology node to another. If you have an existing design at 65 nm and you want to migrate it to a 45 nm process, for example, you just swap the cell library, modify your constraints, press the “Go” button, and let the synthesis, floorplanning, place, and route engines perform their magic (I know this process is nowhere like as easy as I’m portraying it here … but it would certainly appear to be this straightforward to any analog folks looking at this flow).

A Conventional Analog Design Flow

So, what do you think life is like on the analog side of the fence? What amazingly cunning tools do those guys typically have at their disposal? Honestly, when you discover the truth, it makes you want to cry. Let’s consider a high-level view of the analog portion of the flow as illustrated in Figure 2.

  

Figure 2. A high-level view of the analog design flow.

Here’s the way it goes: We start with someone having a bright idea (with regard to the analog portion of the SoC), and everyone jumps up and down saying how wonderful it is. So all we have to do is implement it.

Analog IP? Don’t make me laugh (at least not process-portable analog IP). The best we can hope for is that we might be able to re-use some transistor-level schematics as starting points for portion of the design. The rest of the design will be captured as new transistor-level schematics.

Simulation is performed using a SPICE-like simulator or a fast-SPICE equivalent; synthesis doesn’t come into the picture at all. Generating a floorplan and placing the transistors and other components is performed by hand. Similarly, routing the design is performed by hand.

If we peer back through the mists of time to the 1980s, parameters such as the sizes of the transistors and other components were specified by the circuit designers as attributes in the schematic. These attributes were then used by the SPICE simulator, and also by the layout designer, who literally generated the various components (and later the routing) at the polygon level. (Actually, this is something of a simplification, because some attributes were – and still are to this day – communicated to the layout designer as text annotations in the schematic, or via a separate text document, or by paper and pencil.)

Sometime around the early 1990s, Cadence introduced the concept of PCells (Parameterized Cells), which are described in a proprietary Lisp-like scripting language called SKILL. In this case, the circuit designers place PCell symbols in the schematic and then associated parameters with these entities.

Eventually, each PCell uses its associated parameters to automatically generate the preliminary layout for that cell. The reason I say “preliminary” is because some layout designers will eventually convert the PCell representations into their polygon equivalents (this process is known as “smashing”) and then start “tweaking” these polygons by hand. The layout designers also have to do a bunch of other stuff like abutting, well-merging, interdigitation, and row-stacking in order to create a more compact layout. And then they get to do the routing by hand.

To provide a sense of scale, if we had a 30,000-transistor mixed-signal SERDES block, for example, the complete layout for this block could easily take a team of one or two layout designers two to three months (two-thirds of this would be the placement; one-third the routing).

I don’t know about you, but this doesn’t strike me as being a lot of fun.

A Brave New World

Wouldn’t it be great if the analog folks could use some special language to specify a function at a high level of abstraction, automatically synthesize this representation into an optimized transistor-level netlist, and then automatically place and route this netlist? Well, yes it would, but we aren’t there yet, so what can we actually do today?

One technique that has been around for quite some time is to hand-create a transistor-level netlist, to somehow specify which parameters can be varied and over what range of values, to define some way to measure the “goodness” of the output(s) and other criteria like power consumption, and to then kick off a long series of simulations that sweeps the various parameters across their respective ranges. The problem is that this approach works only with relatively small circuits, and even so it can take a huge amount of time and computational resources.

One company that is doing some really exciting things in the analog/mixed-signal arena is Magma Design Automation, with its AMS design platform called Titan. Using Titan acceleration technology, designers can code AMS functions as equations. Once the equations have been captured, the user can specify a target process/technology and Titan will generate an optimized implementation for that function.

My understanding is that writing and testing the equations can add 20% to 50% to the overall design cycle, which is something of a pain. However, once you’ve done this the first time, you can re-use this function in future projects. This technique has several advantages, including facilitating architectural exploration and also facilitating the migration of functions from one process/technology node to another.

Another company that is well worth watching is Ciranova. A couple of years ago they came up with something called PyCells. These are the equivalent of PCells, except that they are captured in the open source Python language. They also have PyCell Studio, which provides a complete standalone environment for creating PyCells that can be used with any OpenAcess tool (including tools from Cadence).

Now your first reaction may be: “Ho-hum, what’s all the excitement PyCells?” Well, actually they are jolly exciting, because as part of their implementation the folks at Ciranova have managed to fully separate the design constraints from the implementation technology. And why is this important? Well, in 2008 Ciranova introduced a tool called Helix, which performs automatic floorplanning and placement of an analog design.

As part of this process, Helix automatically executes all of the tasks that layout designers traditionally perform by hand, including abutting, well-merging, interdigitation, and row-stacking… and the result is a correct-by-construction, production-ready, DRC-clean placement. (How is all this possible? Well, in addition to being fully multithreaded, Helix employs incredibly cunning genetic algorithms, but I can say no more about this because I am bound to secrecy.)

A design comprising a few hundred transistors can be fully placed by Helix in a minute or so; a design involving say 30,000 transistors might take a few hours (compare this to multiple layout designers slaving for weeks or months as discussed above). Quite apart from anything else, this dramatically changes the picture with respect to migrating an existing design to a new process/technology node as illustrated in Figure 3.

  

Figure 3. PLL netlist placed by Helix, transistors resized,

same constraints, two technology files, runtime 30 seconds.

But wait, there’s more, because I hear that, slaving away in their secret underground bunker, the boffins at Ciranova (“They don’t let us out very often…”) are currently beta testing what they are at pains to call a “Trial Router.” Basically, this Trial Router can auto-route a design comprising a few hundred transistors in just a few seconds; a design involving say 30,000 transistors might take 30 minutes or so.

Now I’m not saying that you would take the results from this Trial Router and proceed directly to tape-out. In reality, the layout designers may end up throwing a lot (or all) of the Trial Route results away and re-doing it all by hand.

So what’s the deal? Well, the point is that the designers need to get a feel for the electrical performance that can be achieved by the design and they need this information as speedily as possible. Thus, the reason this Trial Router technology is so exciting is that you can quickly extract highly accurate parasitic values for the circuit and get a real good feel for how the circuit will perform.

I mean, if you can take a design that would normally take two months to place and a further month to route by hand, and you can generate a production-ready placement in a couple of hours and then perform a first-pass Trial Route in 30 minutes. Tell me that this isn’t exciting (I won’t believe you).

And as for the future…

As the famous American inventor Charles Franklin Kettering famously said: “My interest is in the future because I am going to spend the rest of my life there.” So what will the future hold with respect to analog synthesis?

Well, some folks think that true, top-to-bottom analog synthesis is a pipe-dream. Over the years there have been some amazing failures in this area, with companies claiming all sorts of things that never came to pass.

What about the technique of specifying a transistor level netlist and then varying a bunch of parameters to determine the optimum circuit configuration? Well, this really falls under the heading of “optimization” rather than “synthesis”.

A slightly more sophisticated approach might be to specify a function in terms of its transfer function and to use a computer to sift through hundreds or thousands of different topologies playing with the parameters for each topology. (When you come to think about it, this is really just circuit optimization with the addition of a couple more parameters.)

I think that the folks at Magma are doing some very interesting work and have certainly solved part of the puzzle, but (trust me on this) they would be the last to use the term “analog synthesis,” which is regarded as bad karma by the majority of analog designers.

Meanwhile, the folks at Ciranova have taken the approach that computers are great at performing “grunt work”, so they’ve automated the drudgery of placement and (“Trial”) routing. Although this doesn’t sound glamorous, it’s actually a rather amazing achievement.

But as for the ability to create a high-level specification and then synthesize a circuit topology… well, I’m not so sure (please feel free to quote me on this).

It was a good week for team approaches and an overall brighter outlook for the industry.

Synopsys teamed up with ARM to boost efficiency for ARM’s AMBA 3 interconnect, configuring the interconnect to eliminate unnecessary logic. That ripples down into better performance, lower power and less routing on an SoC. So now what do you do with all that space you’ve just opened up? See below.

Speaking of team approaches, TSMC and Cadence teamed up to provide a 65nm mixed signal/RF reference design kit focusing on behavioral models and a reference flow. Included in the release is a phase-locked loop noise-sensitive reference design. This is the most recent in what is expected to be a flood of tools aimed at the analog and mixed signal market, something that will become critical in SoCs that incorporate more and more functions to soak up all that extra space each process node provides. While the digital engineers will likely use whatever comes their way, the analog engineers are a lot pickier about these things. A big plus is that the reference design kit will help with mixed signal verification, which is where the real time savings are needed.

The auto industry may be down, but that doesn’t mean you don’t make tools to improve its efficiency. Mentor Graphics rolled out an integrated design environment for the Automotive Open System Architecture (AUTOSAR) system that uses standard interfaces and components dictated by AUTOSAR. Anything that helps Detroit regain its footing is good for the entire industry, given the number of electronics components that are finding their way into cars these days.

ARM unveiled physical IP for TSMC’s 40nm G process, balancing performance with lower power. The target markets are consumer devices like set-top boxes, disk drives, mobile computing devices, HDTV and graphics processors. Included is a power management kit and ECO kit library extensions for addressing current leakage by replacing or complementing the HVt, RVt or LVt implant layers with long channel-length devices.

Handset sales are stabilizing. TriQuint Semiconductor posted 7% gains in total revenues in the first quarter of 2009 compared to the same period in 2008, including a 24% growth in handsets. Given the fact that no one likes to be locked into a contract for more than two years, and the ongoing recession has been under way for 16 months, it’s getting to be that time for many people.

Computer sales revived in the past quarter. Intel posted Q1 revenue of $7.1 billion, along with a statement from CEO Paul Otellini that the industry is “returning to normal seasonal patterns.” There’s only so long you can keep an old laptop computer or server blade going before it starts costing you big bucks in productivity loss. The big question is whether the replacement is a new computer or a netbook or smart phone—or whether it’s some combination of those.

AMD reported revenue of $1.8 billion during Q1, which was flat compared to the fourth quarter of 2008. While it was down 21 percent from Q1 of 2008, it’s not exactly an apples-to-apples comparison because AMD no longer has an in-house fab. Still, it was better than anyone expected, even with an operating loss of $308 million. 

And finally, the whole market continued its drive upward. Both the Dow and the Nasdaq have been posting gains for weeks. While it’s too early to tell if this upward trend will stick, the market usually runs 6 to 12 months ahead of the overall economy, depending upon who you listen to. At the very least, it’s a signal for the foundries to begin starting up their machinery again and for companies to begin developing products for next holiday season.

–Ed Sperling

Analog and mixed signal IP began closing the gap with digital core IP in design explorations in the first two months of this year, a clear sign that multicore systems on chip have emerged as the dominant semiconductor model and that the architecture requires both types of IP.

While it’s too early to tell this year what effect that will have on overall design activity—the economy is the real determining factor there—the convergence is pronounced. In January, when chip design exploration typically is at its lowest even in a good year, there were 894 digital IP core explorations vs. 427 for analog and mixed signal. Last month, the number for digital had grown to 2,729 while those for analog/mixed signal had increased to 2350.

Off-chip interface IP also is becoming important, although to a far lesser extent. Much of that work is still being done by hand, but many industry insiders believe that approach will change over the next couple of process nodes as design engineers are called upon to add more context to their designs, including software applications and application interfaces, as well as connections at the board level. The exploration with off-chip interfaces was 211 in February, up from 75 in January.

On chip bus IP activity, meanwhile, was 173 in January vs. 327 in February, and verification IP—still in emerging market mode—showed 9 investigations in January and 28 in February.

January (blue) vs. February design investigations.

–Ed Sperling