Performing full-chip verification of large mixed-signal systems on chip (SoCs) is an increasingly daunting task. As complexity grows and process nodes shrink, it’s no longer adequate to bolt together analog or digital “black boxes” that are presumed to be pre-verified. Complex analog/ digital interactions can create functional errors, which delay tapeouts and lead to costly silicon re-spins. Cadence helps customers overcome these challenges with a fully integrated mixed-signal verification solution that spans basic mixed-signal simulation to comprehensive, metric-driven mixed-signal verification.

To view this white paper, click here.

By Ed Sperling
SoC design has largely been a race to the next process node in accordance with Moore’s Law, but it’s about to take a sharp turn away from that as the Internet of Things becomes more ubiquitous.

There has been much made about the Internet of Things over the past couple of years—home networks that involve smart refrigerators sending reminders to consumers that the milk is outdated. While this gee-whiz stuff grabs headlines, the reality is that the chips that drive these devices are hardly at the leading edge of design. Some of them date back to the half-micron processes, where things like layout-dependent effects, electromigration and finFETs aren’t even relevant.

But that’s only part of the picture. The real challenge to making this all work is much less about the wonders of technology and more about basic efficiency and cost in familiar areas such as network management, I/O, integration with mobile devices and software that can fuse it all together. And the real killer application appears to be the automobile, where the ability to eke out an extra 5 or 10 miles per gallon and to stay connected by voice without removing your hands from the wheel or your eyes from the road is critical to safety.

“This enters into the world of complex systems because you have to be able to simulate large numbers of things interacting together,” said Wally Rhines, chairman and CEO of Mentor Graphics. “The complexity increases at least as the square of the number of components. If you count the interactions, as long as you have a limited number of air-pressure sensors, light sensors, motion sensors, you can have dedicated signal processing for each of those sensors. As they start interacting, those interactions have to be verified and analyzed.”

Adding to the challenge, what is developed today may not be what it’s used for next year.

“You put out a network of 100 sensors and you’re worried about the interaction between them and the host,” said Rhines. “And then you decide that you’re going to do some other kind of interaction between sensors. That adds to the complexity.

The Internet of Things also relies heavily on analog at the front end—the part that senses and measures what’s going on around us—tied into a number-crunching digital back end. From a design standpoint, this is nothing new. But the challenge is how you manage all the data collected by these analog sensors without overloading the networks and the servers that need to make sense out of all of this—and still do it in an efficient manner with sufficient performance.

“You can’t just transmit all the data that you collect,” said Frank Schirrmeister, group director of product marketing for system development in the system and software realization group at Cadence. “It’s more of the client/server approach. The bandwidth is not there to deal with that. Bandwidth is certainly growing, but the amount of data is growing much faster than the bandwidth. That means you have to be smarter at the node. This is why every LED has about 800 bytes of software code. In the future, they’ll probably also be adding IP addresses, which will require more code.”

This doesn’t necessarily require new EDA tools, but it may require thinking about how to use them differently. Simulations need to be run not just for what is there today, but in a virtualized environment to understand future uses and the resulting corner cases that might result. Just as traffic on a chip can cause issues, traffic between chips on an ad hoc basis can cause similar problems. To a large extent, this requires thinking of network-connected platforms rather than chips, but ones that are cheap enough and small enough to fit in lots of different devices.

“You see this with the ARM M series,” said Schirrmeister. “Do you use a regular microcontroller or license the M and configure it to your needs. Platforms like this would help address future changes.”

Flexibility rules
One way of approaching the configurability unknowns is through derivatives. If an ASIC costs $30 million to design, a derivative might cost $10 million. But a platform derivative might be only $5 million, according to Naveed Sherwani, president and CEO of Open-Silicon.

“These are all niche markets,” Sherwani said. “So from a chip development standpoint, the volume is not there. It will have to involve derivatives. Those are the chips that will talk to the Internet.”

But flexibility is the key here. Because no one is certain how technology will be used, or how it will be used in the future, it has to account for that. Corner cases may involve unknowns and best estimates rather than fixed numbers. The Internet of Things involves everything from cars to chips that will be used inside the human body or even inside of livestock. As a result, being able to reconfigure connectivity will be essential to avoid obsolescence, particularly in the beginning as the concept begins rolling out.

“You need a waterfall approach because there is so much heterogeneous stuff that needs to be connected,” said Kurt Shuler, vice president of marketing at Arteris. “A lot of this is about connectivity, and standards will be important. But the other piece of this is that it will also involve humans interacting with machines. So it won’t just be one phone controlling the entire house. It will be lots of things working independently and together. So you need processing power for the human interactions—which is where a network on chip matters—but you probably won’t need so much in a device that is simply passing data along. And if you have cars talking to each other, you’ll need lots of busses.”

Conclusion
None of this will sort itself out overnight, and adoption may not be as straightforward as some proponents anticipate. Still, little by little, more things will be connected to more things, and controllable by more devices from more places.

Sun Microsystems and Novell promoted crude versions of these ideas as far back as the early 1990s, when they believed that networked devices could talk and possibly share processing capabilities. More than two decades later, that networking is wireless, processing power is plentiful, ubiquitous and inexpensive, and connectivity is almost a requirement.

But how all of this technology is used—and potentially used together—remains uncertain. Things talking to things make sense in some areas, but the promise undoubtedly is overhyped in others. For technology to take off it has to be inexpensive enough to be accepted by consumers, easy enough to use so that you don’t have to learn to program it, and practical enough that people will actually use it. The Internet of Things will succeed in some areas and fail miserably in others. But from a design standpoint, the more flexibility and connectivity that is built into devices and platforms—and the more that tools can identify potential conflicts across devices and networks rather than just a chip—the less impact failures will have. And the easier it will be to capitalize on successful segments while minimizing the downside of the less successful ones.

Custom and analog designers will lay the foundation for 20nm IC design. However, they face many challenges that arise from manufacturing complexity. The solution lies not just in improving individual tools, but in a new design methodology that allows rapid layout prototyping, in-design signoff, and close collaboration between schematic and layout designers.

To view this white paper, click here.

By Ed Sperling
Mentor Graphics updated UVM Connect, allowing it to be compiled to run with OVM. In case you’ve forgotten, Mentor and Cadence supported OVM, while Synopsys supported VMM. UVM is supposed to be the bridge between both these worlds, but it still isn’t fully baked yet—and some engineers are balking about learning everything from scratch.

Mentor also received certification for its Litho Friendly Design signoff tool for TSMC’s 20nm process.

Apple released its iPhone 5, offering substantially better performance and energy efficiency. But exactly how does that efficiency equate to battery life, particularly now that the company has reduced the thickness of the battery?

Intel took a similar route, focusing on low-power processors to change how people interact with their devices, starting with the Haswell architecture due out next year. The keynotes at this week’s Intel Developer Forum focused on new interfaces and more compute performance rather than extending battery life.

TSMC’s sales grew 2% in August compared with July, up 32% from August 2011. Revenues for the first eight months were up 16% compared to the same period in 2011.

A couple new books were released for verification engineers. One is the Mixed-Signal Verification Guide from Cadence. The second is SystemVerilog Assertions, which has been updated.

As process technologies continue to scale aggressively, it is becoming more challenging when developing high-quality, high-speed mixed-signal IP. Specifically, the 28-nm process poses some unique challenges not found in 65-nm and 40-nm technology processes.

This paper discusses the low power requirements found in 28-nm processes and addresses issues associated with the aggressive scaling of the core supply voltages in these technology processes. It also focuses on restricted design rules and how they have created a paradigm shift in the way circuits are designed and laid out in 28-nm processes as well as describes techniques to maximize design and layout reuse. Furthermore, the paper details design-for-yield challenges encountered in 28-nm processes and the verification methodologies used to ensure robust and manufacturable IP.

To download this white paper, click here.

By John Blyler
System-Level Design sat down with Nicolas Williams, Tanner EDA’s director of product management, to talk about trends in analog and RF chip design.

SLD: What are big the trends in analog and RF simulation?
Williams: The increased need to bring more layout dependent information into the front-end design early on. Layout-dependent effects influence performance, so it is no longer possible to separate “design” from “layout” phases, as we did traditionally. With nanoscale technologies, a multitude of physical device pattern separation dimensions must now be entered into the pre-layout simulation models to accurately predict post-layout circuit performance. This is more than just adding some stray capacitance to some nodes. It now includes accurate distances from gate to gate, gate to trench (SA,SB, etc.), distance in both X and Y dimensions between device active areas, distance from the gate contact to the channel edge (XGW), number of gate contacts (NGCON), distance to a single well edge (WPE), etc. Getting the pre-layout parameters accurately entered into the simulation will minimize re-design and re-layout resulting from performance deficiencies found during post-layout parameter extraction and design-verification simulations.

Another issue is larger variability at nanoscale. This is not so much due to manufacturing tolerance, but really because of layout-dependent effects. These effects include the ones listed above plus several that are not even modeled, such as nearby and overlying metal stress modifying Vt and gm and poor lithography. The lithography challenges are so severe in deep nanoscale that device patterns on final silicon look like they were drawn by Salvador Dali. Poor pattern shapes, increasing misalignment and shape-dependence on nearby patterns results in more gate length and width variation. More variability requires more complex simulations to have better confidence in your design. This requires faster simulators to simulate more corners or more Monte Carlo runs.

The lithography challenges are so severe in deep nanoscale that device patterns on final silicon look like they were drawn by Salvador Dali.

SLD: Statistical analysis, design-of-experiments, and corner modes—digital designers already hear many of these terms from the yield experts in the foundries. Should they now expect to hear it from the analog and RF simulator communities?
Williams: Statistical analysis and corner models have always been part of analog and RF design, but in the past it didn’t take much to try all combinations. There was no need to take a sample of the population when you could check the entire population. In nanoscale technologies, the number of effects that can affect circuit performance has grown exponentially to point where you have to take a statistical approach when checking corners. The older, alternative approach, of running the worst-case combinations of all design corners from all effects would result in an overly pessimistic result. Also, when the number of Monte Carlo simulations required to statistically represent your circuit has grown too large, that is where ‘design-of-experiments’ comes into play using methods such as Hyper Cube sampling.

Simulation accuracy is limited by model accuracy. Statistical variation of devices and parameters are more richly specified than the traditional SPICE approach for Monte Carlo (where you had “lot” and “device” parameters). Now you have spatially correlated variations, and you have the much richer .variation blocks in SPICE. Foundry models are now “expected” to provide usable models at this level, which raises all kinds of foundry-proprietary concerns.

SLD: How will this increase in statistical distribution analysis affect traditional analog electronic circuit simulators like Spice?
Williams: Statistical analysis requires a huge number of simulations, which can either take a long time to execute, or can be parallelized with CPU farms or cloud services, and smarter ways to sample which “corners” to run to get a reasonable confidence that you will be successful in silicon. Traditionally, aggregation of such results would have been a manual process, or at best some custom design flow development undertaken by the end user. Look for an upcoming sea change in how simulators are designed, sold and deployed by the EDA vendor community, to better address these needs.

All these simulations are great if your design meets all of its specifications. But what happens if it doesn’t? I feel the next step will be to use these simulations to figure out what variables your design is most sensitive to. Then you can try to mitigate the variability by improving the circuit or physical design (layout).

By John Blyler
System-Level Design (SLD) sat down to discuss trends in analog and RF integrated circuit design with Ravi Subramanian, president and CEO of Berkeley Design Automation, (at the recent GlobalPress eSummit) and later with Trent McConaghy, Solido’s CTO. What follows are excerpts of those talks.

SLD: What are the important trends in analog and RF simulation?
Subramanian: I see two big trends. One is related to physics, namely, the need to bring in physical effects early in the design process. The second trend relates to the increased importance of statistics in doing design work. Expertise in statistics is becoming a must. One of the strongest demands made on our company is to help teach engineers how to do statistical analysis. What is required is an appreciation of the Design-of-Experiments (DOE) approach—common in the manufacturing world. Design engineers need to understand what simulations are needed for analog versus digital designers. For example, in a typical pre-layout simulation, you may want to characterize a block with very high confidence. Further, you may also want to do that block extracted in post layout with very high confidence. But what does ‘high confidence’ mean? How do you know when you have enough confidence? If you have a normally distributed Gaussian variable, you may have to run 500 simulations to get a 95% probability of confidence in that result. Every simulation waveform and data point has a confidence band associated with it.
McConaghy: As always, there is always a pull from customers for simulators that are faster and better. In general, simulators have been delivering on this. Simulators are getting faster, both in simulation time for larger circuits, and by easier-to-use multi-core and multi-machine implementations. Simulators are also getting better. They converge on a broader range of circuits, handle larger circuits, and more cleanly support mixed-signal circuits.
There’s another trend: meta-simulation. This term describes tools that feel like using simulators from the perspective of the designer. Just like simulators, meta-simulators input netlists, and output scalar or vector measures. However, meta-simulators actually call circuit simulators in the loop. Meta-simulators are used for fast PVT analysis, fast high-sigma statistical analysis, intelligent Monte Carlo analysis and sensitivity analysis. They bring the value of simulation to a “meta” (higher) level. I believe we’ll see a lot more meta-simulation, as the simulators themselves get faster and the need for higher-level analysis grows.

SLD: This sounds a lot like the Six Sigma methodology, a manufacturing technique use to find and remove defects from high volume productions—like CMOS wafers. Will design engineers really be able to incorporate this statistical approach into their design simulations?
Subramanian: Tools can help engineers incorporate statistic methods into their works. But let’s talk about the need for high sigma values. To achieve high sigma, you need a good experiment and a very accurate simulator. If you have a good experiment but you want to run it quickly and give up accuracy, you may have a Six-Sigma setup, but a simulator that has been relaxed so the Six-Sigma data is meaningless. This shows the difference between accuracy and precision. You can have a very precise answer but it isn’t accurate.
To summarize: Today’s low-node processes have associated physical effects that only can be handled by statistical methods. These two trends mean that new types of simulation must be run. Engineers need to give more thought as to which corners should be covered in their design simulations. Semiconductor chip foundries provided corners that are slow, fast and typical, based upon the rise- and fall-times of flip-flops. How relevant is that for a voltage-controlled oscillator (VCO)? In fact, are there more analog specific corners? Yes, there are.

SLD: Statistical analysis, design-of-experiments, and corner modes—designers already hear many of these terms from the yield experts in the foundries. Should they now expect to hear it from the analog and RF simulator communities?
Subramanian: Designers must understand or have tools that help them deal with statistical processes. For example, how do you know if a VCO will yield well? It must have a frequency and voltage characteristics that are reliable over a range of conditions. But if you only test it over common digital corners, you may miss some important analog corners where the VCO performs poorly. A corner is simply a performance metric, such as output frequency. You want to measure it within a particular confidence level, which is where statistics are needed. It may turn out that, in addition to the digital corners you’ll need to include a few analog ones.
McConaghy: These terms imply the need to address variation, and designers do need to make sure that variation doesn’t kill their design. Variation causes engineers to overdesign, wasting circuit performance, power and area or under design, hitting yield failures. To take full advantage of a process node, designers need tools that allow them to achieve optimal performance and yield. Since variation is a big issue, it won’t be surprising if simulator companies start using these terms with designers. The best EDA tools handle variation, while allowing the engineer to efficiently focus on designing with familiar flows like corner-based design and familiar analyses like PVT and Monte Carlo. But now the corners must be truly accurate, i.e., PVT corners must cause the actual worst-case behavior, and Monte Carlo corners must bound circuit (not device) performances like “gain” at the three-sigma level or even six-sigma level. These PVT and Monte Carlo analyses must be extremely fast, handling thousands of PVT corners, or billions of Monte Carlo samples.

SLD: Would a typical digital corner be a transistor’s switching speed?
Subramanian: Yes. Foundries parameterized transistors to be slow, typical and fast in terms of performance. The actual transistor model parameters will vary around those three cases, e.g., a very fast transistor will have a fast rise and switching time. So far, the whole notion of corners has been driven by the digital guys. That is natural. But now, analog shows up at the party at the same time as digital, especially at 28nm geometries.
The minimal requirement today is that all designs must pass the digital corners. But for the analog circuits to yield, they must pass the digital and specific analog corners, i.e., they must also pass the condition and variations relevant to the performance of that analog device. How do you find out what those other corners are? Most designers don’t have time to run a billion simulations. That is why people need to start doing distribution analysis for analog corners like frequency, gain, signal-to-noise ratios, jitter, power supply rejection ratio, etc. For each of these analog circuit measurements, a distribution curve is created from which Six-Sigma data can be obtained. Will it always be a Gaussian curve? Perhaps not.

SLD: How will this increase in statistical distribution analysis affect traditional analog electronic circuit simulators like Spice?
Subramanian: Spice needs to start generating these statistically-based distribution curves. I think we are at the early days of that frontier where you can literally see yourself having a design cockpit where you can make statistics simple to use. You have to make it simple to use otherwise it won’t happen. I think that is the responsibility of the EDA industry.
McConaghy: The traditional simulators will be used more than ever, as the meta-simulators call upon them to do fast and efficient PVT and statistical variation analysis up to 6-sigma design. The meta-simulators incorporate intelligent sampling algorithms to cut down the number of simulations required compared to brute force analysis. Today, many customers use hundreds of traditional SPICE simulator licenses to do these variation analysis tasks. However, they would like to be able to get the accuracy of billions of Monte Carlo samples in only thousands of actual simulations. These analyses are being done on traditional analog/RF, mixed-signal designs as well as memory, standard cell library and other custom digital design.

SLD: I know that the several of the major EDA tool vendors have recently released tools to make the statistical nature of low process node yields more accessible and useable by digital chip designers. Are their similar tools for the world of analog mixed signal design?
Subramanian: Analog and RF designs are now going through this same process, to move from an art to a science. That’s why I say that the nanometer mixed-signal era is here (see figure). Simulation tools are needed, but so are analysis capabilities. This is why our simulation tools have become platforms for analysis. We support the major EDA simulators but add an analysis cockpit for designers.

Figure 1: Mixed-Signal and RF designs are now part of the nanometer SoC design process.

SLD: Why now? What is unique about the leading-edge 28nm process geometries? I’d have expected similar problem at a higher node, e.g., 65nm. Is it a yield issue?
Subramanian: Exactly. At 65nm, designers were still able to margin their designs sufficiently. But now the cost of the margin becomes more significant because you either pay for it with area or with power, which is really current. At 28nm, with SerDdes (high frequency and high performance) and tighter power budgets, the cost of the margin becomes too high. If you don’t do power-collapsing, then you won’t meet the power targets.

SLD: Is memory management becoming a bigger market for simulation?
Subramanian: Traditionally, memory has had some traditional analog pieces like charge pumps, sensitivity chains, etc. Now, in order to achieve higher and higher memory density, vendors are going to multi-level cells. This allows storage of 2, 4 or 8 bits on a single cell. But to achieve this density you need better voltage resolution between the different bit levels, which means you need more accurate simulation to measure the impact of noise. Noise can appear as a bit error when you have tighter voltage margins. You might wonder if this is really a significant problem. Consider Apple’s purchase of Anobit, a company that corrected those types of errors. If you can design better memory, then you can mitigate the need for error correction hardware and software. But to do that, you need more accurate analog simulation of memory. You cannot use a digital fast Spice tool, which uses a transistor table look-up model. Instead, you must use a transistor BSIM (Berkeley Short-channel IGFET Model) model.

EDA revenue increased nearly 18% in Q2, rising to $1.44 billion compared with $1.22 billion in the same period in 2010, according to the latest EDA Consortium numbers. Revenue was down 0.6% sequentially from Q1.

All geographies were up, year over year, with double-digit growth in the Americas, Japan, and Asia/Pacific. In addition, EDA employment was up about 3% year over year, and 1% sequentially. In the Americas, revenue was up 21% year over year; 18% each in Japan and Asia/Pacific, and 9% in Europe, the Middle East and Africa.

By category, CAE grew about 20%; IC physical design and verification grew 6%; PCBs and MCMs grew 22%; intellectual property grew 23%, and services revenue increased 20%.

EDA companies weren’t the only ones showing optimism. Semico Research issued its forecast that analog within the computing consumer and communications markets will grow 14%, 9% and 13% in 2011, 2012 and 2013 respectively.

Semico anticipates the market for analog will reach $61.9 billion in 2015. What’s particularly interesting is the consumer market will only account for about 23% of that number in four years; it currently represents 33% of the total analog pie.

One-On-One with IDT CEO Ted Tewskbury: How IDT is bridging the analog and digital engineering worlds with a mixed-signal team approach.