By Ed Sperling
Mentor’s Colin Walls looks around at where engineers can learn about embedded software. It seems none of the education is complete enough, so they have to cobble it together from a variety of sources. Sounds like good job security for those with a bank of expertise.

Cadence’s Richard Goering interviews a dual power-format user from Maxim about the convergence of CPF with the new IEEE 1801/UPF standard. There’s still room for improvement, but the new standard is a long-awaited giant step in the right direction.

Mentor’s Robin Bornoff questions the value of heatsinks as a magical way of cooling electronics. Bottom line: The heat still has to go somewhere—even after it’s dispersed by the heatsink.

Real Intent’s Prakash Narain kicks off a staff-written blog about what went on at DVcon ’13 and what trends they spotted. There’s a long list here, so pour a large cup of coffee.

IHS iSuppli’s Richard Dixon sees a bright future—or in his words, an exhilarating ride—for MEMS in the automotive market. Of particular note are the various architectures for this market.

Cadence’s Jack Erickson sees the Internet of Things as the next big driver of design—and high-level synthesis. Considering the emphasis will be on time-to-market rather than complex tradeoffs at the most advanced process nodes, there is a good case for HLS everywhere.

Synopsys’ Eric Huang takes a look at where USB 3.0 is showing up—new products, existing products, but not in smart phones. You have to wonder about that one.

Mentor’s Andrew Patterson looks at how embedded OSes are chosen by auto makers and why the current approach raises all sorts of questions about security and safety. Does anyone buy screwdrivers anymore?

Cadence’s Stacy Whiteman digs into delta markers in ViVA, Cadence’s waveform viewer. This kind of insight into tools is valuable for users of these tools.

Synopsys’ Mick Posner is wondering when the Pac-Man video game was launched. Unless this is a trick question, the answer is 1980. It was developed by the Nakamura AmusementMachine Manufacturing Co., or NAMCO, and distributed in the U.S. market by Midway.

And in case you missed the most recent issue of Low-Power/High-Performance Engineering, here are some standout blogs:

—Synopsys’ Cary Chin looks for logical answers on why his phone’s battery mysteriously drains while it’s asleep.

—Cadence’s Adam Sherer takes a lesson from Mario—Nintendo’s resourceful plumber.

—Mentor’s Steve Pateras shows off the latest development in built-in self-test—a new low-power version—and what it means for design.

—Atrenta’s Mike Gianfagna believes this may be the biggest and best DAC yet, even if it is in Austin.

—Apache Design’s Aveek Sarkar rolls out part two of his epic on challenges in IC and electronic systems verification.

—Calypto’s Ghulam Nurie says that just adding more clock gating isn’t enough. It has to be efficient clock gating.

—Nvidia’s Barry Pangrle questions whether power or performance is more important, and concludes that’s the wrong question to ask.

—And Chris Rowen of Tensilica/Cadence looks at why technology made such a big difference in the Boston Marathon bombing.

By Ed Sperling
Synopsys’ Mick Posner talks about painting fish models and tuning specs for his suped-up 440HP Subaru. This is what engineers do when they’re not thinking about FPGAs.

Mentor’s Colin Walls examines what an FPGA means to a software engineer. He may be onto something here. This is the Chunnel between hardware and software.

Cadence’s Richard Goering looks at the progress being made at 20nm, with 16nm FinFETs and 3D-ICs. TSMC expects to roll out 10nm finFETs by the end of 2015, with significant power savings. Check out the numbers.

Synopsys’ Eric Huang wonders about the economics of NAND flash if the price per gigabyte will drop to 17 cents by 2017. He also has some unusual survival tips.

Mentor’s Andrew Patterson plays tour guide to the upcoming auto industry meeting in Barcelona next week that will focus on in-vehicle infotainment systems and how to get Android apps included. The key here is keeping the GENIVI standard flexible enough to deal with a broad swath of solutions.

Cadence’s Stacy Whiteman provides a site map for online support for Virtuosity. This is great for the people who read the directions before assembling something.

Synopsys’ Hezi Saar extols the virtues of meeting power, performance and reusability requirements in mobile systems.

And in case you missed the most recent Low-Power/High-Performance Engineering newsletter, here are some standout blogs:

- Mimasic founder Bhanu Kapoor digs into what’s coming in power management and why changes are needed.

- Nvidia’s Barry Pangrle looks at the promise of delay-insensitive circuitry at a reasonable cost.

- Apache Design’s Aveek Sarkar rolls out part one of his forthcoming epic on challenges in verification, including the three criteria that design teams have to simultaneously meet.

- Atrenta’s Bernard Murphy examines RTL-based estimation integrated with power reduction.

- Synopsys’ Cary Chin poses a question: What slick new mobile device is facing energy-efficiency complaints? The answer will surprise you.

- Mentor’s Shabtay Matalon looks at the value of virtual prototyping that supports power and software analysis.

- And Tensilica’s Chris Rowen takes a trip to Italy and observes that people really do with the technology we develop.

By Ed Sperling
Synopsys’ Parag Goel highlights some of the papers on verification and SystemVerilog that will be presented at next week’s Synopsys User Group, aka SNUG. If you’re registered, grab a large cup of coffee. There are papers here from Freescale, Intel, Cisco, AMD and others.

Cadence’s Jack Erickson sheds some light on an intriguing paper about sharing approaches for high-level synthesis, which was unveiled at DATE this week. After years of promise, HLS is beginning to take off. It’s amazing what a few hundred million extra gates can do to a market.

Mentor’s Dennis Brophy notes that the IEEE unanimously approved the new Unified Power Format standard, bringing visual acuity to a bad case of double vision. It may take some time to clean up this mess of dueling power formats, but this is a major step forward.

Real Intent’s Jim Foley takes a deep dive into non-block assignments for combinational logic. If you work in this area, grab a knife and fork.

Arteris’ Kurt Shuler examines IP transaction protocols, including AMBA, OCP and others, and why interconnects need to be agnostic.

ARM’s Karthik Ranjan looks at bringing the benefits of smartphones to Pay TV, a change that will be fueled by “headless gateways.” This sounds like something out of a Tim Burton film, but Internet TV is long overdue—especially when you pay for 500 channels and can’t find anything to watch.

Synopsys’ Eric Huang woke up in the wrong time zone. Why else would someone look this happy in the middle of the day? (Scroll down to the photo.)

Cadence’s Richard Goering captures the meat of the recent EDA CEO panel last week on subjects ranging from consolidation to Moore’s Law. Make sure you check out the picture. Who’s having fun and who isn’t? Goering also shed some light on why Cadence agreed to buy Tensilica and what it means for SoC design.

Mentor’s Colin Walls takes on the concept of endianness—so named for code ordering based upon the shape of an egg. Code is written either right to left or left to right depending on whether it’s little endian of big endian—a problem that plagued the Unix world for decades. These days, it’s a relatively simple fix, as long as you plan for it.

Synopsys’ Navraj Nandra explains what “gears” mean for the MIPI M-PHY. This gives new meaning to the term “gear head.”

Cadence’s Frank Schirrmeister explains the Internet of Things, which is expected to include 50 billion devices connected to the Internet by 2020. Apparently cows are on the list of things, which is certain to confuse animal rights activists.

Synopsys’ Karen Bartleson interviews Russ Housley, chair of the Internet Engineering Task Force, on how the Internet works. It’s nice to see something can work so well with no one in charge of it.

And in case you missed last week’s Low-Power/High-Performance Engineering newsletter, here are some noteworthy blogs:

—Docea Power’s Ghislain Kaiser pinpoints five things you need to consider in low-power verification.

—Apache Design’s Norman Chang digs into ESD compact models for chip-package-system simulation.

—Atrenta’s Bernard Murphy compares guesswork to other design approaches.

—Power architect Barry Pangrle notes that leadership changes across the industry could herald much bigger changes ahead.

—Tensilica’s Chris Rowen looks behind the scenes at his company’s history and purchase by Cadence.

—Mentor’s Tom Fitzpatrick shows off some best practices for power control modeling in verification.

—And Synopsys’ Cary Chin looks at the fine balance between standards and healthy competition.

By Ed Sperling
Mentor’s Colin Walls compares the speed of programming in C, C++ and assembly code. The actual writing of the code doesn’t vary that much, but when it comes to experimenting and testing, C is still tops.

Cadence’s Richard Goering is touting a new white paper about improving gate-level simulation performance. The simulation is necessary, but like all accurate measurements it has been bogging down under the weight of larger designs.

Synopsys’ Karen Bartleson is on the hunt, asking what standards should be developed and whether a compliance lab is needed for existing standards. Our advice: Weigh in on this one. We can’t afford another UPF/CPF/IEEE 1801 version x.0.

Real Intent’s Vaishnav Gorur rolls out part three of his clock domain crossing epic, this one on clock and reset ubiquity. CDC has become a huge problem in complex designs. While it can’t actually be eliminated, at least it can be tamed.

IHS iSuppli’s David Hancock says 35mm film is now in the minority because most movie theaters went digital at the end of last year. This may be a bad time to consider a career as a projectionist.

What makes an executive world-class? According to Mentor’s Michael Ford, they’re the one with the five-year survival plan. And when all else fails, restructure. That will keep the board guessing until the next upswing, at which time the exec can take full credit for a turnaround.

Cadence’s Jack Erickson cuts through the misinformation stream about high-level synthesis support to set the record straight on SystemC support.

Synopsys’ Mick Posner points a spotlight on partitioned blocks with more signals than physical IOs, which as you can guess will affect system performance. Less obvious are the advantages of interconnect flexibility.

Real Intent’s Jim Foley picks a lint rule and digs in. This one is ARITH_CONTEXT. If you work with linting, grab a cup of coffee and a pen.

Mentor’s John Day looks at the controversy surrounding the Tesla electric vehicle that ran out of power in Connecticut and why standards are so necessary. We may never know what really happened, but a dead car in the middle of winter in southern New England is no place to be thinking about it.

And in case you missed the most recent Low-Power/High-Performance Engineering newsletter, here are some standout blogs:

—Synopsys’ Cary Chin looks at the foundations of low-power design and what comes next.

—Mentor’s Arvind Narayanan shows how understanding multi-corner, multi-mode can improve battery life.

—Apache Design’s William Ruby observes that clock gating is low-hanging fruit, but you have to pay attention to the metrics.

—Tensilica’s Chris Rowen writes that with good people and good tools, anything is possible.

—Docea Power’s Gene Matter looks at what’s needed to build power models for good power estimation. Say goodbye to spreadsheets.

—Atrenta’s Mike Gianfagna pinpoints the biggest challenge for Moore’s Law in the future—EUV lithography.

—Low-power architect Barry Pangrle observes that not everyone sees finFETs as the next big thing. You’ll be surprised to find out who’s not convinced.

By Ed Sperling
Mentor’s Robin Bornoff rolls out part one of his forthcoming epic on experimentation vs. simulation, and how to make sure a product doesn’t fail, doesn’t need tweaking—or get canned altogether.

Cadence’s Richard Goering looks at the challenges of test in 3D-IC memory on logic and how this issue is being solved. Given the fact that chips are now being produced using this technology, with many more on the way over the next few years, effective test methodologies are critical.

Real Intent’s Vaishnav Gorur unveils part one of his look at clock domain crossing strategies, starting with the best way to structure an electronic tour of a city. This is like something out of an Isaac Asimov story.

Semico Research’s Michell Prunty looks at a less controversial kind of gun control—more accurate devices for first-person shooting games. This technology is probably safe to leave lying around the house.

Mentor’s Randall Myers digs into how to do high-speed serial correctly—and why Intel is following AMD on this one.

Cadence’s Joe Hupcey looks at the top four trends at CES that benefit EDA—mobile, automotive, standards and TVs.

IHS iSuppli’s Mike Howard questions whether the DRAM market can return to growth this year. Answer: Maybe. That should provide great comfort to people.

Cadence’s Hans Zander has some tips for Specman users working with random generation misbehavior and how to debug it. If this is your language, take notes.

And in case you missed last week’s Low-Power/High-Performance Engineering newsletter, here are some noteworthy blogs:

Synopsys’ Cary Chin looks at the writing on the wall at the Consumer Electronics Show and what it will mean for semiconductors.

Mentor Graphics’ Arvind Narayanan rolls out some useful guidelines for multi-voltage chip design.

Tensilica’s Chris Rowen digs deep into the benefits of efficiently computing across a wide data word and how tweaks there can have more impact than moving to the next process node.

Apache Design’s Aveek Sarkar and ANSYS’ Lawrence Williams explain why streamlined approaches are needed for more robust and reliable designs.

Docea Power’s Gene Matter looks at the combination of transaction-level modeling and power analysis.

Atrenta’s Mike Gianfagna says that improved energy will be a pre-requisite to even getting into a discussion with customers this year.

And Nvidia’s Barry Pangrle compares the new crop of supercomputers for speed and performance.

By John Blyler
Panelists from industry, national laboratories, and the Portland State System Engineering graduate program recently gathered for an open forum on model-driven engineering.

The goal of the forum—which was hosted in collaboration with PSU, the International Council on Systems Engineering (INCOSE) and IEEE—was to connect systems engineering and IT modeling to domain specialties in electronic/electrical, mechanical and software engineering. Panelists included speakers from Mentor Graphics, ANSYS, CH2M Hill, Pacific Northwest National labs, SAIC, Veterans Affair Resource Center and PSU.

To clarify what is meant by systems engineering (SE), Herman Migliore, director of PSU’s SE program, cited Norm Augustine’s often quoted definition: Systems engineering is the practice of creating means of performing useful functions through combination of two of more interacting components. This broad definition encompasses all domain specific SE disciplines, including hardware and software.

Migliore noted that modeling the entire system engineering process, from beginning to end, is made difficult by the challenges of exchanging modeling information between all disciplines. These disciplines include engineering, science, business and even the legal profession, as well as vertical markets such as defense, electronics and software.

“Each discipline and market has it own view of engineering and modeling the system,” said Migliore. The challenge becomes integrating all these differing points of view. That’s why the one model that might unite them all is the Vee-Diagram, which emphasizes the decomposition of the high-level system into component pieces, followed by the integration of the components into a working whole. This approach requires designers to consider test, verification and validation requirements at every phase of the development life cycle.

Next up was James Godfrey from CH2M-Hill, a construction management company that includes semiconductor equipment programming and deployment. To date, many vendors use UML diagrams to engage customers about needed processes that will then be created in software. Unfortunately, UML doesn’t address continuous systems needed for continuing improvement, according to Godfrey. SysML does deal with continuous processes, e.g., pumps, fans and moving waste.

Doing his work at PSU, Godfrey learned about a collaborative system M&S framework developed at Georgia Tech (see diagram below).

Many in the construction management world question the need for models. Godfrey noted that these users wonder why that can’t continue to use Visio to capture typical construction drawings and specification. This often leads to a redundant entering of information into static diagrams and then later in dynamic models.

“Reality feeds into models that then can become diagrams,” said Godfrey. All of which should be stored in one data repository.

ANSYS approached the system modeling challenge from a more electronics point-of-view. According to Andy Byers, ANSYS started as a structural analysis company in the nuclear industry, among others. With the acquisition of Ansoft in 2008, ANSYS added electromagnetic modeling. System-level multiphysics and electronic power modeling were added with the purchase of Apache Design a few years later.

Today, most engineers communicate via documents. But many now want models in addition to documentation for the systems they’re building or integrating. Yet models in one engineering domain don’t often translate well to other domains.

“Pictures may be best way to talk across different engineering disciplines,” observed Byers.

Another factor encouraging model-driven development is that many component companies are now moving up the supply chain (or left-hand, integration side of the Vee-Diagram) to create subsystems, including both embedded hardware and software.

As companies are moving further up the system supply chain, they are finding out that optimization modeling techniques don’t scale across multiple point and physics, noted Byers. Such inefficient optimization leads to overdesign, where designers leave too much margin on the table. This message was a key theme at the recent Ansys-Apache Electronics conference (JB: reference]

But a system-level model must be simple enough for all engineers to use. Today, most analysis are set up and performed by a few experts with PhDs. These experts are becoming a bottleneck, said Byers. “There needs to be a democratization of simulation to the engineering masses.

Finally, as useful as the Vee-Diagram is for system-level modeling, users must look beyond engineering to other systems, like cost, schedule, and even legal. Focusing on this last point, Byers related a story concerning the exchange of models in the automotive industry between and OEM and a Tier 1 (subsystem) and Tier 2 (component) vendors. In order to avoid intellectual property (IP) and gross negligence issues, the OEM lawyers wanted to embedded a legal model into the engineering one. It was unclear as to the success of this approach.

Switching perspectives, Ryan Slaugh spoke about the challenges of hardware-software integration from the standpoint of the Pacific Northwest National Labs (PNNL). With its changing mission, PNNL is facing a problem that is commonplace to electronic companies—deciding when research projects are ready for commercialization. “ We are trying to cross the chasm of death from R&D to successful product development,” said Slaugh.

To determine the maturity of an R&D project, PNNL uses a Technology Readiness Level (TRL) process. This helps grade projects to tell when they might be ready to become products. For example, a project with high confidence, which is one that re-uses known good hardware and software, has a low score. Once in the product stage, systems engineering techniques are applied to the life cycle to low the risk of failure.

How are complex modeling approaches taught to students? What is needed to help college students get used to modeling? These questions where addressed by William “Ike” Eisenhauser, an affiliate professor at PSU and director of…

Simple modeling approaches make great communication tools, especially for non-technical professionals. But in essence, all models are wrong, noted Eisenhauser. “Yet some can be useful.”

Eisenhauser presented a brief overview of different kinds of models:

1. Simple representation: e.g., solar system ball-and-string model in high school.
2. Math model: Describes a situation (y=function of x).
3. State diagram: Moving from math to device representation.
4. Engineering flowcharts (non-math models): Communicate to others to help make decisions.
5. Behavior models: More complex, intended to describes why system behaves as it does. These models help to predict change.
6. Discrete models: Sometimes mistaken for the actual system. They demonstration implementation, e.g., balls moving in a physical model.

The greatest challenge with modeling is teaching that models are just tools, not playthings. “Modelers must learn when to stop using models,” cautioned Eisenhauser. “This is a critical lesson for engineers. “

The problem is that students go into modeling because they want to create cool models. It is an analogous problem to physics majors who go into physics to build light sabers, not to help mankind with issues of global importance, said Eisenhauser.
That’s why it is important to teach engineers the objectives of modeling and knowing when to stop.

How does modeling fit into the role of systems engineering? Unfortunately, SE remains a text-intensive discipline. Documentation matters in detailing complex systems. There is an ongoing need to reduce text editing in SE modeling. That’s where system-modeling approaches such as SysML can help.

The educational problem that Eisenhauer and others in PSU’s SE program face is how to provide a useful SE modeling tool. All such tools—even SysML—require more than one 8-week course to learn. Any such tool will need to be taught across several classes.

Is SysML the best tool for SE modeling in university course? That’s an ongoing challenging in modeling education, namely, how to discern the popular software-of-the-day from truly useful and market-acceptable tools, said Eisenhauser.

The final speaker was Bill Chown, from Mentor Graphics. He spoke about Model Driven Development (MDD), a contemporary approach in which the model is the design and implementation is directly derived from the model.

The challenges facing system designers are well known, from increasing complexity to the convergence of multiple engineering disciplines and the associated problem of optimizing a comprehensive system design.

The design team itself is a dynamic entity, comprised of an architect or systems engineer, the hardware or software component designer and the system integrator who puts it all together, noted Chown. Further, each of these professionals may only be involved in the design for their portion of the life cycle, such as from the concept through design and to domain specific areas.

What types of models are used through the lifecycle? Chown listed three categories:

1. Platform Independent model, which includes function, architecture, interfaces, interactions and which can demonstrate that requirements are understood and met.
2. Platform-dependent models, such as hardware architectures with virtual prototypes or software architectures with partitions and data, which can be used to determine resources and performance goals and for hardware-software co-design before physical implementation.
3. Platform-specific models, for implementation, verification, test and deliverables.

Models can and should drive implementation. For example, software models can generate code once configured to an RTOS. Hardware flows have emerged for C-to-RTL synthesis and UML-to-SystemC simulation and validation. Test languages also can be generated directly from models.

Model-driven design has evolved to cover the full system or product life cycle, from requirements to prototype and then production.

By Ed Sperling
Mentor’s Nazita Saye examines the shrink and pink phenomenon—and why embedded simulation pays for itself. This is like reverse engineering a shopping trip.

Cadence’s Richard Goering interviews Sigrity CEO Jiayuan Fang. Of particular note is the positioning for the PCB and 3D-IC worlds.

Synopsys’ Eric Huang looks at market dynamics for WiFi-AC routers and questions why no one will stand next to him—or even close to him—during a video shoot.

Vista Ventures’ Jim Hogan lays out the custom design market, what’s changing, and who’s doing what. The gang’s all here in a Cutom 2.0 posting on John Cooley’s DeepChip.

Mentor’s Mike Jensen compares engineering expertise to practicing to become a professional musician. The work seems to be steadier for most engineers, though.

Cadence’s Jason Andrews is back with some insights into the Linux kernel message system updates. If this is your area of expertise, take note.

Synopsys’ Mike Thompson questions why people are still using 8-bit processors when they could be using 32-bit processors for the same tasks. It’s like taking your riding mower out on the freeway.

Semico Research’s Jim Feldhan digs into the lack of innovation in the ultrabook market and why there should be lots of upside for this market. For anyone who has tried to seriously create content on a tablet or smart phone, that should be readily apparent—unless you have chicken fingers.

Mentor’s Colin Walls calls himself a professional enthusiast. That’s certainly easier to comprehend than embedded system coding for a non-technical person.

Cadence’s Yuri Tsoglin offers up some tips on using long expressions in e, which can result in coding errors even though they’re supposed to be legal.

Synopsys’ Mick Posner shows off a customer’s HAPS Christmas tree, decorated with fan shrouds. What do you tell them? Cool?

And in case you missed last week’s Low-Power/High-Performance Engineering newsletter, here are some notable blogs:

— Mentor’s Erich Marschner peels back the covers on the next version of UPF.

— Synopsys’ Cary Chin compares politics to engineering, and what it would mean for battery life.

— MIPS’ Rao Gattupalli looks at the role of virtualization in creating secure embedded systems.

— Apache Design’s William Ruby tackles how to debug your design for power.

— Nvidia’s Barry Pangrle observes that predictions about arranging atoms are finally coming true.

— Atrenta’s Mike Gianfagna looks at the end of the road map and what’s next.

— And Docea Power’s Gene Matter digs into power simulation and hardware emulation, and why not both?

By Ed Sperling
Mentor’s Mike Jensen looks at why companies don’t share simulation expertise. The reason? Most companies perceive it as competitive information.

Synopsys’ Navraj Nandra digs into fuzz, which is roughly the same stuff that hard rockers used to add into their music intentionally back in the 1960s. Now everyone wants it out. Time to call in the sound crew.

Cadence’s Richard Goering reports on a presentation by Alberto Sangiovanni-Vincentelli of UC Berkeley about the coming swarm of devices—7 trillion devices, give or take a few billion. That works out to about 1,000 per person.

IHS iSuppli’s Peter Lin analyzes the PC market and says that mainstream and value PCs are far more popular than high-performance models, which only account for about 9% of the market. Looks like gamers have switched to other platforms.

Mentor’s Mark Laing wants to know where the missing pieces are in process engineering software. The answer may depend on the process node.

Synopsys’ Hari Balisetty digs deep into reusable sequences in UVM. You might need to study this one.

Cadence’s Tawna Wilsey previews some of the upcoming changes in MMSIM 12. If you use this tool, there’s some useful information here.

DeepChip’s John Cooley unveils a wide swath of rumors from all sides of the industry, ranging from design tools and potential marriages all the way through to who’s going to manufacture Apples upcoming 20nm quad-core chips.

And in case you missed this month’s Low-Power/High Performance Engineering newsletter, here are some noteworthy blogs:

— Independent power architect Barry Pangrle weighs the impact of ARM’s big.LITTLE architecture on the IC industry.

— Synopsys’ Cary Chin takes a look at the iPad Mini, and lauds its arrival—even without a Retina display.

— Cadence’s Luke Lang digs deeper into CPF 2.0, and uncovers new features that aren’t available in the previous version.

— Tensilica’s Chris Rowen examines what’s needed to simplify design and to really scale multicore.

— Apache Design’s Matt Elmore rolls out part two of his epic on the growing challenges of ensuring signal integrity.

— Atrenta’s Mike Gianfagna questions why no one will insure IP.

— Docea Power’s Gene Matter looks into power and thermal trends and challenges at the system level.

— MIPS’ Duane Sand examines why the new release of Android is so interesting.

By John Blyler
Power continues to be a challenge in the design of System-on-Chips (SoCs) for the mobile handheld space. Consumers want ever-increasing compute capabilities to quickly handle new handset functionality as well as perform traditional PC applications. To meet these needs, chip designers must continue to push the performance envelope with a variety of low-to-high end processing cores while maintaining the same power budget as earlier generation handhelds.

As if that wasn’t challenging enough, designers must also pay attention to the thermal envelope limit. Why has thermal become so important? First, a handheld device can’t become too hot to hold. Second, uncontrolled or unplanned thermal affects could force the handheld device to throttle down on performance to prevent overheating of the circuitry. Both are “no-no’s” from a consumer use perspective.

Figure 1: The increasing power gap highlights the growing importance of battery and thermal constraints in system chip design. (Source: Apache Design)

Balancing the competing performance-power-thermal requirements necessitates a system-level approach to design. But the balance has shifted in recent years as power concerns now seem to dominate over performance issues. “In my opinion, power is leading performance, especially since the thermal limit has become a challenge,” explained Charles Matar, vice president of engineering at Qualcomm, during a recent keynote at the Ansys-Apache Design “Dimensions of Electronic Design” seminar.

To really manage power usage, battery life and thermal envelope limits, one must design for multiple performance nodes. These modes, in turn, are based upon the software application that is running and other workload concerns, such as connectivity. Dealing with the integration of both hardware and software (firmware, RTOS and OS) subsystems mandates a full system-level approach. But full system power modeling tools have lagged behind performance-focused modeling.

Software compilers for heterogeneous-core chips with many ARM processors, GPUs, DSPs, and other cores are not optimized for the system. This creates software executables that are not workload optimized across all the processing units, observed Simon Bloch, an adviser in the Advanced Systems Engineering Lab at Samsung.

“EDA tool companies continue to improve their offerings but are still designing for performance—their number one priority,” said Matar. He cited place and route (P&R) tools as an example, where algorithms that focus on component placement need to be more thermally and power-aware.

Bloch agreed, noting that the electronic system-level (ESL) and SystemC community had standards for modeling performance, but there were no standards that exist for modeling power.

But the development of high-level ESL and TLM power modeling tools face at least one major challenge. Many believe there needs to be more industry focus on system-level power models and standards that reach well beyond the existing chip-level power standards. To achieve this goal, all of the SoC industry fabless intellectual property (IP) vendors must work together with foundation IP providers to develop standards for both power and thermal modeling.

Developing these system-level models and standards would also address the growing issue of overdesign. Generous design margins are often the result of engineers working in silos. “As design teams are spread across companies and continents, designers may not be able to share the same information,” explained Aveek Sarkar, vice president of product engineering and customer support at Apache Design. “If you are designing the IP, you may not be aware how the IP is being used at the full chip level. So you tend to over-compensate, over-design to protect yourself for the entire system. That leads to increased cost and power usage.”

Matar ended his keynote presentation by talking about new technology trends in mobile SoC design, including heterogeneous computing, 3D-ICs with through-silicon vias (TSVs) and finFet transistor structures.

Heterogeneous computing refers to a variety of low-, medium- and high-performance processing cores on the same SoC, sometimes referred to as small and big cores. Heterogeneous also including different types of cores, from general-purpose (GP) to graphic computing units (GPUs) and application-specific processors. The availability of these different processing engines means that chip designers can offload tasks to the appropriate processor to optimize power and performance. But these offloads must work closely with the high-level operating system (HLOS) so the software programmer can take full advantage of the available compute power. Naturally, all of this requires good hardware and software system-modeling tools.

As with any new technology, 3D-ICs with TSVs still face yield, cost, and thermal challenges, noted Matar. He observed that TSVs will be especially helpful for performance and power management in the graphics and memory areas.

New process technology such as finFet transistor structures will allow designers to continue to benefit from voltage scaling at lower process nodes. 3D structures are a shift in paradigm from a transistor perspective that should provide the same or higher performance level as today’s planar technology but at lower power (voltage).

Figure 2: Decreasing noise margins at lower process nodes will pose a challenge for finFet device designers. (Source: Apache Design)

Still, finFet structures won’t be without their tradeoffs. For example, supply voltage scaling for finFets will range from 700 to 800 mV by next year. “But the supply noise due to switching currents on the SoC will continue to rise,” said Sarkar. “So these two trends of high frequency devices at low power will play against each other.”

Regardless of the latest technology trends, the broader view afforded by a system-level approach will be needed in mobile handset and most other electronic system designs. Sarkar made this point by citing a customer design that involved and SoC application processor. The customer integrated the SoC into a package—all designed by the same company. The chip-package system was designed to work at 2GHz, which it did. But when the chip-package was sent to the end customer it failed. Why? The end customer incorporated the chip-package subsystem into a low-cost board and the voltage dropped by 300 mV, which resulted in the chip performance dropping to 1.2GHz.

The need for a system-level model that incorporates power, thermal and performance awareness is becoming critical in the mobile handheld, as well as the general electronic markets. Both speakers from Qualcomm and Ansys-Apache Design shared their perspectives, from SoC to larger electronic systems, as to why this trend will continue. Hopefully, the EDA tools industry and power standards organizations are listening.

By Ed Sperling
Mentor Graphics significantly beefed up its Questa verification platform, adding automated formal assertions that can quickly identify and separate out problems that can slow down the verification process. One of the big benefits of formal verification is that it can reach parts of a design that are difficult to debug using standard techniques and pinpoint areas that cause problems. One of the drawbacks is that most verification engineers aren’t proficient in writing assertions, so automating the process is a big deal. Included as a bonus is code coverage closure.

Mentor also rolled out design, verification and test solutions for TSMC’s 20nm infrastructure, which includes support for double patterning,  as well as support—all of the above plus thermal tools—for TSMC’s Chip on Wafer on Substrate (translation: stacked die) reference flow.

In fact, all of the Big Three EDA companies made announcements with TSMC this week. Synopsys is collaborating with TSMC on its 20nm reference flow, as well, with its Design and IC compiler tools, silicon calibration modeling and double-patterning-ware variation analysis. Synopsys also joined the Partners for the Advancement of Collaborative Engineering Education, an initiative started by GM, Autodesk, HP, Oracle, Siemens and PLM Software.

And TSMC validated Cadence’s Wide I/O memory controller and PHY IP for its stacked die reference flow. The foundry also has included Cadence’s Virtuoso and Encounter platforms in its 20nm infrastructure for custom, analog, digital and mixed signal design.

In addition, Cadence announced a deal with Taiwan’s Industrial Technology Research Institute, which used a variety of Cadence tools to tape out a 3D-IC chip.

TSMC also chose Apache Design’s RedHawk, Totem, Chip Thermal Model and Sentinel-TI for its 20nm and stacked die reference flows, as well as the Slwave and Icepak tools from Apache’s parent company, ANSYS. These tools address thermal analysis, run-away and thermal-induced electromigration, as well as power, noise and reliability issues.

The on-chip network market is booming, thanks to the need to quickly stitch together more third-party IP blocks in SoCs. Sonics passed the 2 billion unit mark for licensees  and Arteris was ranked No. 4 on the list of fastest growing private companies in Silicon Valley—behind Adap.tv, Audience and Axcient. Notice they all start with the letter A. Number five on the list was Aerohive Networks.

IntegrIT ported and optimized its acoustic echo cancellation and wideband technology for Tensilica’s DSP software solutions. IntegrIT’s AEC WB codec adds high-definition voice for mobile platforms.