By Ed Sperling

The network on a chip (NoC) approach is gaining ground as an essential part of a system on a chip (SoC), providing the same kind of time-to-market advantage that well-tested intellectual property blocks provide.

This follows almost eight years of hype about NoCs potential with little to show for it. Times have changed and there appear to be two main drivers, one technological and the other business-related. From a technology standpoint, the real key is that chip designs are becoming far too complex to create all the interconnects necessary to get an SoC out the door on time and on budget. From a business perspective, the downturn has cut into staffing of design teams so severely that most companies don’t have the manpower left to develop complex interconnects on a chip that also has multiple cores, multiple power islands, as well as shared busses and memory.

“The key trend that makes such technologies more important is simply the increasing levels of integration, which significantly increase the amount and complexity of the on-chip communication—particularly in the sharing of key resources such as external DRAM,” said Jim Hogan, a venture capitalist familiar with this market. “This complexity permeates every part of the SoC design, from the increasing fraction of circuit delay due to wiring at deeper process nodes up through the massively deeper pipelining required to keep modern DRAMs operating at high efficiency, to the QoS scheduling required to ensure that general purpose software on CPUs can co-exist with real-time communications and multimedia traffic. NoCs provide a structured framework for managing these growing complexities and will therefore become the dominant approach for complex SoCs.”

But structured does not mean standardized. Far from it, in fact. While NoCs fit into standardized EDA flows and work with standards, they are one of the key components that must radically change from design to design.

“At 45nm, and with some designs at 65nm, companies have started to see issues with interconnects” said Charlie Janac, CEO of Arteris. “Projects cost more, they last longer, or they’re being canceled. There’s more problem solving, and the interconnect is more important. When we had single-core chips, it was a choice between a mainframe versus distributed network computing. Now we’re dealing with four to six cores, algorithmic engines, graphics, peripherals and on-chip/off-chip memory. All of this requires more communication on a chip.”

Defining NoC

So what exactly is a NoC? Definitions vary, and likely will evolve as NoCs become both more necessary and more widely deployed. And some of the standard definitions are fuzzy at best. Wikipedia, for example, defines a NoC as “an emerging paradigm for communications within large VLSI systems implemented on a single silicon chip.”

Most chip architects view NoCs as more of an evolutionary step than a radically new concept, though, with the difference being that a NoC is now a discrete part of the development process instead of including it as a piece of something else.

“I like to use the phrase ‘network on chip’ to describe what we do and have been doing for a few years,” said James Aldis, SoC architect at Texas Instruments. “My definition is based around the idea of the NoC being a separate component in the top-level assembly, with a point-to-point interface to each other top-level component. This is distinct from a traditional ‘bus’ where the bus is the top-level assembly. The alternative view is that a NoC is really something with a network-style architecture, where you send out bus requests and responses on the same wires. This alternative view means that the external interfaces of the NoC are not traditional ‘bus-style’ but rather ‘network-style.’ Transactions are captured in packets rather than being represented by separate address, data and command busses. This alternative view is not yet real in the IP industry. You can’t buy IP with this sort of interface on its boundary. It may be used internally in some companies.”

The NoC is particularly attractive at advanced process nodes because of the increasingly complexity and the ability to isolate some of that complexity in the network.

“With the advent of SOCs, a lot of complexity has moved into the interconnect. No one building such chips is really using the old “bus” paradigm anymore,” said Geert Rosseel, senior director at Pixelworks. “The interconnect now has to manage communication between IP blocks having very heterogeneous bandwidth and latency requirements and possibly living on different clock and power domains. The interconnect is now managing CPU-type requests with networking and real-time media (video and audio) traffic, usually all directed to shared resources such as memory. In my opinion, everyone building an SOC is already implementing some kind of complex on-chip communication system.”

But the NoC takes that one step further.

“What sets the concept of a NoC apart is the idea of developing an architecturally clean and unified approach to solving this problem,” Rosseel said. “You put all communication complexity in the network with the IP conforming to some simple interface standard. Once you have this ‘clean’ separation, you can develop an interconnect based on internal protocols that are optimized to meet the performance, area and power requirements.”

Looking forward and backward

The final caveat for most NoCs is that they have to embrace both new and existing technology. That includes a number of existing on-chip protocols, the Open Core Protocol (OCP), ARM’s Advanced extensible Interface (AXI) and AMBA High-Performance Bus (AHB), as well as an alphabet soup of proprietary and lesser-known acronyms.

Ian Mackintosh, chairman of OCP-IP, said the real key is to maintain openness, while embracing existing standards. “The world is heterogeneous,” Mackintosh said. “People have worked up from single bus generators to intelligent networks on chips where you need predictive performance of the NoC.”

OCP-IP has been working on a way to standardize NoC benchmarking to help sort through years of attempts to get this right. For further reading on this subject, check out the white paper entitled: “An Iniative Towards Open Network-on-Chip Benchmarks.”

By Ed Sperling

As with all network topologies, the general rule is the faster the better.

Jack Browne, VP of sales and marketing at Sonics, said his customers are asking for higher-speed interconnects. “Right now we’re at 300MHz,” he said. “They want to more than double that in the very near future and eventually get to 1GHz.”

Getting to that speed is no simple matter, and several approaches are under consideration.

One approach now being tested is a wireless network on a chip. Intel, STMicroelectronics and Philips are all experimenting with these techniques, sources say. And in the commercial NoC space, companies such as Arteris, Sonics, Silistix and Inventure are working on similar technologies.

Parthe Pande, assistant professor at Washington State University, said it’s too early to tell which approach will win. “This is a big research problem,” Pande said. “On-chip wireless networks are very promising. The big problem there is the on-chip antennae and how small you can make them. One approach is carbon nanotubes, but there are manufacturing problems.”

Serialized packets are another approach, but the tradeoff so far has been increased latency. At least part of that is caused by the complexity of designing systems with dedicated wires, shared busses and segmented busses, as well as algorithms that do not take advantage of all the options. Parallelization remains one of the chief conundrums for all levels of chip and software design.

Brad McCredie, an IBM’s chief architect for the Power6 chip, said to understand what’s happening on a chip becomes evident when you look outside the chip because everything is being consolidated into the chip.

“There’s been a lot of research into optical and on-chip optical, but economics never let that happen,” he said. “Whether it happens in the future we don’t know. But between chips, there is a firm direction toward a parallel bus. In cluster configurations we’re seeing packets.”

He said IBM currently is working on 3GHz packet-switch networks on chip for DARPA. But those chips are using parallelized packet switching. The bulk of the work so far has been serialized, and experts say that has created latency issues.

“The main bottleneck right now is parallelizing software,” said Pande. “This is a very hot research topic right now. Packets are another big research problem.”

One approach is to divide the packets into six parts, slimming down the data being sent and avoiding storage of the packets in cache. But Pande said there is still an enormous amount of work to be done, and so far there is no clear winner emerging from the research.

By Ed Sperling

Feb. 4, 2009— Santa Clara, Calif. — Moore’s Law is still alive, but just how well it is depends on your perspective.

Paolo Gargini, Intel’s director of technology strategy, said the good news is that Intel can see its way to remaining on the Moore’s Law road map for at least the next 10 years. The bad news is that it’s going to cost a lot more money to do that—about $9 billion for fabs, $1 billion for technology and another $2 billion for products. And that’s at every new process node.

Speaking at DesignCon, Gargini said Intel is counting on 1 billion users of mobile Internet technology, 100 megabits per second of wireless throughput and 1 billion transistors on the go to turn a profit from that enormous investment. But the number of other companies that can afford to keep pace with their own fabs will continue to shrink.

From a technology standpoint, what will drive those changes are continuous shrinkage in the length of gates, the thickness of the insulation and voltage, as well as strained materials, high k dielectrics, metal gates and a host of new materials. In fact, Gargini said that in the future silicon may simply be the base material on which everything else is built. Intel is in the process of developing new deposition methods and experimenting with new materials and approaches. Those new approaches include nMOS, or n-type metal oxide semiconductor, quantum-field effect transistors (QWFETs), as well as nanowires and nanotubes.

Intel is on track to deliver 32nm chips this year, he said. 

If you think designing a single-core system is hard, designing multicore systems is multiple times harder. Connecting all the pieces together and making them work properly, if not together, is one of the hardest tasks design engineers and architects will ever face.

System-Level Design tracked down some of the experts in this field and sat them down around a table to discuss what’s going on. Included in the discussion were

James Aldis, system on chip architect for Texas Instruments wireless business unit; Charles Janac, president and CEO of Arteris, Drew Wingard, CTO of Sonics, and Dave Gwilt, product manager for ARM interconnect products. What follows are excerpts of that conversation.

SLD: Let’s start with a really basic question. How do you define multicore?

Gwilt: We’ve been doing multiprocessing heterogeneous stuff for a very long time and in many different markets. Multicore is running a single software image across multiple processing elements.

Wingard: That doesn’t match what we see in practical systems.

Aldis: TI has been producing multicore chips for multiple generations now. We split the software into the piece that’s going to run on the RISC and the piece that’s going to run on the DSP and the piece of application processing that’s going to be offloaded onto a hardware accelerator. That’s all a very manual process. When I think of multicore these days I tend to think of what’s coming up in the wireless space where you have a single software image and it’s magically distributed over identical cores on the same device. But multicore means more than that.

Janac: There are a number of people who have tried to do the homogeneous multiprocessor kind of approach—similar to an FPGA. That works in some applications like defense and aerospace and networking, but it doesn’t work in cost-sensitive applications like wireless and consumer. As a result, we wind up with the majority of the market being heterogeneous multiprocessor SoC’s. Those are getting increasingly complex because the wireless carriers are constantly trying to deploy new applications and handset guys are trying to approximate the function of a PC. That’s putting increasing pressure on the hardware.

SLD: What do you actually gain integrating multiple cores, which share memory and busses, versus single-core chips?

Wingard: We’re doing these high levels of integration because we’re trying to get a certain amount of function at the lowest system cost and power and with the right amount of performance. We integrate not because we want to, but because Moore’s Law says we have so many transistors. It’s the job of the system architect to figure out how to make it work. In many cases, the thing that throttles these chips is that they have to share memory, but if you don’t share memory you don’t save costs. The personal computer space is driving DRAM road maps to give us increasing bandwidth per pin. Then we want to put the right amount of processing and bandwidth on the SoC so we can maximize utilization of that extra DRAM bandwidth. Some of this is also driven by form factor. You can’t do a multichip iPhone because there isn’t enough space inside the package.

SLD: Is the heterogeneous approach because each function requires different processing power?

Gwilt: Absolutely.

Janac: I was at a presentation where one gentleman said he was proud that his company was only using 7 percent of the ARM processor and that the rest of the system was running on these proprietary algorithmic engines. I wouldn’t be very proud of that.

SLD: So that’s 7 percent utilization?

Janac: Yes. They should be adding some intelligence that makes use of that resource and reduces the cost. One of the issues is how do you route the traffic to the cores that are available. What is the idle core doing? If it is idle, can you utilize it better?

Wingard: Today, in the battery-powered domains, they’re shutting off regions of the chip and turning off the power supply to several of the cores. If they don’t have anything to do, they’re shutting them off.

Janac: Or they’re putting them in a lower operating mode.

Wingard: All these games get played, but there’s an inefficiency associated with that. If you use heterogeneous cores, you can get better results. Your battery lasts longer. You can get higher performance. And you are much more able to support these multi-mode devices, which are still not general-purpose computers. PCs don’t do it this way because economics demand that you have a single software platform and you can run anything you want to pretty well. Application flexibility is much more limited. That doesn’t mean we don’t see clustered processors like the ARM MP core being useful for these applications. It’s still valuable to span a wider range of performance points by using some number of identical cores that you can schedule software across. ARM can scale an application, and the power associated with running that application, when you play with the voltage and the number of cores that are turned on.

Gwilt: That’s the key—using that to get power scaling across a broader dynamic range.

SLD: Didn’t TI do this with its DaVinci platform?

Aldis: Yes, we did. But there’s another aspect to all of this, too. The more open you make your platform, the more you end up in the PC world that Drew described. One thing we’re seeing in the wireless space with the advent of the iPhone and the mobile Internet devices that are coming through now is an emphasis on getting raw power out of the main processor and software portability. The wireless world, particularly at the high end, is becoming more and more like the PC world. This presents a challenge because just throwing gigahertz at something isn’t going to fly in the wireless world because of the constraints of power and form factor.

SLD: More and more, chip developers are trying to get multiple generations out of chips because of the cost of creating one. Is it harder to do with heterogeneous cores?

Janac: No, that’s where the interconnect comes in. If you have the right structure for the interconnect, you’re actually able to add in and back out IP in a much more cost- and time-efficient manner to get multiple derivatives.

Gwilt: That’s absolutely correct. Nowadays, with the type of interconnect technology that’s available, we’re able to build chips with very large numbers of cores and use the content of the cores that we require. We can choose those cores dynamically and maintain a highly optimized solution.

Wingard: There are some interesting examples where they take a subsystem, and within the context of a platform they implement that function in dedicated hardware or an optimized programmable processor. They get to higher performance and lower power that way. But in other versions of the same platform they move that same function into software. From the perspective of the application, the platform is the same. They’ve put in a layer of middleware that allows them to be agnostic. That makes it much easier to take this common platform definition and build different variants.

SLD: Your definition of interconnect is different than the historical one. This version seems to have logic built into it so you can optimize performance in multiple products.

Wingard: We want to put enough intelligence into the interconnect so that some part of the platform definition relies upon logic within the interconnect. What’s different about each chip is the set of IP cores, but there’s a set of common functions that are part of the platform definition. Some of those functions live within the interconnect—things like how do we enforce security and how do we manage to recover from errors. What scares me most about phones becoming more like computers is I really don’t like getting blue screens when I’m in the middle of a call. We expect stability in our appliances.

Gwilt: That same requirement for stability is also being driven by the need for integration. Our customers all want to pull together very significant platforms in very short periods of time. Having the ability to manage that stability through the interconnect is a valuable function.

Janac: If you use the interconnect to assemble these kinds of platform applications, you also need some automated and sophisticated tools for the design of the interconnect and for verification. It’s a matter of both the IP and the tools that come with it that are required for rapid time to market.

Wingard: The total amount of communication that we have to manage in the interconnect grows with the total number of components that have to be connected. But historically the fraction of the chip that’s dedicated to the interconnect and the main memory controllers has been remarkably constant across a wide variety of applications and design styles. Typically, between 8% and 12% of the die are interconnect and memory system components. As the chips get bigger, this is the part of the system that must change for each design. I can mix and match components, but the interconnect is going to be different every time. It is the most chip-specific IP, even in a platform definition. That’s why the automated tooling for this part of the design is so important.

SLD: But interconnects traditionally have been several steps after the initial architectural design. Has that changed?

Aldis: We’re now in our third generation of SoC platforms where we’ve known what our interconnects are going to look like—maybe not all the dots on the ‘I’s’ and crosses on the ‘T’s’ but we’ve known at a very early stage what we’re going to be using. We also know all the requirements we’re going to put on the different cores in the chip so they can plug into our interconnect environment. Nowadays, when we build a chip the interconnects are enabled before any of the cores. We have legacy cores, of course. But for any new cores, before we have working RTL we have an interconnect. This makes a huge difference between the time it takes to kick off a project and see the test cases running and starting to debug and analyze. We also have a System C model for the interconnect technology we’re using, as well. That’s part of the very initial architectural studies.

Wingard: This has a lot to do with the application domain that’s being targeted.

In those places where you put multiple cores together, you have to worry about the sharing behavior and performance. You quickly get the point that until you have a model of that system and you need to understand the implications of a shared memory and the interconnect that feeds it, you don’t know if you have an architecture that works. For those domains where it’s not, ‘Slap it together and we don’t care about performance,’ you absolutely have to have the interconnect technology and it has to be available very early in the architectural phase of the chip. There are many designers from ASIC background who aren’t used to that.

By John Blyler

Total chip power trends in architectural designs are murky, while economic numbers are crystal clear.

That makes it far more difficult to find meaningful technology trends in these times of economic instability, even though economic numbers can greatly influence chip power trends. Engineers would say that the signal-to-noise ratio (S/N) is just too low, meaning that the signal (useful information) is still there but it’s barely discernible from the noise.

For example, consider the latest total chip power trends that result from pre-silicon, architectural-level investigations. These investigations or trade-off studies will eventually lead to an actual IC project.  Figure 1 below shows which ranges of power (in watts) have been of critical interest to chip architects over the last three years. Up until mid-2008, there was clear interest in chips that had a total power budget of less than 0.11 watts and those between 1 and 4 watts. This latter range coincides with the total power usage of handheld wireless devices, such as mobile phones.

Figure 1

Since the middle of last year, however, it is not as clear which power ranges are of the most interest to the designers of future chip products. For one thing, the number of overall chip investigations – a precursor to actual chip starts – is down considerably. This coincides with the ongoing downturn in the semiconductor industry and overall global economy. This decrease in numbers contributes to the difficulting in reading future trends in total chip power design – at least for the near term.

Economic trends may be somewhat easier to discern, especially if you follow the right metrics. For example, analysts at e-forecasting.com recently said the leading indicators for both chips and chip making equipment fell in November in North America. These indicators are a composite of components that included interest rate spread, productivity measures, changing profit margins and more.

The North American chip sales indicator declined by 2.7 percent in November. (See Figure 2) Not surprisingly, the chip equipment sales indicator declined by 3.5 percent in the same month.

Figure 2

The “murkiness” of lower numerical values for all data types – e.g, all architectural power ranges – means that it is difficult to discern which trends are about to rise about the noise floor. Using sensitivity models designed to clear up this murkiness are one way to see trends more clearly. This will be my strategy going forward.

By Ed Sperling & John Blyler

For all the concern about 45nm chip development—and there have been a number of design investigations at that process node since the beginning of the year—the vast majority of activity is still at 130nm.

This is an indication of just how costly it has become to stay on the Moore’s Law road map—and how many companies have stopped trying to keep up. It’s also an indication of just how much life is left in the older process nodes. Since the beginning of the year, there have been more than 13,000 design investigations—trying out new tools, architectures and processes. Roughly 12 percent of those were at 45nm, with 60 percent at either 90nm or 130nm.

This has multiple implications for the industry, and particularly the fabless development model. While companies such as Broadcom, Qualcomm, Nvidia and AMD continue to live on the bleeding edge of the fabless world, the vast majority of chip developers have adopted strategies that either hang back one or two nodes or skip nodes entirely. Because of the expense of developing new chips, the number of chips that need to be sold to generate a profit has been steadily rising.

Within the foundry business, however, there have been two very distinct models. While companies such as TSMC, UMC and the Common Platform triumvirate of IBM, Samsung and Chartered Semiconductor continue to lead the pack to the next process node, that leadership comes at a very high price. Others, such as China’s SMIC, Israel’s Tower and Malaysia’s Silterra continue to erode their profits several nodes back where volume is significantly higher.

Joanne Itow, managing director for manufacturing at Semico Research, said the number of wafers processed at the leading edge continues to grow. That’s a function of how much volume is necessary to break even at advanced nodes. But Itow said that also translates into more foundry business at the leading edge than there was five years ago. Within that scenario, there also is more competition.

At the same time, she said 130nm remains popular for a variety of reasons: “It can be run with or without copper, on 200mm or 300mm wafers, and there is still a lot of capacity at 130nm. So the price is very competitive and it is not surprising that companies will continue to utilize that technology for a long time. As the price to manufacture declines, we (consumers) benefit from the new electronic applications that emerge. New designs at 130nm are taking advantage of the technology at very good price points.” Apple’s iPhone is only one example of new consumer designs that use 130nm technology.

For capital equipment makers, this isn’t particularly good news. Fewer foundries at the leading edge mean fewer sales. The abandonment of the 200mm fab equipment by memory makers has left a lot of used equipment for sale, said Itow. Big foundries have depreciated their equipment and remain competitive on pricing against second-tier foundries, but the overall effect on capital equipment sales is significant.

This also has implications for the EDA industry, although low-power design starts and a focus on business objectives versus raw performance could pry open a replacement market as well as drive new markets. As expected, the vast majority of design investigations occurred at 100MHz and 50MHz. Low power has become not only a mandate but an opportunity for chip developers, and many companies have begun developing multicore chips that run at lower clock speeds—or are using multiple chips at lower clock speeds.

Systems on chip, in particular, seem to be gaining momentum. Of all design activity, nearly 40 percent of those questioned used at least one block of non-memory IP, and some used more than 30 blocks. That figure is a strong indication of time-to-market pressures and the maturity of the IP industry, as well as an indication of how companies are crafting their chips.

Interestingly, the bulk of the lower clock speeds are being developed at older process nodes, not at the bleeding edge. Speed is still important, but as a selling point power is at least as important, if not more important. In fact, since January there have been only 23 investigations into chips running at clock speeds greater than 3GHz.

By region, most of the design activity occurred in North America. Asia, including Japan, saw only about one-fourth as much activity as North America in 2008. Despite all the startups in China and the preponderance of manufacturing there, the bulk of the design activity remains in North America. Asia was tied with Europe.

By Ed Sperling

The crossover for system on insulator (SOI) versus bulk CMOS was supposed to happen at the 22nm, but that was before software developers ran into problems programming multicore chips.

For years, SOI was considered the high-performance cousin of CMOS—more expensive, more difficult to manufacture and unnecessary for most applications. It is the heart of the Cell processor, for example, which drives Sony’s Playstation 3, the latest versions of digital televisions and some network appliances that need the benefits of always-on active power.

But with the persistent problems of writing general-purpose applications that can scale with multicore processors, SOI is quietly gaining more mainstream appeal. By running either faster or cooler—or both—it can provide the performance gains that multicore chips would provide if the software could take advantage of all the cores.

“SOI does offer a way out,” says Horacio Mendez, executive director of the SOI Consortium. “The big issue is the scalability of bulk CMOS, and there are significant challenges there. When you shrink the transistors, they’re not stable. And with stability comes a power consumption problem.”

The instability is caused in large part by voltage threshold variations. As companies continue down the Moore’s Law road map, short-channel effects (see Fig. 1 below), an increase in parasitic leakage as a result of scaling gate-length dimension and gate oxide leakage all contribute to power dissipation. SOI chips use up to 40% less power due to lower parasitic capacitance, and because they can use higher current they operate at lower voltages.

In practical terms, that means SOI chips can at least keep the number of cores constant and still add performance at each process node. And because they run cooler, they also can use less expensive packages—something that affects when they become economically feasible to use in lower-performance applications.

Short Channel Effects — Source: IBM

Given the advantages, it should come as no surprise that IBM has opened its SOI fab to commercial business at 45nm. Mark Ireland, IBM’s vice president of semiconductor platforms, said SOI is expected to be adopted by the Common Platform group—IBM, Samsung and Chartered Semiconductor—at 32nm.

“What we’re doing now is creating an industry ecosystem,” Ireland said. “From a design standpoint, this is more about education of engineers. At IBM we moved our entire ASIC business to SOI at 45nm. A lot of the hesitation is just about the unknown. But it’s the same design tools and ARM physical IP.”

Opening SOI technology to a broader market also should drop the cost even further, bringing it much closer to parity even at 45nm. But the biggest advantage is still on the software side. While many applications can be threaded to deal with between two and eight cores, far fewer will gain from the addition of more cores. On top of that, very few applications are scalable so they can be written once and recompiled for as many cores as become available.

“Customers already are coming to us looking for higher single-threaded performance,” Ireland said. “Clearly, that legacy market is not going away. Applications will not change overnight. And you do get a performance gain every time you move to the next node, so at 32nm vs. 45nm, there is a performance gain.”

Intel developed a similar technology called TerraHertz in 2000, but so far has done nothing with it commercially. It is one of several possibilities that Intel can tap into at future process nodes, along with its Tri-gate technology. Likewise, IBM has been developing its own tool bag of options, which includes everything from FinFETS to AirGap insulation between structures on a chip.

All of these technologies can be manufactured using existing equipment, and likely will have a significant role in future system development

By Ed Sperling

Santa Clara, CA – User groups are typically good for figuring out the pain points for engineers, but this year’s Mentor Graphics User2User conference was as much about survival skills as it was pain points.

Terry Fox, signal integrity consultant at Terry Fox & Associates, advised engineers working in the high-speed design world to speak in terms that “bean counters can understand.”

“There are two things that bean counters understand,” he said. “Cost and risk. And it’s very dangerous when they think they understand engineering.”

He also said all designs need to leave room for errors in their noise and power budgets and advised engineers that there really are “designs from hell” where nothing will ever work right. One way around that is to make sure that in the pre-layout design review there actually is a layout person. But he said noted that the process must budget enough slack for inaccuracies within that process.

One recurring theme throughout the conference was access to information in a central place. Fox said there needs to be a single location for all critical information in a design. At the board level, Chad Hawkinson, vice president of vertical marketing at PTC, said the missing piece of the puzzle is communication among various engineering groups so that incremental decisions along the way between the MCAD and ECAD teams are effectively communicated.

“The result is less problems toward the end of the process,” he said.

Lack of communication has dogged all aspects of system-level design for years. Cadence’s Open Access database was created in part to create a better method for sharing tools and IP, and partly to improve communication across various groups. That has become particularly important as designs include more software development up front, as various pieces of the entire design become compressed and begin overlapping, and as teams are spread out around the globe.

While all of this is useful information, survival skills may say something about an industry under pressure. It’s no longer just technical information and how-to engineering content, and either the presenters are under pressure or they’re hearing a lot more feedback from engineers about what they’re encountering in the field.

By John Blyler

Chips continue to grow in complexity. This is nothing new. But even at the existing process nodes of 180nm and 130nm, complexity is increasing as designers attempt to squeeze in more feature sets while shrinking the power budget and chip size. This growing complexity, married with the shift to time sensitive consumer product markets has led to an increase in the use of prototypes to verify these chips prior to production.

But what do users really seek in prototyping tools? The report that follows contains the summary and analysis of a survey conducted with more than 270 qualified respondents in the ASIC and related markets. The results track well with similar surveys in this space, but the details present some surprising implications.

Application Markets

Most responders listed the communication market as their primary product area, followed closely by the Consumer, Computer and Other markets (see Figure 1). Most prevalent “Other” markets were Industrial, followed Mil/Aero, Automotive and Medical.

Figure 1

In the category of communications, most respondents listed wireless handsets and wireless and wired networking as their chief application areas, followed closely by wireless base station design, telephony/VOIP and wireless Metro Area Networks (MANs). A small percent listed research, remote controllers, CDMA networks, fixed networks, telemetry and military as other areas of focus within communication category.

In the consumer market most respondents list multimedia designs – involving both video and audio subsystem – as their primary area for developing ASIC prototypes. Multimedia design concerns will be reflected proportionately in other parts of this survey, i.e., processor types, interfaces, etc. Interestingly, several designers listed games as their chief concern. That’s a trend we will watch in future surveys.

Computer design issues were most closely tied to peripherals such as storage, printers and the like. PC and workstation systems came next, with others including prototyping systems, servers, data acquisition modules, and instrumentation and software/firmware design issues.

Job Function

Most of the respondents identified themselves as ASIC or ASSP designers, followed by engineering management, corporate management, verification engineers, system architects and software designers. A small percent of users listed their function as applications engineers, business development, academia and sales/marketing.

Figure 2

ASIC/ASSP/SOC Design Details

When asked to describe their current ASIC/ASSP/SoC design, more than half of the respondents indicated a design size of less than 5M gates, with that majority below 2M gates.

In terms of memory, most designers focus on SRAM memory, suggesting the strength of on-chip memory prototyping. Still, DDR and Flash memory account for about 22% each of memory usages.

Embedded processors usage is led by the MIPS processor, which matches up with the respondents’ applications markets. ARM, Tensilica and Intel comprised roughly 16% each of the remaining usage. Other processors used for ASIC prototyping ran the gamut from microcontrollers like the 8051, Microchip’s PIC and Xilinc’s MicroBlaze to proprietary cores. A large number of DSP cores also were cited, including Ceva Teak Lite, TI and in-house multimedia DSPs.

To the question concerning the types of external interfaces used in ASIC prototyping projects, the top three busses were PCI, USB and Ethernet. SPI, SATA, XAUI and HDMI finish up the lower quadrant. Though not listed in the survey, questions have arisen about the use of the PC-104 bus. Several experts believe PCI Express represents the path forward for PC-104. This projected growth will be the subject of a future survey.

The majority of users listed Serial RapidIO (sRIO) as the main external bus of choice under the “other interface” category. This is no surprise, since the sRIO interface is commonly used to connect multiprocessor designs, especially for DSPs. This tracks well with the use of DSPs highlight in the “Processor” usage category cited earlier. Other interfaces include I2C – a low-speed serial bus used to attached peripherals to a motherboard, embedded system, or cellphone; DVI, RS-232, parallel bus, CAN – automotive bus, DigRF – digital serial interface for 3G air standards; and even UART.

Re-spins

A little over half of the respondents indicated their previous design project required no re-spin. Of those acknowledging re-spins were necessary, 50 percent stated that only one re-spin was needed. About half as many reported by two re-spins were required and slightly less than 10 percent admitted to three re-spins.

The main reason for chip re-spins was the presence of logical and functional errors. This result tracks well with other recent studies that indicate more than 60 percent of re-spun ASICs fail due to logical/functional errors, not because of timing or power issues. This means that functional verification is now the most critical phase of the chip development cycle.

Figure 3

Verification Environments

When asked what type of verification was used for a current project and planned for future work, the largest groups of respondents selected Mentor’s ModelSim/Questa. This was followed by Cadence NC Simulator and Synopsys VCS.

Figure 4

Other software simulation environments consisted of tools from IBM, Altera’s QuartusII and Xilinx’s ISE, Synplicity’s Synplify, Dolphin’s SMASH and Catena’s Analog and Mixed Signal (AMS) Simulators, Aldec’s Active-HDL Simulator and homegrown systems.

In terms of emulators, most users listed Cadence systems, followed by Mentor and Eve. An interesting side note is that only Eve emulators saw a planned increase for future projects. Formal verification favorite was Formality, followed distantly by OneSpin, Real Intent and Certess. System Verilog lead the way in Assertion-based tools, followed by OVL and PSL.

Here’s where the results get interesting. When asked what type of virtual prototyping environments were currently being used, ARM was the favorite – but by a decreasing margin for future projects. Synopsys’s Virtio was the second most popular choice, showing projected growth along with CoWare, VaST and Virtutech. One should exercise caution when interpreting these results, since the slower pace in usage of ARM tools may simply reflect the growth of virtual prototypes in non-telecom related industries.

Figure 5

Looking at the other end of the prototyping spectrum revealed that Synplicity was used more often for ASIC prototyping with FGPA-based systems – at least in the market areas highlighted by this study. ProDesign followed second, then came Dini and Gidel. It must be noted, however, that 36 percent of respondents still used custom-built FPGA-based prototyping, though the percentage was on the decline for future projects. This marked decrease in custom-built systems may attest to the growing complexity of ASIC designs and hence the corresponding complexity of FPGA prototypes.

Conclusions

This survey points to the changing dynamics in ASIC prototyping tools and methodologies. Prototyping of specific blocks on an ASIC core now seems mandatory, especially since ASICs continue to increase in design complexity. This complexity is manifested by an increase in logical and functional errors in the chips, which has resulted in a need for more complete verification tools and methodologies.

But prototyping itself has taken on a new dimension with the advent of virtual prototypes – used more often by software designers – and FPGA-based prototypes used by chip hardware engineers.

These trends have been confirmed by other studies. For example, Aberdeen’s “Best in Class” study cites verification as one of the most prevalent concerns in chip companies. Chip Design Trends reports, which tracks ASIC pre-silicon architectural trends, confirms the growing complexity of ASIC chips – at all levels of design metrics. Contrasting this complexity with the continued decrease in ASIC starts suggest that ASICs may be getting larger in size though less numerous in unique projects. All of these trends support the growth of prototyping as a key element in future chip designs.

On the business side of the equation, one should note the shift away from corporate electronic expenditures to the rapid increase in consumer’s consumption of electronic products. The consumer world is outpacing the corporate world in the purchase of electronic goods, but there is a caveat: Consumer electronics have a shorter time to market, high product volume but lower cost per unit that corporate electronics. What does this mean to chip designer? It means that they must find a way to reduce ASIC re-spins, such as with ASIC prototyping.

The rising copper prices are leading some companies to re-examine aluminum, particularly for price-sensitive commodity products at older process nodes.

Copper interconnects, which completely changed design at 130nm—along with a shift to 300mm wafers and low-k dielectric insulation—are getting a second look. In fact, they’re actually being used in some chips at 110 nm and larger.

The reason is the cost, say industry sources. When copper interconnects were first under consideration in the late 1990s, copper sold for less than $1 a pound. The price peaked at $4 a pound this summer, before retreating to the current $3.25. But no matter how you cut it, that’s a significant price hike.

Aluminum isn’t free of significant price increases, either, although it’s not rising as quickly. A story by TimesOnline said that aluminum prices are expected to increase by about a third in the next couple years, in large part because the cost of running aluminum smelting plants is skyrocketing. That would increase the price to about $4,000 a ton, compared with $6,000 to $8,000 a ton for copper over the past few months.

While it’s true that chips require very small quantities of either copper or aluminum, in volume the numbers can mean the difference between a vendor winning a contract or losing it to a lower-priced competitor.

Copper will continue to be used in the most advanced chips, and road maps from the Common Platform, Intel and TSMC all show copper interconnects in future generations of chips. But in commodity applications, particularly those running at older process nodes, every penny counts.

“Some applications do not need to go to advanced geometries,” said an industry source. “These are particularly cost-sensitive applications. You will see aluminum interconnects at 110 nm and 130 nm become qualified for automotive applications in the near future.”

–Ed Sperling