By Ed Sperling

Synopsys is teaming up with Imec, the Belgian research lab, to help solve the problems of 3D IC stacking and through-silicon vias. This is important stuff for re-use of older technologies, not to mention cutting verification time and achieving timing closure and getting chips to market on time and improving yield and…well, you get the idea. Synopsys also added design-rules-driven technology to Galaxy Custom Designer that helps speed DRC repair tasks.

Mentor Graphics added Amba 4 verification IP to its Questa library. Given the growing popularity of ARM’s processor, this is a necessary step—especially with Mentor’s commitment to the Android phone.

Actel got its first public endorsement of its new SmartFusion chip. Micrium is porting its embedded software stack to the mixed-signal FPGA. Micrium’s software is targeted at the ARM Cortex-M processor line.

TSMC sales were up 0.1% from January to February, which isn’t much. But when you consider that’s 144% higher than last year it starts putting things in perspective. Still, it would be nice to have a breakdown by process nodes.

By Ed Sperling

Every now and then a new trend comes along in the semiconductor design world, often because an old tool doesn’t work well anymore or because a new one is achieving critical mass. Lithography moved to immersion when the wavelength couldn’t be refracted far enough anymore. Designers at the advanced end of Moore’s Law began using tools like high-level synthesis and Transaction-Level Modeling 2.0 to help sort out the complexities of multicore, multi-voltage, multi-power island designs.

What’s changing at 32nm and beyond is the number of different directions the industry is heading. In the past, each new node brought new changes. At 130nm, the changes were considered extremely difficult because manufacturing moved from 200mm to 300mm wafers, added copper interconnects and low-k dielectrics for insulation. Most developers and chipmakers heaved a sigh of relief when that transition was over. But in retrospect, that was relatively tame.

Interviews with dozens of engineers, vendors, scientists, researchers and business managers over the past six months show that what’s ahead cannot be bounded into just one or two shifts. The change under way now is geographically global. It’s moving to a higher and higher level of abstraction, from semiconductor to system to device. And it is as much driven by business as technology. Moreover, taken in total these changes will completely alter the basic fabric of the design community in ways that have never been seen before.

Business
Behind many of the changes afoot in the market there is always a business case. In the past, technology trumped business. Those with steely nerve and enough backing could often carve out a space for themselves in markets, and even if they weren’t entirely successful they could minimize their losses.

Three things changed over the past decade to alter this approach. Business now trumps technology in almost all cases. First, the venture community has grown more cautious about the rate of return in hardware and EDA tools ever since the dot-com bubble burst in 2001. It’s not possible to return to the tap anymore without a real product and a real business model.

Second, the cost of failure has gone up. It now costs $4 billion to $5 billion to build a state-of-the-art fab. Consortiums of very large companies and governments are now involved in this business. And it can cost upwards of $100 million to build a very complex SoC at the latest process node. Stalwart adherents to Moore’s Law such as Freescale, which made the leap to the next process node without hesitation until 90nm, have begun skipping nodes on certain products.

Third, chips are now so complicated that it takes too long to build everything from scratch. That means chipmakers must buy IP from third parties. Even Intel doesn’t make everything itself anymore. And all but a very few companies now use a fabless or fab-lite model for at least the digital portion of their chips, which forces them to adhere to design rules and process technology developed by the foundries.

Put these together and the result is that business issues are forcing a handoff of some of the most basic parts of semiconductor engineering—defining a unique architecture, tinkering with the layout, refining the process, and balancing all of these pieces together at tape-out. Fast yield, time to market and standardized interconnects and IP are no longer just goals. They are requirements. Some companies have handed off the building of chips entirely to a new class of value-chain producers like eSilicon, Global Unichip and Open-Silicon.

Globalization
For the first 50 years of its existence, the semiconductor industry defined global as North America, Europe and Japan. Taiwan was a latecomer to the part, and TSMC’s vision of a foundry model was considered revolutionary well into the 1990s. Companies like Texas Instruments and AMD said they had no intention of letting go of their own fabs.

Fast forward through two downturns and 10 process nodes and the situation now looks much different. Software is increasingly a part of the design process, heavily automated foundries can be located anywhere in the world where tax breaks and the cost of power are lowest, and massive education programs are under way in multiple countries that see semiconductor and computer engineering as a fast way to economic health.

While many lament that the semiconductor industry is declining or not showing growth, the opposite is happening. It’s expanding significantly. In 1977, the Semiconductor Industry Association reported total semiconductor sales of $2.88 billion, with about $1.92 billion of that in the Americas and only $182 million in Asia/Pacific (not including Japan). In the first 11 months of 2009, sales were $196 billion worldwide, with $102 billion in Asia/Pacific and $33 billion in the Americas.

By any standard this represents an enormous increase in sales, but the profits are now far more dispersed around the globe. Moreover, IP for chips is being developed in places like Eastern Europe and former Soviet republics, and in the future that kind of work will accelerate in other parts of the world because the barrier to entry into this market is one of the lowest—you don’t need to build full systems—while the return on investment is one of the highest. Virage Logic, ARM and Synopsys have been snapping up these kinds of operations around the globe over the past couple years.

Technology
Most of these changes are being driven by the technology itself. There are fewer design starts for ASICs these days, but the problems being solved are far more numerous on each chip than in the past. The tradeoffs of area, power and performance have been relatively balanced over decades of development. When lithography became an issue, there was enough slack in power and performance to tide chip designers over until the next node.

At 90nm that began to change. Classical scaling ended, lithography stalled at 193nm, defect density increased as irregularities in silicon and process technology became evident. Power forced even companies like Intel to begin adding more cores onto a chip rather than continuing to turn up the clock speed, creating problems about what to do with more and more cores.

At 22/20 nm—the next node for companies that live on the edge of Moore’s Law—things get even more interesting. Both Synopsys and Mentor Graphics predict that FinFETS will start showing up on chips—3D transistor structures that will wreak havoc on parasitic extraction because of the amount of data that will now need to be analyzed and synthesized. IBM has talked about potentially reducing the functionality on chips at future nodes to be able to get chips out the door that fit into the power budget.

All major chip companies are now looking at heterogeneous cores instead of homogeneous cores and matching software and core size for a specific function. IBM and Mentor are experimenting with computational scaling to compensate for the limits of 193nm lithography. And power techniques that used to be considered exotic and extraneous are suddenly becoming necessary.

Even substrates are changing. Intel, which examined and then rejected partially depleted silicon on insulator (SOI) is looking seriously at fully depleted SOI for future nodes. And work is under way to sidestep much of this entirely with 3D stacking of chips, which have many problems such as heat dissipation and parasitic issues still not fully understood.

Abstraction
Perhaps even more daunting in this whole process is a complete shift in control within the design flow. The number of computations necessary at advanced nodes, coupled with business pressures and time to market issues are forcing engineers to rely on models. For many, this is like black-box technology. You put requirements in one side and the software adds a lot of the things in between.

For engineers who learned to solve problems the hard way–that is, without software models–this is perhaps the toughest change of all. RTL engineers who work at big chipmakers say there is enough work at the moment to stick with their core competencies. The problem is the amount of data they are dealing with is going up, and over the next few years it will skyrocket into the stratosphere.

Japan has been particularly accepting of tools like TLM 2.0, high-level synthesis from companies like Mentor, Forte Design Systems and Synopsys, and network-on-chip technology from companies like Arteris and Sonics. The acceptance level in Europe is lower, and it has been lower still in North America. But that is likely to change at future process nodes as business pressures take root, something that is already becoming evident with the rapid proliferation of DFM tools and automated test suites.

Tools vendors characterize these changes as a shift from design engineer to systems engineer. But there’s far more to it than that. In the future, a systems architect will have to understand how the software will behave in the system they’re designing and how all pieces of the verification can be matched to the progress in the design. The next phase of systems engineering will be concurrency in multiple pieces of the design, with real-time feedback across the flow to make a series of modifications and more modifications until tape-out.

This is already evident in the number of tools players around the fringes that are trying to solve unusual problems–companies like Atrenta, Jasper, Oasys, CoWare, and a slew of others that have made inroads and will continue to make inroads.

Conclusion
Taken as a whole, the confluence of a variety of factors ranging from technology to tools to business is coming to a head. Each node from here gets tougher not because one problem has to be solved, but because more and more problems have to be solved simultaneously at each successive node.

Moore’s Law will continue, but not in the form in which it was originally conceived. A FinFET is not a classic transistor, and 3D stacking moves things into a different plane. Moreover, the tools to create these new devices will continue to change, the way they are manufactured will change, and the skills necessary to create these structures will change.

Perhaps even more important, all of these changes will begin showing up over the next couple of process nodes. We are all living and working in interesting times, but whether it’s a blessing or a curse may depend on each engineer’s role, their training, their ability to accept change and possibly even where they’re located

By Ed Sperling

The new year is off to a gallop, which either means the economy is recovering or everyone took the holidays off and now they’re playing catch-up.

There were a barrage of press releases over the past week. While individually they look like the usual marketing, collectively they tell a different story—and probably the first really positive one since the downturn hit. Business is up, design activity is up, and executives are back to pitching financial success to Wall Street.

Virage Logic signed a partnership deal with eSilicon to become an IP partner in eSilicon’s value chain. Virage also inked a deal to provide its Sonic Focus software on IDT’s codecs for PCs. and another deal to license its ARC processor cores to Phison, which makes USB drives and memory controllers.

Canon is migrating its India Design Centre to OVM and is using Mentor’s Questa verification platform. Business is healthy in Asia.

Top execs are back on the road again doing more than just sales calls, too. CEOs from Synopsys (Aart de Geus) and Actel (John East) will be presenting at the Needham conference in New York next week.

And electronics companies began talking up the products that are running their latest technology at CES. ARM is showcasing its Cortex-A9 processor in an NXP set-top box  while MIPS is showcasing its cores in set-top boxes running Android.

Even jobs are beginning to return to the market, according to job boards. Some of this work is still on a consulting basis, but it’s at least a first step toward a broader recovery. Welcome to 2010.

By Ed Sperling

Virage Logic wasted no time in putting its ARC acquisition to work. As soon as the ink dried for the deal, Virage opened fire on ARM. Virage’s new 32-bit processor core, aka the ARC 601, is aimed squarely at ARM’s Cortex M0 microcontroller. With the lines already blurred between microprocessors and microcontrollers this should prove to be an interesting slugfest. What’s especially interesting about this new ARC core is that it’s the same size as an 8-bit microcontroller.

At least ARM is getting a reprieve from Intel’s laser-like focus. With the Federal Trade Commission hammering Intel, this time for including graphics on its processors, the company is facing battles on all fronts—Europe, Korea, Japan and now the United States, it has to be a major distraction. How many other big markets are there? Intel did take the unusual step of responding to the FTC with a statement. It said the FTC jumped the gun and filed before it knew the facts.

Meanwhile, the other half of the dynamic duo, Microsoft, settled its dispute with the EU. Microsoft will now offer multiple browsers to customers. Does anyone still care about which browser gets used? A more pertinent question is whether they can take advantage of more than one core for searches and video playback.

Mentor Graphics achieved IPv6 phase II compliance for its Nucleus operating system. IPv4 is predicted to run out of address space in 2010, which happily was never mentioned in the Mayan calendar. Still, this is a good move for Mentor. We’re taking odds on whether there will be some hiccups in the transition of the Internet, though.

X-Fab, a major analog/mixed signal foundry in Germany, is backing Synopsys’ Galaxy custom installation solution. Analog and mixed signal continues to be a slow and tedious process, in part because analog engineers don’t put a lot of trust in automated tools. Anyone trying to push tools into this market needs a lot of patience and staying power.

TSMC introduced process technology for LED driver devices. This stuff goes all the way back to .6 micron, which is 600nm and as far forward as 180nm. Guess they found a good use for all that fully depreciated equipment.

Chartered Semi, meanwhile, won two investor relations awards in Asia. This is interesting because Chartered has been dead silent since early September, when Abu Dhabi’s ATIC offered to buy the company.

By Pallab Chatterjee

The high cost of SoC development at advanced process nodes is forcing a significant shift in many of the methodologies used in design.

Hierarchical design methods are giving way to IP integration and hierarchical analysis at the architectural and functional design levels. Previously, large blocks were implemented at the top level of the chip and the analysis was pushed off until these top blocks were done and the chip was checked as a whole. The rising complexity of today’s designs and the ability to interpret results from current EDA tools cannot sustain this approach.

This shift in design tasks has been a major point of discussion at a number of recent industry events. The focal point of integration and analysis was presented formally for discussion by Jim Hogan and Paul McLellan at the recent ICCAD conference, and was amplified through the rest of the ICCAD conference as well as at ARM’s Techcon3, the MEMS Executive Congress and the Low Power Workshop. While the main context of the discussion by Hogan and McLellan was EDA business models and the location of the rapidly dissolving profit margins and value in the design flow, the technical conferences presented panels and papers exemplifying the new focal point and methodology.

The role of the integration phase has pretty much been unchanged since the start of IC design. It is separated into three levels: component/device design, IP/block design and architectural/system design integration. While the breadth of the work at these levels has grown and now includes level-specific analysis, the overall scope of the levels remains fairly unchanged over the past 30 years. The component/device design activity has shifted from being a common task performed by all semiconductor companies to a specialized task performed by just a small portion of the supply chain and specialty semiconductor firms.

The MEMS and Low Power events focused on the base process technology and new application device areas. Both areas, which are currently undergoing double-digit revenue growth, are focused on traditional component-level design and process per device functional performance optimization. The MEMS and low power marketplaces have joined standard product memories and largely shifted out of the modern design ecosystem, requiring them to use the old “IDM style” design flow. Due to a lack of transportable and standard design tools, these markets create custom devices, IP blocks and then final full designs on in-house flows for in-house standard product chips.

There is no functional multi-company IP market in these channels. The primary analysis tools are at the mathematical, mechanical and physics levels rather than transportable in high-level languages. The analysis also is very company- and function-specific rather than standards-based.

Following this trend, the fabs and IDMs that are still in the primitive device creation market have been focusing on creation of customized software tools to support integration and analysis. ICCAD had several papers on NBTI (negative bias temperature instability), SEE (single event error), thermal issues, yield and reliability tools and models created by these device manufacturers to perform fab-line specific-use analysis. These are not general-purpose tools with large target audiences. Instead, they are being created by the fabs and IDMs, in conjunction with the universities, for internal use.

At the ARM event, ARM was the primary transistor-level provider of design knowledge for sub-90nm processes, surrounded by an ecosystem that includes a large number of design partners who could use these transistor-level elements as function blocks. Among them are IP and software companies targeting the next level of hierarchical major design activity, which includes analyzing and optimizing these IP blocks. Correspondingly, the technical sessions were no longer focused on the creation and use of the IP in a technology node, but on the integration and interoperability of the IP blocks to implement functions.

Follow the money
The biggest shift in the design trend is that most of the integration and analysis is solely a hardware task, even though the largest development portion for an SOC is the application software. This effort is currently both the largest segment of the development cost and the largest manpower allocation on a project. The software is implemented at multiple levels from microcode to control in-hardware state machines and embedded processors/controllers to standard interface control firmware (such as for DDR3 memory control) to higher-level code such as ECC, operating systems, GUIs, and in-system applications.

The software requires co-verification and iteration of the logic hardware, possibly the IP selected and the software/firmware. This activity is now performed in high-level languages, which are typically many orders of abstraction above the mathematics and physics level issues of the manufacturing process. As a result, there are many traps for the creation of high-level SoC systems that are physically realizable and yieldable.

The biggest challenges facing cost-effective yield in new SOC designs aren’t necessarily the lithographic process or the actual wafer fab. More important is that the designs are being created at high levels of abstraction without regard for the realities of having sub-wavelength active transistors that need to be manufactured in high volume. The systems designers have been hiding behind the “comfort” of the ESL and high-level EDA tools, and have lost touch with the devices that make up the functions. As a result, there is little regard or respect for the concept of a single chip with billions of devices on it, all of which have to work as planned.

Engineers at the conferences say a lot of the issues are due to the commercial EDA vendors making SoC tools having spent literally decades away from the semiconductor manufacturing and device R&D floor, and creating solutions that produce algorithmically and mathematically valid solutions that also are physically unrealistic and which cannot be implemented. As the vendors do not have a good feel for the validity of solution, so go the solutions from their tools not being valid from an engineering perspective. An example of this gap in understanding is the creation of hardware logic solutions with firmware control, which return a fatal error rate in the 1 part per millions region. Given an optimistic perspective that these errors occur in the 1 part per 100 million range, a 1 billion-plus transistor device would then have more than 10 fatal errors in the design.

The knowledge base of creation, integration and verification will need to be re-unified to address this issue. Only then can the industry reverse the point tool segregation of the problem that has been promoted by the EDA industry for the past 20 years so that modern SoC design once again will not be the domain of just a few semiconductor companies.

By Geoffrey James

Intellectual property was once seen as the new growth market for EDA. Dozens of firms – large and small – jumped on the IP bandwagon, attracted to the “build once, sell many times” business model.

“As late as 2004, the industry was still thinking that as much as 90% of SoCs would be reused IP,” said EDA consultant Gary Smith.

The IP segment, however, hasn’t proven to be a profitability panacea, especially for smaller firms. There are the big players—Synopsys and Mentor in the EDA world, ARM and MIPS on the processor side, and Virage Logic in a variety of markets, which has broadened recently with the acquisition of ARC and NXP’s IP portfolio. There also are players like Rambus and Denali that have staked out strong market presence. For most other companies, though, IP has been more troubling than it has been worth, as evidenced by the continued consolidation in this sector.

For one thing, IP never achieved the promised level of penetration. Reusable blocks comprise only a little more than two-thirds of today’s typical SoC, according to Smith. Perhaps as a result, since 2007, IP revenue has stalled at or around 20% of total EDA market. (See figure 1.)

Source: EDAC

But there have been other problems as well, especially for smaller firms. Far from an easy way to make money, IP has become one of the most harrowing segments of the EDA market, with five major financial and technical challenges:

CHALLENGE #1: New IP always requires customization.
Back when IP first became big business, state-of-the-art circuitry was around 180nm. At those geometries, IP was pretty much plug and play. If a block of RTL did something on one chip, it would do the same thing on another chip. While the overall chip had to use the block correctly, there wasn’t much else that could go wrong. It didn’t matter what foundry made the chip, nor what other kinds of circuits were in the general vicinity of that particular block of IP.

That all changed at around 90nm. Suddenly, a circuit that worked perfectly on one chip would go all catawampus on another, simply because of leakage from surrounding circuitry. Even the same chip manufactured at different foundries might end up with wildly different yields, due to the peculiarities of the individual processes. As a result, IP, if it’s complicated or if it’s targeted for the smallest geometries, stops looking “plug and play” and starts looking like custom design work.

This screws up the “build once, sell many times” business model, says Smith. “Design firms selling state-of-the-art IP often find themselves spending more time tuning the blocks for specific designs than creating new IP to sell,” he says. In order to survive, smaller IP firms must extract revenue from the customization, rather than from the IP license. Unfortunately, this ties up their most precious resource—top engineering talent—thereby limiting their ability to continue to innovate.

CHALLENGE #2: New IP has a short market window.
Once a certain type of IP is well-understood and has been qualified for multiple manufacturing processes, it does begin to approach the plug-and-play status that would make “build once, sell many times” workable. However, once the IP reaches that state, it’s generally no longer unique enough to command a premium price. Instead, there will be multiple plug-and-play approaches to solving that problem. The IP becomes a commodity, making it more difficult to recoup the development expense.

For example, when USB 2.0 first came out, the IP to make it work commanded a premium license fee. However, once USB 2.0 had gone into enough designs, the problems making it work with different processes were largely solved and easily imitated. Because of that, chip designers can choose from a number of different versions of USB 2.0 IP and since none of them are noticeably better than the other, semiconductor firm are likely to pick the cheapest.

That’s probably OK, if you’re selling a knockoff. But if you invested a lot of time and money to come up with the first version, and then qualify it on multiple processes, you have a very limited amount of time to obtain the kind of high license fee that would provide a good return on that development investment, according to Richard Wawrzyniak, ASIC and SoC senior market analyst at Semico.

“The IP world is driven by your ability to differentiate your customer’s product,” he says. “If you can’t provide that differentiation, then your IP has limited value.”

CHALLENGE #3: IP Litigation can get expensive.
With chip designs costing more money every year, it’s not surprising that many semiconductor firms are outsourcing designs to India and China, where engineers are plentiful and cheap. Unfortunately, China (and to a lesser extent India) has an abysmal record of protecting high tech IP. “The entire idea of intellectual property is alien to Chinese culture; China didn’t even have patent laws until 1990,” explains Usha Haley, a business school professor at the University of New Haven and author of Asia’s Tao of Business: the Logic of Chinese Business Strategy (Wiley, 2004).

Unfortunately for their profitability, IP firms can find themselves involved in legal hassles related to the unauthorized use of their IP. That’s just a cost of doing business for large IP firms. Smaller IP firms, however, simply can’t afford that expense, according to Charlie Cheng, CEO of Kilopass, a company that holds IP patents for non-volatile memory. “Our only defense is to keep innovating so that people will keep doing business with us rather than stealing our IP,” he explains.

CHALLENGE #4: Semiconductor firms want to manage their risks.
Many semiconductor firms look a bit askance at IP because it makes them dependent upon the IP supplier. If something goes wrong with the IP during, say, verification or manufacturing, the IP supplier might not be willing (or able) to drop everything and run to fix the problem. And if the semiconductor firm hopes to move a chip design to a newer node, the IP supplier may need to get re-involved and possibly retrained on the design rules for a new process.

Under the circumstances, many semiconductor firms prefer to develop as much as possible of their circuitry in-house, so that they have control over development priorities if a problem occurs. Many firms only turn to IP when they lack the expertise to develop an in-house product. CPU IP is a case in point, according to Art Swift, vice president of marketing at MIPS. “We’ve been working on the RISC computing concept for decades, which has created a vast experience base and intellectual process that would be difficult, if not impossible to reproduce elsewhere,” he explains.

In other words, smaller IP suppliers entail risk that some semiconductor firms aren’t willing to suffer, according to George Zimmerman, chief technical officer at Solarflare, a company that makes 10 Gigabit Ethernet chips and controllers. “Going with a larger firm offers more risk mitigation,” he says. “We’ll only work with a smaller IP firm when what we need is highly specialized and can offer a substantial performance advantage.”

CHALLENGE #5: IP design favors economies of scale.
In contrast to their smaller brethren, the larger IP vendors have more resources to apply to making sure the IP behaves as expected. Synopsys is a case in point. “We have about 700 people working in our IP group who focus on adapting IP to run on different process nodes and for different customers,” says John Koeter, the company’s vice president of marketing for the solutions group. This massive application of manpower allows Synopsys to achieve the “build once, sell many times” business model.

Smaller firms, however, lack the economies of scale to imitate Synopsys’s success. Instead, they’re forced to marshal whatever resources they can to help a handful of customers, most of whom will require a significant amount of custom work. And while that still is revenue, it’s not as easy as getting a check every month for your IP licenses.

This is not to say that smaller firms can’t make money in chip IP, according to Smith. “The ones doing OK are making analog content because analog is difficult and there aren’t analog engineers available to be hired,” he says. But the idea that IP could be a short cut to big money for small firms remains a dream unfulfilled. “The reality is that it’s just not as easy as it looks to make money in this business,” Koeter says.

The barrier to entry also has escalated well beyond what it was at 130nm or even 90nm. The companies looking for IP typically are at the leading edge of design, which means the IP has to be qualified and tested for that process node.

“Prior to 45nm, there was no IP ready before silicon, said Brani Buric, vice president of marketing and strategic foundry relationships at Virage Logic. “Now you have to design complicated technology for SoCs, test it and verify it. So the skill level required on a scale of 1 to 10 went from 3 to 20. It’s tough to be a small player in this market.”

By Wang Xiaodan

Strength, vision and perseverance are a must for all the enterprises that have successfully carried out university programs. That ranges from equipment donations, university competitions and joint laboratories all the way to teaching material support, R&D funds, and students’ practical training. And all of this requires not only money, but also the integration of resources of the enterprise itself for target institutions, industrial chain partners and government departments.

In this sense, university programs have become a long-term strategy for enterprises. There are hardly any results for short-term operations, performance is difficult to assess, and a lot of enterprise resources are involved.

Interestingly, those enterprises that have their own “research institutes” are loyal practitioners of university programs. In general, internal research institutes have projects that last for three to seven years, allowing them to carefully plan their university programs and develop the deep connection necessary between the university programs and their own future. These enterprises include Intel, IBM, Microsoft and Google, among others.

The reason is simple: They have established their present position, and are willing to lay out the future. Just consider that an entire generation of young Chinese students may become your potential customers, potential buyers, potential partners and even the future policy-makers. And even without any direct business connections, they will have favorable impressions on your brands.

Intel is a good example of how a company is building loyalty in China, and its approach involves several steps. The first includes teachers. Through course collaboration and teacher training, Intel has established cooperation with more than 100 universities. Take the multicore university program as an example. Intel first invited teachers from five domestic universities to develop courses and opened its first teacher training class in 2006. So far, the company has held 11 teacher training classes, and trained 400 front-line teachers, who have cultivated nearly 20,000 students afterwards. Three courses on the multicore technology have become state-level high-quality courses.

The second step involves students in the form of student competitions, scholarships and enterprise internships. For example, Intel sponsors the National Embedded System Design Competition and the National Multicore Technology Programming Competition, introduced the “Intel Scholarship” program, and cooperated with the Ministry of Education in the founding of Intel Internship Base. This base, located in Intel Asia-Pacific R&D Center, Zizhu Science-Based Industrial Park of Shanghai, has received 600 students for exercitation. All students are assigned with mentors, and participate in the R&D process just as full-time staff.

Meanwhile, in order to coordinate with Intel’s deep embedded strategy, one general-purpose university textbook based on the examples of the x86 architecture and Atom processor will be promoted in Chinese educational institutions next year. This is how Intel intends to weaken ARM’s grip on the Chinese electronics market. Presently, Chinese students majoring in electrical engineering learn and use ARM processors and tools, and regard their embedded design skills based on ARM’s architecture as a stepping stone for the job interview. In this regard, Julia Zhu, Education Manager of Intel China Ltd, said, as long as Atom’s technology and platform are open, Intel will still have winning chance in the competition.

“Teachers are familiar with the x86 architecture, and students have been learning the Principles of Microcomputers based on x86 architecture. The problem is that this textbook is outdated,” she said, “Therefore, by leveraging Atom’s new technology and platform we can help institutions to complete the curriculum reform and continuously provide teachers with better and newer technology and equipment support. In this case, we also have advantages our competitors do not have.”

Jun Ge, executive director of Intel China Ltd. in charge of external cooperation, noted that Intel has a China Strategy Office that specializes in what products Intel should launch in China in 10 to 15 years. With such a long-term outlook, Intel certainly needs to cultivate its Chinese fans over the next 10 to 15 years, which is the goal of Intel’s University Program Planning Department.

EEFocus is the Chinese media partner of System-Level Design.

By Ed Sperling

The world is still full of engineers who can build fast interconnects to things like PCI Express or USB 2.0 who can create complex schematics for determining the connections between a processor core, memory, logic and various IP blocks on a piece of silicon. But over the next several years, many of those engineers will have to figure out new ways to make a living.

The number of companies that are jumping into pre-configured interconnect strategies—either through existing bus structures such as AMBA or the emerging network on chip approach—is growing rapidly. This is the latest trend in the disaggregation of the supply chain for systems on chip, using pre-configured approaches or high-level flexibility to plug in third-part components instead of developing everything in-house.

There are several reasons these approaches are gaining in popularity:

1. Complexity is making it harder to keep track of the interconnects, particularly in devices where there are multiple cores and multiple power islands that can be turned on and off.
2. Smaller staffs with targeted resources, or even the same size staff with more complex demands, are forcing design teams to put their resources where they can make a competitive difference rather than re-inventing something that is good enough and which adds no value.
3. Market windows are forcing companies to rethink their make vs. buy decisions, which is driving decisions about everything from intellectual property to restrictive layouts.

Riding the bus

One of the earliest standardized approaches to solving interconnects was the bus approach, and it remains popular in many chip designs today. ARM rolled out the Advanced Microcontroller Bus Architecture (AMBA) in 1996. AMBA is now in its third generation, with significantly improved speed over the first iteration. IBM developed its own CoreConnect standard for its Power chip architecture.

For chip developers, the nice thing about both bus architectures is that they’re free and well documented. AMBA 3.0 actually includes five different bus interfaces, most notably the Advanced High-performance Bus (AHB), which permits such things as burst transfers and split transactions, and the Advanced eXtensible Interface (AXI), which focuses on addressing and data phases. CoreConnect, meanwhile, includes a processor local bus, an on-chip peripheral bus and a device control register bus.

The advantage—and the disadvantage—of buses is that they’re hard-wired through a crossbar switch. While that guarantees a connection, there are fairly regimented ways of making those connections. For example, you can’t just connect a 32-bit IP core with a 64-bit interface without a converter, and you can’t just match up components with different frequency without using a clock converter.

“Ultimately, a bus performs the same task as a network on chip,” said Mike Dimelow, director of marketing for ARM’s processor division. “Their ways of solving the interconnect issue are different, though. They are both complementary and competitive with each other, but the problem they are trying to solve is the same—connectivity.”

They’re also a way of adding re-usability for IP, which is why Xilinx is now adding support for the AMBA bus architecture in its FPGAs—the last of the major FPGA vendors to support AMBA (both Actel and Altera have supported AMBA for years, while Xilinx backed the IBM CoreConnect approach). One of the attractive things about AMBA is its support for IP-XACT, the IP interoperability standard created by the SPIRIT Consortium (now part of Accellera).

“What this allows us to do is standardize on an interconnect scheme,” said Vin Ratford, senior vice president for worldwide marketing and business development at Xilinx. “FPGAs are a repository for a lot of IP. AMBA is one element for allowing more reusable IP.” (See Figure 1)

Figure 1: AMBA's IP connection (Source: ARM)

Adding flexibility

Building on the need for pre-configured connectivity, networks on chip have taken that approach a couple steps further by decoupling the transaction from the transport, and more recently decoupling the entire physical layer. The approach follows the broader networking world, where information is packetized into discrete bundles rather than maintaining a constant connection the way old telephone lines used to do. (For a look at life before packetization, check out some of old political thrillers where the telephone was kept off the hook one a connection was made to make sure that communication would not be interrupted.)

Decoupling of all those pieces allows a much more flexible design, and both Sonics and Arteris have been pitching the value of different NoC approaches. Sonics joined forces with Synopsys in June to create a pre-configured IP block that includes a memory scheduler and Synopsys’ Designware protocol controller IP. Arteris upped the ante in the NoC world in August, rolling out a peripheral NoC that instantly connects timers, USB, infrared interfaces and audio and touch-screen components.

The advantage of NoCs is a reduction in the number of wires and the flexibility of the design. “What this provides is ultimate flexibility,” said Geert Rosseel, chief technology officer at Arteris. “There is no topology or configuration you have to worry about up front, so in the end this can lead to truly smaller chips with higher frequency. You get big improvements with power, area and performance by using this approach.” (See Figure 2)

Figure 2: The NoC approach. (Source: Arteris)

That’s particularly useful from an architectural level when not all the functions or connectivity that ultimately will be required are known. In some cases, new standards or interfaces are completed before a chip reaches tapeout, and having the flexibility to add onto the design at a later stage is invaluable—particularly when the design will be used for a series of derivative chips.

ARM, meanwhile, is hedging its bets on both the bus and NoC. While it continues to update and support AMBA, its QoS now supports both, according to Dimelow.

By Ed Sperling

When it comes to ecosystem plays, ARM’s TechCon3 gets the trophy. Most of the major players in system-level design showed off the fruits of their deals with ARM this week, with major emphasis on time to market, better performance and reduced power.

Mentor Graphics joined forces with ARM over its Nucleus real-time operating system. The two companies have developed a comprehensive software development solution around the Nucleus RTOS and graphics for ARM processors that offers ARM a way of reaching much further into the handheld world.

Synopsys, meanwhile, rolled out an optimized implementation methodology for a fully synthesizable 2GHz ARM Cortex A8 processor at 540 milliwatts. It gives new meaning to the idea of a design flow.

The other Big 3 player, Cadence, signed a deal with ARM to develop AMBA-based designs with its SoC design flow. CoWare struck a deal with ARM involving the AMBA bus, as well, this one for rapid configuration. For that matter, so did Xilinx, for development based upon ARM’s interconnect fabric.

In the manufacturing world, ARM also inked a deal with Globalfoundries, which should prove an interesting one considering the foundry’s push to create what it calls a virtual IDM model.

And ARM itself introduced a new Cortex-A5 MPCore processor, which allows for up to four cores on a processor that runs at very low power. ARM had to showcase something on its own. Clearly, Intel is showing up in the rear view mirror on this one.

By Ed Sperling
Virage Logic cut an interesting deal with NXP, the former Philips Semiconductor. Assuming the deal goes through, NXP gets to use Virage’s IP for 44 months, pays $60 million to Virage, and gives Virage a large chunk of its standard analog IP—not to mention 160 of its employees. So is this a case of crossing the pond or everyone swimming in the same pond?

Mentor’s deal to buy Valor was much simpler. Mentor will simply pay $82 million for Valor, which makes PCB productivity improvement software. Considering the push for holistic design that extends well beyond the chip, this is an interesting acquisition.

Synopsys took the covers off its high-level synthesis tool Synphony. This had been rumored for some time, but no one outside the company knew for sure what was happening—or at least they weren’t talking. It’s an interesting extension of Synopsys’ Synplicity acquisition, though. It allows engineers to migrate algorithms written in floating point to fixed point, or from The Mathworks‘ Matlab to RTL. This has been a big hole in Synopsys’ product lineup. Consider it filled.

TSMC issued its September sales report, confirming what many already knew: much of the buildup of the past few months was largely the result of an inventory shortage. Net sales dropped 3% from August, and 0.8% from September 2008.For the first 9 months, sales dropped 24.6% compared to the same period in 2008. Some companies are coming out of the recession nicely—notably Google, Apple and Intel—but it certainly isn’t going to be a straight line back for everyone.

ARM’s Techcon (formerly the ARM Developer Conference) is next week, and a large portion of the industry is lining up on ARM’s side to make presentations. This is newsworthy largely because it’s in context of one of the biggest wars to be fought in years in the chip industry, this one between ARM and Intel. ARM’s strength is its low-power cores, while Intel’s is performance. Both are struggling to reach parity (or superiority) in each other’s stronghold—ARM is working on more cores and Intel is working on low-power versions of Atom—and it should prove to be an interesting fight.