Mentor Graphics won two deals. The first was from U.K.-based Professional Circuit Design, which standardized on Mentor’s PCB design through manufacturing technologies and consulting services.  The second involved Vestel Electronics, a set-top box manufacturer in Europe, which is using Mentor’s Inflexion user interface technology.

Synopsys won a deal with AMD, which will use Synopsys’ Discovery VIP involving everything from USB 3.0, ARM’s AXI, SATA 3.0, PCI Express 3 and Synopsys’ Protocol Analyzer. What makes this especially interesting is AMD’s play in the enterprise space.

MIPS rolled out a new generation of processor cores called Aptiv, with an emphasis on performance and energy efficiency. The cores are targeted at high-end mobile devices and smart home entertainment, squaring off against ARM’s big.LITTLE with what it claims is a much simpler power management scheme.

Cadence introduced TripleCheck IP Validator, the latest addition to its verification IP catalog for compliance testing of interface IP. The company also announced availability of its OrCAD Capture Marketplace for its OrCAD and Allegro PCB community through a desktop browser.

Samsung rolled the industry’s first hardened ARM Cortex A-15 SoC utilizing Synopsys’ IC compiler for place and route of the 32nm chip. The chip is based on Samsung’s LP process using high-k/metal gate technology. ARM’s A-15 is its most power processor core yet, and one that it has positioned squarely against Intel.

The problem stems largely from re-use and legacy IP. While it might be convenient to use only on an AXI standard protocol from ARM, most chips are a combination of IP tied to specific protocols that require complex interconnects, add significant time to the verification process, and often have an impact on performance.

“It’s never AMBA, Sonics or Arteris for everything,” said Mike Gianfagna, vice president of marketing for Atrenta. “There are a lot of configurations on a chip. You’ve got crossbar switching and arbitration schemes. The big question, particularly when you get into 3D stacking, is which one you should use. So you come up with half a dozen configurations and you experiment for power, performance and area.”

He said the on-chip interconnect problem is one more complexity issue that has to be ironed out. But it also has some unusual pitfalls. “An IP block is like an amoeba. It can morph in unpredictable ways. You need to be able to analyze that up front.”

How we ended up here
There have been a number of attempts over the past 15 years to avoid this kind of problem. In 1996, when the Virtual Socket Interface Alliance (VSIA) was formed, SoCs were still in their infancy even though more and more chips included some sort of processor. The hot topic at that time was whether to decouple the processor from the chip and isolate components from the interconnect. That gave rise to a handful of ARM standard buses.

“The job of the interconnect fabric is to just make it work,” said Drew Wingard, CTO of Sonics. “But what’s happening in designs is the total level of integration is going through the roof. We’re now seeing chips with more than 100 IP cores, MPEG encoders and decoders and Huffman algorithms, and you need the interconnect in a subsystem to be a good match for what you’re trying to do. The interconnect needs to be optimized for that.”

But within a single design there may be dozens of interconnects from multiple vendors, including some that were internally developed by the chipmaker.

“There will still be custom semiconductor companies doing their own interconnects,” Wingard said. “But for the bulk of the design, the number of interface standards generally is going down and most IP cores are much more latency tolerant than they used to be.”

Past, present and future
To a large extent, SoC developers are suffering from the same kind of backward-compatibility issues as software and processor vendors have been wrestling with for decades. What makes it an issue now is the level of integration and the emphasis on re-use of IP because of cost and time-to market constraints.

“If you look at the big companies, there is a long legacy of using things so they have a lot more heterogeneous stuff,” said Laurent Moll, CTO at Arteris. “Some of it they got through acquisition. If you were to create a brand new company—and there aren’t many of those these days—with a clean sheet of paper they would most likely pick the IP that is homogeneous. So you might settle on AXI as the dominant protocol, and you might even be able to achieve that today because most commercial IP is available with AXI.”

He said the first reason companies choose a homogeneous interconnect fabric is integration and verification. “It’s easier to have one person be the expert on a team than have to work with a bunch of other experts. It also takes less time to verify, fewer tools, and less time to integrate.”

Also key is performance, but that’s far less of a clear-cut decision because not all IP behaves the same way in different designs. “There are sets of protocols that don’t like to talk with each other,” Moll said. “Even the same protocols sometimes don’t work as well together as you would expect.”

Even more complexity
Just getting these various IP blocks to talk with each other is hard enough. Doing it efficiently is as much art as science. But at the center of any discussion of power there is almost always the interconnect fabric.

“Logically, the longest wires on a chip are in the interconnect,” said Sonics’ Wingard. “You have to get to all four edges of the chip. That’s why interconnect architectures are frequently restructured to decrease the time it takes to get a signal from one side to the other.”

Wide I/O and stacked die are being viewed as a way of dramatically reducing distances on a chip by running them through an interposer. To a large extent, that’s an interconnect problem. With non-uniform memory characteristics, one chip may be one or two ticks closer, which in turn improves throughput and scalability. It also allows designers to load balance data structures and traffic, Wingard said.

The downside of this approach, again, is choice—too many choices, in fact.
“The Achilles heel of 3D is too many options,” said Atrenta’s Gianfagna. “You have to reduce the number of choices quickly. So even when you come up with your bus architectures, power domain management is still a big deal.”

This shift has been overhyped, overpromised and slow to materialize. While SoCs have been common for years in mobile electronics and for high-performance platforms such as gaming consoles, they have always been more expensive to design and manufacture. But at 40nm and beyond—and increasingly even at 65nm and 90nm—physics, an increasing amount of software and the inclusion of more third-party IP are forcing changes in best practices for designing chips. And as the industry heads into 2.5D stacking over the next couple years, subsystems that can be part of systems in package will add even great emphasis, as well as some new wrinkles, to the shift.

“It’s happening now and it will continue to happen,” said Tom Lantsch, executive vice president of corporate development at ARM. “We’re seeing application processors that are heterogeneous multicore on the same chip with graphics engines and video engines and they’re now running Symbian instructions. A lot of this shift is based on power. There’s a realization that you can do things other ways more efficiently.”

So what exactly is the difference between an SoC and an ASIC? The common definition is that an SoC includes one or more processors plus software and peripherals, making it a complete system rather than a ASIC, which is suited for a very specific task.

“The ASIC customer used to be the system house,” said Hans Bouwmeester, director of IP at Open-Silicon. “But now the system houses and fabless semiconductor companies are focusing on horizon tasks. It’s not divided by front end and back end anymore. It’s horizontal and vertical, which is re-use or availability of IP and competence. If you look at ARM’s chips, they’re applicable across multiple domains and customers are willing to outsource that development to them.”

This shift hasn’t been lost on Open-Silicon or eSilicon, both of which are shifting from an ASIC to an SoC approach. And both say the SoC world will explode once the once the industry begins adopting 2.5D stacking over the next couple years—a move that also may include more emphasis on FPGA platforms as part of the 2.5D stack.

Partition issues
At least part of what an SoC brings to the design table is flexibility. There is an ability to try different things, and at each new process node more room to experiment. But silicon is never free, even if it is available. Shrinking feature sizes creates its own set of problems at each new process node.

The typical method of deal with these problems is a “divide and conquer” approach. If there are 500 blocks, those blocks can be aggregated according to function, shared resources, or some other scheme. But in an SoC, finding the right line on which to base that partitioning is more difficult. Even worse, it can change, depending upon which market a chip will serve.

“If you do a flat design you always get the best quality,” said Sudhaker Jilla, product marketing director at Mentor Graphics. “But as the chip grows the runtime becomes unbearable. It can go from hours to more than a week. The alternative is to use a hierarchical approach, but then you have a problem of performance. You want the turnaround time of a hierarchical flow, but the quality of a flat one.”

The reality is both are needed for SoCs, but that also means a significant learning curve for the design teams. They need to learn new tools, figure out how to partition their designs—whether it’s by blocks, geography, or IP.

“The key is that companies need to figure out how to divide and conquer,” said Jilla. “Will it be dual-core or quad-core? Or will it be multiple different cores?”

More tools, more IP
For EDA and IP vendors, this is only good news. Selling to the biggest chipmakers has always been lucrative, but continuing to sell to those same customers while also adding incremental business is a big win. FPGA tools have been sufficient, for example, to do basic layout and verification, but put that same FPGA into an SoC or a stacked die configuration, add software and third-party IP, and then try to integrate it all together and the complexity easily outpaces what the typical FPGA tool can do.

“The biggest trend is that people are spending 35% to 40% of their effort writing software,” said John Koeter, vice president of marketing for Synopsys’ solutions group. “When you get down to 28nm or 20nm, companies are spending more than 50% of the time to market developing software. If you look at an SoC today, it’s usually two to four host CPUs, two to four GPUs, and it’s increasingly heterogeneous.”

He said that opens up huge opportunities for linking software to hardware, and virtualizing the hardware and software. It also opens up opportunities for IP, tools to help integrate that IP, exploratory tools that can show the tradeoffs at the architectural stage, and a suite of verification tools and verification IP.

“Just from a verification standpoint you’ve got to tackle this at several levels,” said Pete Heller, senior product line manager at Cadence. “You’ve got to look at it from the subsystem and block level for functional reasons. And you’ve got to look at the full SoC and pump real data through the system so you can get as much real-life validation as you can. Then there’s a third level, which is to put it into the hands of 100,000 people and let them be the guinea pigs after you’ve already worked out all the bugs you can.”

What is a subsystem?
That leads to the next phase of this whole development scheme—fully integrated and tested subsystems, which are expected to begin hitting the market over the next year in preparation of more SoCs and 2.5D stacked die.

“If you look back 10 years when Gartner was tracking design starts, in 2000 there were about 20,000 chip designs a year,” said Drew Wingard, CTO at Sonics. “Now we’re seeing more SoCs because you have processors sprinkled around the chip that may or may not even show up in the bill of materials and that you may or may not have access to.”

Increasingly, those pieces will be combined into fully integrated systems that include IP, possibly processors, and perhaps even shared resources such as memory with standardized interfaces. That approach will become particularly useful when chips can be stacked, either in 2.5D or 3D, and it will completely render the number of design starts meaningless. There will be more design starts, but the final outcome may be subsystems rather than chips—or chips that are part of a stack rather than the fully integrated stack itself.

“A general-purpose processor may not be the most efficient way to accomplish a task,” said Wingard. “This has led to a huge discussion around subsystems. Not everyone believes each function needs a processor. But how independent is a subsystem going to be? You can quickly get into a situation where you have enough performance most of the time, but there may be specific and critical sequences where you don’t have enough.”

There has been a lot of talk about subsystems across the industry lately, and companies are positioning themselves to take advantage of this shift. But the challenges of making this all work are huge.

“This is similar to the challenge embedded companies have faced for a long time,” said Simon Butler, CEO of Methodics. “It’s one thing if you’re dealing with a homogeneous environment where the tools talk together. But when you have to bring all these different pieces together and make sure all the parts are aligned, it’s going to be very difficult.”

Past, present and future
Still, the road to SoCs has been set and it’s gaining momentum. That became very obvious at the Consumer Electronics Show over the past couple of years.

“What’s changed is the user experience is now a combination of hardware and software,” said Mike Gianfagna, vice president of marketing at Atrenta. “We’re seeing the consumerization of electronics. The idea isn’t new. Joe Costello was talking about this a decade ago. But it’s finally happening. The semiconductor content is enabling the user experience.”

That will only increase as future designs allow more choices of IP, software, processors and ultimately subsystems on a chip—and more intelligent tradeoffs to make it all work faster and cheaper while using less energy.

There are at least five levels of coherency that need to be considered already, with more likely to surface as stacked die become mainstream over the next few years. Perhaps even more mind-numbing, this stack itself will have to take on a level of coherency over the couple generations of chips.

Let’s take a closer look.

Cache coherency
The concept of keeping data coherent historically was relegated to processor makers such as IBM, Intel and AMD, which have focused on improving performance through faster access to data. One solution to that improved performance has been multithreading and multiprocessing. Along with that, these vendors have added in various levels of cache memory for faster recall of important data.

More cores also makes it harder to effectively use these caches. Data has to be kept consistent, which requires more system overhead in terms of processing and power just to maintain that coherency. And it gets even harder as more cores are added into an SoC, which increasingly are not same size, do not run at the same frequency, and sometimes do not even connect directly to the main CPU.

“With cache coherency, some of the traffic may be serviced by the cache on another GPU,” said Drew Wingard, CTO at Sonics. “If you’re just using an ARM core, the CPU coherence is sufficient. But the GPU uses its own local memory. You really want it to be fully cache coherent across all of those.”

But even finding the data to maintain consistency may be a problem in a complex SoC.

“You can view what’s in memory, or view it and be able to change what’s in memory, but first you have to find it,” said Kurt Shuler, vice president of marketing at Arteris. “If you have four cores, the most efficient way to hook them up is for each core to have its own cache and graphics to have its own cache. If you change something, you have to snoop in all the caches to make sure it’s consistent.”

But there is also a move in the completely opposite direction—sharing memories among multiple cores—because it reduces the number of components on the bill of materials. The Low-Latency Interface specification from the MIPI Alliance is a case in point, where a memory can be shared between a modem and an applications processor. Intel, meanwhile, has added on-chip graphics that share memory with the CPU.

“The whole design gets more complex,” said Shuler. “You have more traffic beyond the cores, and from a power standpoint the overhead goes up.”

Still, cache coherency is one of the better-understood pieces of this stack. It has been an issue ever since multiprocessing was first employed in the 1960s. “Snooping” has been widely used since that time.

Software coherency
A newer facet of coherency involves embedded software. Because SoCs now include an increasing amount of software in the design, engineering teams now have to wrestle with coherency issues that previously were dealt with by the operating system.

“Fundamentally you’ve got two combined issues here,” said Andy Meyer, verification architect for Mentor Graphics’ Design Verification Technology Division. “You’ve got cache coherency, where the same data is being viewed in a couple places. And then you’ve got an issue with consistency in the simple code in a uniprocessor that now has to run on a second processor. The ordering of events can change in multiprocessing.”

Those problems crop up regularly in verification, but not always with the expected results. It’s difficult to effectively write the stimulus in a testbench for coherency. What happens, for example, when a core is shut down to save power?

“The scariest part is when there is no OS support,” said Meyer. “There’s also a big problem with heterogeneous cache, such as when you have a CPU working with a GPU.”

Another issue has to do with effective coverage in verification, already a problem for complex SoCs. States frequently are distributed across multiple chips and multiple boards. Timing varies from one state to another, and can be particularly problematic if snooping functions are tied to a state. And parallelism continues to baffle even the most advanced teams.

“Standard coverage methods don’t work well here,” said Meyer. “You have to query in ways you traditionally didn’t have the power to query and ask questions across months of regressions. For instance, ‘Have we been here ever—or in the last two months.’ Until coverage steps up, people with deep knowledge of verification running hundreds of full-time emulator systems are finding out at the last minute that it’s not okay to ship.”

I/O coherency
Tied in with both cache coherency and software coherency is I/O coherency. Increased communication on a chip, between chips, and between a chip and the outside world, have turned what used to be a relatively straightforward networking issue into a complex jumble of prioritization and synchronization.

“You have to deal with this even in single processors,” said Sonics’ Wingard. “You may have a PCI core streaming data into memory. Today, without I/O coherence, it’s difficult to determine what is coming in. The CPU has no way of knowing what was transferred when it dos a copy from non-cache to cache.”

He noted that personal computers had I/O coherency for a long time, particularly with direct memory access. DMA was developed initially to help solve the bottleneck that occurred when a CPU was involved in an I/O transfer. Rather than tie up the CPU with that transfer, the CPU continued running, then accepted an interrupt when the transfer was completed.

But with more of this being moved onto a chip, keeping coherency while moving data back and forth from more places is becoming much more difficult.

Ecosystem coherency
One of the least addressed facets of the coherency stack involves business and communication issues across a supply chain for a particular SoC rather than the actually technology itself. Even where competitive suspicions can be overcome, the very different approaches taken for designing components, IP and software, as well as language barriers, create one of the more difficult and less tangible challenges in the coherency stack.

“The challenge going forward is that you have a bunch of people who may not be that skilled in system development driving the chip and spec for one design, and other supplier trying to orchestrate things,” said Mike Gianfagna, vice president of marketing at Atrenta. “So you bring them together to solve a problem for one customer in 12 weeks and then they move on. You’ve got corporations coming together and bringing all these pieces together almost like the way a movie is done. But is there a coherent way to communicate data and information risks and still provide good visibility from a power/performance/area point of view?”

For decades this task has been handled by IDMs, but in the SoC world there are far fewer IDMs these days. Many of these chips are built using third-party IP such as cores from ARM or MIPS, DSPs from companies such as Tensilica, and standard IP from the Big Three EDA vendors.

Coherency in stacked die
It’s uncertain whether stacking of die, either in 2.5D or 3D configurations will make coherency easier or harder. The answer is likely to be a little of both.

“With 2.5D and 3D, you’re looking at low-power memory access,” said Arteris’ Shuler. “You put the DRAM closer to the CPU, the addressing is wider and you get rid of some of the latency. But you also need coherency across all of this.”

No one is sure yet how multiple high-speed communication channels between die will affect coherency. If the channel between the core is wider and shorter that will improve data speed, but if processors and DRAM are scattered on multiple die, with some of them shut down, some partially shut down, and others fully active, it may make it harder to keep track of data and make sure it is all synchronized.

A significant consideration in moving from one process generation to the next is that there are many IP functions that must migrate. “Sometimes it’s too expensive to port it from one generation to the other and you may not need it as far as the speed or as far as the power,” noted Shafy Eltoukhy, vice president of manufacturing operations for Open-Silicon.

This is where advanced die stacking comes into play. The engineering team may consider going to 28nm for one particular aspect of the function—for example, to get a better speed in the ARM processor—while there are a lot of other interfaces for a particular die that may not have to be in that advanced process node. A USB 2.0 or 3.0 does not have to be in 28nm to achieve the requirements—it could be in 90nm or 40nm, he said.

“The whole notion of re-using IP is common, though something not as commonly discussed is the reusability of die. What we’ve been seeing a fair amount of is companies saying, ‘I’m going to use advanced packaging techniques that are available today and I’m going to take this older generation die that I’ve got sitting on the shelf. And I’m going to make a much smaller new chip to complete it or extend it or interface to it. And I’m going to put that all into a multi-chip module, or advanced packaging structure, and circle back and use a lot of the IP that is in actual hardware form and make that available.’ It’s not mainstream, but reusing IP 15 years ago wasn’t mainstream either,” said Jack Harding, president and CEO of eSilicon.

Engineering teams tend to have a certain function they really want to squeeze and go to the next generation, but there are a lot of other functions in the design that don’t have to be in the latest generation, Eltoukhy observed. In advanced SoCs, customers are paying first and foremost for the IP development. “You are paying more dollar-wise per silicon area for a function that does not have to be in 28nm.”

What process node makes sense
Naturally this leads to a discussion about not bringing every single function into the next generation, especially because some analog and RF functions do not scale very well. So why not stay in the previous generation and partition the design in order to leverage older technology where available and not re-invent it?

“What I have to do instead is some kind of interface between this technology and the new technology. I put only the function that I want in the technology that can handle it and leave the other somewhere else,” he noted.

The question then becomes how to connect these together. “You certainly can connect them on the package level, which people used to call MCM (multi-chip module). You can actually get multiple die and bolt them in the substrate of the package and connect them. But the package technology has been way, way behind compared to the silicon technology, and you may end up with much higher power and slow interfaces and so on,” Eltoukhy explained. This has led to the development of silicon interposer technology in order to replace the substrate interconnect or the package interconnect, which is commonly known as 2.5D stacking.

Essentially, silicon interposer technology connects one die to another instead of connecting to a package, thereby reducing power and improving speed. Xilinx already has made its version of 2.5D-stacked technology available with certain product families.

Another use of 2.5D would be in a processor design that needs to talk to a DRAM, he continued. “Most people have a DDR interface and you go through the board to interface with the memory. But this approach is slow and large. Instead of buying a DRAM package from a DRAM vendor, we ask the vendor to sell us a known good die, which can be attached with processors on an interposer so you don’t have to go outside the chip. The DRAM can talk to the processor right away and the form factor will be much, much smaller. So there are multiple applications for that interposer—mixing the process nodes so that you can reduce the cost and so on, and improving the yield or bringing up some known good die from the DRAM to your die.”

“The application processors, which are really only delivered with package-on-package memory, end up with a very easy knob in that system—they can pile on different amounts of DRAM. To them it’s almost the same design and it is the same software. A couple of bits different in the software and suddenly they’ve got a new derivative part,” said Drew Wingard, CTO of Sonics.

“In many cases the die itself has more package attachment or wire bonding sites than the package may have pins, so you may take the same die and put it into a different package with different amounts of I/O resources available, and then sell those chips—even though they are the same fundamental chip design—at different price points. That’s been going on for a long, long time but with some of the more advanced packaging technologies, there are new degrees of freedom there,” he added.

While sounding tantalizing, all of these options are still under development. Complicating widespread deployment are two factions in the industry at odds as to the right path forward. On one side are the semiconductor foundries, which would like to enable customers to use a transposer because, at the end of the day, they want to sell more dies to put on the interposer, Eltoukhy explained. “They say, ‘We can give you the interposer but you buy the dies from us and we can glue it together for you.’”

In another camp are packaging providers such as Amkor and ASE that fear losing business to the foundries and would also like to offer the interposer to their customers so they won’t go and do the interposer with their foundry. “These two camps are fighting now because it requires some investment from a capex point of view,” he added.

Managing complexity, saving dollars
In addition to dealing with complexity, advanced die stacking techniques can save big dollars, eSilicon’s Harding asserted. “You could measure it just in terms of NRE dollars, you could measure it in engineer years of work, you could measure it in terms of time to revenue. By any metric, going down the advanced-package, multi-die solution is better by two orders of magnitude than just actually making a new chip, and I would argue it’s probably better by one order of magnitude by just doing RTL modification, which still has high NRE and a lot of technical risk, albeit you have a product that is closer to being the final product. These decisions are classic risk-reward.”

On the relationship side, Synopsys struck a deal with Arteris to jointly develop an IP solution based on the Low Latency Interface, which cuts the cost of the bill of materials by eliminating a memory chip and reducing the area of a PCB. In a related move, Arteris introduced its low-latency interface digital controller IP, which it says is already silicon-proven in TI’s OMAP platform.

Synopsys also is working to link Springsoft’s debug technology with its own Protocol Analyzer. It also won a deal with BiTMICRO for a slew of EDA tools.

Samsung teamed up with Mentor Graphics to create a DFM sign-off reference solution for Samsung’s foundry. This opens the door to a couple of other big deals for Mentor, as well, considering Samsung is one of the three main companies in the Common Platform. The others are GlobalFoundries and IBM.

Mentor also announced its Q4 financial results, which set a new record. Revenues for the quarter were $320.4 million, up from $307.3 million in the same period in 2011. For the 12 months ended Jan. 31, revenue was $1.015 billion—also a record—up from $914.8 million in fiscal 2010. Net income for Q4 was $57.8 million, up from $50.6 million in Q4 2011, and for the year it was $83.9 million, compared with $28.6 million the previous year. Mentor expects revenue to increase to about $1.1 billion this year.

Cadence unveiled the production release of a virtual platform for Xilinx’s Zynq-7000, which is based on the ARM Cortex-A9 MPCore. After years of EDA companies trying to gain a strong entry into the FPGA world, this is an interesting doorway.

Docea Power rolled out a new tool for architectural-level power and thermal analysis. Given the fact that the biggest savings in power and heat can be obtained at the earliest stages of a design, this is an important step forward. The next challenge is to implement this kind of capability into existing flows so that power and heat models can be integrated easily with other models. Functionality and performance are no longer enough.

Tensilica introduced its second-generation multimode baseband chip, which includes multiple dataplane processors. The chip was co-developed with NTT DOCOMO, Fujitsu, Panasonic and NEC.  Tensilica also rolled out Dolby Digital Plus for surround sound on its HiFi Audio DSPs, and it struck a deal with ClariPhy, which will license Tensilica’s dataplane processors for optical networking mixed signal processing.

Mentor’s Robin Bornoff explores what could well be the only documented joke about LEDs. And no, it has nothing to do with the number of engineers required to install an LED.

Synopsys’ Karen Bartleson rolls out part four of her epic on why we need standards. This one focuses on innovation.

ARM’s Ian Ferguson looks at the possibilities of ARM chips in really small servers, not just big data centers. This is generally well below the radar for most processor companies. What’s particularly interesting is the crossover between mobile and devices with a plug.

Cadence’s Richard Goering recounts the top 10 Cadence blog posts of 2011, according to readership numbers. Verification, stacked die and power analysis top the list.

In a similar vein, blogger Gaurav Jalan recounts five significant changes in 2011. While most of these are still works in progress, they are indeed significant.

The truth is they’re both right. There are too many old standards and not enough new ones. Where technology converges and uncertainty adds risk, standards are considered essential. They improve time to market, help get multiple companies speaking the same language and moving in the same direction, and they can bring enormous cost savings.

But when standards are no longer needed, they tend to stick around forever—like space junk. Standards need to be maintained and updated. But the work of updating standards, which includes reassessing them regularly and combining them with other standards when it makes sense, is even less glamorous than developing the standards in the first place, and certainly more tedious. Moreover, there is even less direct economic benefit to developing those updates.

The result is that the industry is littered with old standards while the din rises for even more. Scott McGregor, president and CEO of Broadcom, said his company is involved in about 100 standards efforts at any one time.

“Standards need to evolve, and new standards drive innovation in larger markets. “But standards also need to go away when it makes sense.”

He’s not alone in that viewpoint. John Goodenough, vice president of design technology and automation at ARM, said the industry needs to “keep collapsing standards down.”

Standards to ease pain
Wherever there is a pain point—particularly one where multiple vendors are involved—there is discussion about standards. Sometimes it’s a way of slowing down a market leader. Sometimes it’s a way of slowing down everyone else who follows the market leader. But in all cases, it requires an almost superhuman commitment to negotiate an outcome because each company has its own agenda, and standards in many ways are a compromise.

“That’s why standards happen at the edges of the network,” said Charlie Janac, president and CEO of Arteris. “We’ve got standards like AXI (Advanced eXtensible Interface) and OCP (Open Core Protocol). And there will be new standards as we move from 2D to 3D, but those are just being established. The goal is that customers shouldn’t have to care about what they use. It should all just work.”

But getting things to work also requires a lot of translation, which is the really hard stuff in developing standards. Drew Wingard, CTO of Sonics, said the most effective standards are ones that allow engineers to work with their own terminology and still provide useful information to other groups using different terminology and data.

“The folks worrying about video use a different number than the people who are worrying about graphics processor performance,” said Wingard. “The best thing we can do is keep it at that level. But asking one group, like the architects of a subsystem, to adopt my vocabulary, is counterproductive. A better way is to come up with a simple language.”

That’s easier said than done, of course. Ask anyone about power formats these days and you’re likely to evoke a sour look. UPF 1.0, IEEE 1801 and CPF are all standards, but they don’t work together. There has been a big improvement in cross-standard functionality, thanks largely to the efforts of Cadence, Mentor Graphics and Synopsys, and there are now cheat sheets about how to read one versus the other. But the hard work now under way is to bridge those two with a Rosetta Stone type of translation.

While the existence of multiple power format standards still rankles customers—many of whom are quite vocal about it because they use multiple vendors’ tools and IP, which favor one format over the other. But at least the problem is being addressed, and it has served as a warning against developing standards prematurely—or without all the essential players involved in the planning process.

Works in progress
This hesitancy to put a stake in the ground for standards is particularly evident in the 3D stacking arena. Si2 and Accellera have spent the past couple years just watching the process, trying to figure out where standards will be best served.

So far, these efforts are more general than specific, as companies attempt to narrow down what will be effective. Dennis Brophy, vice chairman of Accellera, said the real drivers of these efforts are time-to-market pressures and more complicated, larger systems.

“You clearly can’t start from scratch, so you need to re-use IP,” Brophy said. “That should lead to a more reliable design and quicker verification. But you also have to catalog and store these IP blocks.”

Accellera has puts a stake in the ground for system-level IP integration—work is underway to significantly improve IP XACT. Sonics’ Wingard said what’s really needed is a way of describing the IP that companies are being asked to integrate.
“The days when you spent more money integrating IP than in buying it are over. We expect it to be a black box.”

Accellera also is is pushing for UVM to be part of the system-level verification flow. This is easier said than done, because companies are still investing heavily in VMM and OVM, the verification methodologies that UVM is supposed to supersede. Accellera also is examining what standards will be necessary in software so there is some sort of bridge between SystemC, analog/mixed signal, and system Verilog.

Analog/mixed signal and 3D
Analog is a particularly thorny subject when it comes to standards. The sheer complexity of the problems being solved has surpassed the ability of analog designers to do everything manually, requiring far more automation than in the past. In addition, with stacked die looming in the future, a consistent way of writing analog is now required because the analog will probably reside in a separate subsystem or on a separate die that must be integrated with other die.

“This has to be a black box so it can be sold and integrated,” said Simon Butler, CEO of Methodics. “But how do you prove that it works when you get that block? You need a standard way to test it.”

He said that IP-XACT will address some of those concerns with digital IP for a consistent way of creating testbenches and defining what’s in an IP block. Analog is another story entirely.

“In 3D, there will be dependencies created,” he noted. “We need to add context into all of this.”

The road ahead
Si2 has plotted a number of standards it plans to work on in 2012. Topping the list are the following:

1. OAC: New release of OpenAccess to include scratch designs and other functionality and performance enhancements.
2. DFMC: OpenDFM 2.x will include DRC+ and other enhancements, while OPEX 2.x will include open parasitic extraction parameters and OpenLVS
3. LPC: Updated power modeling standards to support handling power intent and verification for large IP blocks
4. OpenPDK: New OPS 1.0, the Open Process Specification, will include a symbol standard, a design parameter standard, and a callback standard, and all other design parameters. In addition, all work started in 2011 will be completed.
5. Open3D: Standards are expected to be released to address definition of the power distribution network across the die of a 3D stack; thermal design and analysis of an entire 3D stack, including thermal constraints between neighboring dies; and expression of design constraints into and out of the path-finding and floor-planning stages of the overall design process. All work started in 2011 will be completed.

The road behind
Getting rid of the old standards, or at least collapsing them and making them more useful, is a subject no one wants to talk about. But venture capitalist Jim Hogan did have an interesting observation about just how long standards stick around.

At a recent Synopsys interoperability forum, Hogan noted that Roman roads were constructed exactly 47 inches wide to accommodate two horses used to pull a chariot. He said the distance between rails is the same distance, and the seat in his car is exactly 23.5 inches wide.

So far, no one has seen a need to adjust that number.

Synopsys rolled out a new version of its FPGA-based prototyping tools, improving performance and allowing faster design revisions. The rollout also includes improved debug capabilities throughout the entire design cycle. 0

Tensilica won a deal with Skyviia, a Taiwanese company that develops multimedia ICs, for its HiFi Audio DSP core. This moves Tensilica further into the Android and portable multimedia markets.

ARM also made a bigger push into Taiwan, expanding its R&D presence with a Hsinchu Design Center.