Mentor’s Robin Bornoff explores what could well be the only documented joke about LEDs. And no, it has nothing to do with the number of engineers required to install an LED.

Synopsys’ Karen Bartleson rolls out part four of her epic on why we need standards. This one focuses on innovation.

ARM’s Ian Ferguson looks at the possibilities of ARM chips in really small servers, not just big data centers. This is generally well below the radar for most processor companies. What’s particularly interesting is the crossover between mobile and devices with a plug.

Cadence’s Richard Goering recounts the top 10 Cadence blog posts of 2011, according to readership numbers. Verification, stacked die and power analysis top the list.

In a similar vein, blogger Gaurav Jalan recounts five significant changes in 2011. While most of these are still works in progress, they are indeed significant.

The truth is they’re both right. There are too many old standards and not enough new ones. Where technology converges and uncertainty adds risk, standards are considered essential. They improve time to market, help get multiple companies speaking the same language and moving in the same direction, and they can bring enormous cost savings.

But when standards are no longer needed, they tend to stick around forever—like space junk. Standards need to be maintained and updated. But the work of updating standards, which includes reassessing them regularly and combining them with other standards when it makes sense, is even less glamorous than developing the standards in the first place, and certainly more tedious. Moreover, there is even less direct economic benefit to developing those updates.

The result is that the industry is littered with old standards while the din rises for even more. Scott McGregor, president and CEO of Broadcom, said his company is involved in about 100 standards efforts at any one time.

“Standards need to evolve, and new standards drive innovation in larger markets. “But standards also need to go away when it makes sense.”

He’s not alone in that viewpoint. John Goodenough, vice president of design technology and automation at ARM, said the industry needs to “keep collapsing standards down.”

Standards to ease pain
Wherever there is a pain point—particularly one where multiple vendors are involved—there is discussion about standards. Sometimes it’s a way of slowing down a market leader. Sometimes it’s a way of slowing down everyone else who follows the market leader. But in all cases, it requires an almost superhuman commitment to negotiate an outcome because each company has its own agenda, and standards in many ways are a compromise.

“That’s why standards happen at the edges of the network,” said Charlie Janac, president and CEO of Arteris. “We’ve got standards like AXI (Advanced eXtensible Interface) and OCP (Open Core Protocol). And there will be new standards as we move from 2D to 3D, but those are just being established. The goal is that customers shouldn’t have to care about what they use. It should all just work.”

But getting things to work also requires a lot of translation, which is the really hard stuff in developing standards. Drew Wingard, CTO of Sonics, said the most effective standards are ones that allow engineers to work with their own terminology and still provide useful information to other groups using different terminology and data.

“The folks worrying about video use a different number than the people who are worrying about graphics processor performance,” said Wingard. “The best thing we can do is keep it at that level. But asking one group, like the architects of a subsystem, to adopt my vocabulary, is counterproductive. A better way is to come up with a simple language.”

That’s easier said than done, of course. Ask anyone about power formats these days and you’re likely to evoke a sour look. UPF 1.0, IEEE 1801 and CPF are all standards, but they don’t work together. There has been a big improvement in cross-standard functionality, thanks largely to the efforts of Cadence, Mentor Graphics and Synopsys, and there are now cheat sheets about how to read one versus the other. But the hard work now under way is to bridge those two with a Rosetta Stone type of translation.

While the existence of multiple power format standards still rankles customers—many of whom are quite vocal about it because they use multiple vendors’ tools and IP, which favor one format over the other. But at least the problem is being addressed, and it has served as a warning against developing standards prematurely—or without all the essential players involved in the planning process.

Works in progress
This hesitancy to put a stake in the ground for standards is particularly evident in the 3D stacking arena. Si2 and Accellera have spent the past couple years just watching the process, trying to figure out where standards will be best served.

So far, these efforts are more general than specific, as companies attempt to narrow down what will be effective. Dennis Brophy, vice chairman of Accellera, said the real drivers of these efforts are time-to-market pressures and more complicated, larger systems.

“You clearly can’t start from scratch, so you need to re-use IP,” Brophy said. “That should lead to a more reliable design and quicker verification. But you also have to catalog and store these IP blocks.”

Accellera has puts a stake in the ground for system-level IP integration—work is underway to significantly improve IP XACT. Sonics’ Wingard said what’s really needed is a way of describing the IP that companies are being asked to integrate.
“The days when you spent more money integrating IP than in buying it are over. We expect it to be a black box.”

Accellera also is is pushing for UVM to be part of the system-level verification flow. This is easier said than done, because companies are still investing heavily in VMM and OVM, the verification methodologies that UVM is supposed to supersede. Accellera also is examining what standards will be necessary in software so there is some sort of bridge between SystemC, analog/mixed signal, and system Verilog.

Analog/mixed signal and 3D
Analog is a particularly thorny subject when it comes to standards. The sheer complexity of the problems being solved has surpassed the ability of analog designers to do everything manually, requiring far more automation than in the past. In addition, with stacked die looming in the future, a consistent way of writing analog is now required because the analog will probably reside in a separate subsystem or on a separate die that must be integrated with other die.

“This has to be a black box so it can be sold and integrated,” said Simon Butler, CEO of Methodics. “But how do you prove that it works when you get that block? You need a standard way to test it.”

He said that IP-XACT will address some of those concerns with digital IP for a consistent way of creating testbenches and defining what’s in an IP block. Analog is another story entirely.

“In 3D, there will be dependencies created,” he noted. “We need to add context into all of this.”

The road ahead
Si2 has plotted a number of standards it plans to work on in 2012. Topping the list are the following:

1. OAC: New release of OpenAccess to include scratch designs and other functionality and performance enhancements.
2. DFMC: OpenDFM 2.x will include DRC+ and other enhancements, while OPEX 2.x will include open parasitic extraction parameters and OpenLVS
3. LPC: Updated power modeling standards to support handling power intent and verification for large IP blocks
4. OpenPDK: New OPS 1.0, the Open Process Specification, will include a symbol standard, a design parameter standard, and a callback standard, and all other design parameters. In addition, all work started in 2011 will be completed.
5. Open3D: Standards are expected to be released to address definition of the power distribution network across the die of a 3D stack; thermal design and analysis of an entire 3D stack, including thermal constraints between neighboring dies; and expression of design constraints into and out of the path-finding and floor-planning stages of the overall design process. All work started in 2011 will be completed.

The road behind
Getting rid of the old standards, or at least collapsing them and making them more useful, is a subject no one wants to talk about. But venture capitalist Jim Hogan did have an interesting observation about just how long standards stick around.

At a recent Synopsys interoperability forum, Hogan noted that Roman roads were constructed exactly 47 inches wide to accommodate two horses used to pull a chariot. He said the distance between rails is the same distance, and the seat in his car is exactly 23.5 inches wide.

So far, no one has seen a need to adjust that number.

Synopsys rolled out a new version of its FPGA-based prototyping tools, improving performance and allowing faster design revisions. The rollout also includes improved debug capabilities throughout the entire design cycle. 0

Tensilica won a deal with Skyviia, a Taiwanese company that develops multimedia ICs, for its HiFi Audio DSP core. This moves Tensilica further into the Android and portable multimedia markets.

ARM also made a bigger push into Taiwan, expanding its R&D presence with a Hsinchu Design Center.

Apache Design introduced an RTL Power Model solution, which accurately predicts IC power behavior at the RTL level in context of the physical implementation.

Arteris won a deal with China’s Spreadtrum for high-speed chip-to-chip communication between mobile baseband chips and application processors.

Cadence and Samsung have developed a 32nm HD digital camera SoC for Ambarella, which has been creating digital still cameras with high-definition video capabilities. Translation: lots and lots of pixels. Cadence also teamed up with Xilinx for system design, software development and testing of Xilinx’s Zynq platform. And Cadence announced its quarterly numbers, showing net income of $28.1 million for the quarter ended Oct. 1 ($37.3 million non-GAAP) vs. $126.8 million in the same period in 2010 ($11.2 million non-GAAP). Revenue for the quarter was $292 million vs. $238 million in 2010.

eSilicon inked a deal to use Synopsys’ Custom IC design solution for 28nm SoCs. And Synopsys’ DesignWare Audio IP achieved first-pass silicon for 65nm and 55nm process technologies from multiple foundries.

Open-Silicon launched an ARM Center of Excellence to provide complete SoC development solutions for low-power chip development for the networking, telecommunications storage and computing markets. This is becoming a very cozy relationship. Open-Silicon already has a multi-year licensing agreement in place with ARM.

Atrenta introduced early PPA analysis for ARM’s AMBA designer using its SpyGlass and GenSys products.  Atrenta also joined Cadence’s System Realization Alliance, which is no surprise considering it was one of the first to adopt Cadence’s EDA360 terminology.

Arteris won a deal from VIA Telecom for its high-speed inter-chip communications IP between mobile phone baseband chips and application processors.

Tensilica won a deal from EnVerv, which licensed Tensilica’s ConnX DSP cores for its smart grid power line communications SoCs.

ARM, Cadence and TSMC teamed up to tape out a 20nm ARM Cortex-A15 processor. This must mean work is starting on 14nm.
Cadence also is working with TSMC to create a library characterization kit for the foundry’s standard cell libraries.

China’s CYIT, aka Chongqing Chonyou Information Technologies Co., completed tapeout of its low-power 65nm baseband chip in five months, which is about a month ahead of schedule, using Synopsys’ Galaxy low-power design flow. That’s quick turnaround of a mainstream-node baseband design.

While IDMs such as Apple, Intel, Samsung and IBM continue to blaze their own trail, developing in-house tools, methodologies, processes and chips, fabless companies working with foundries and tools developers are beginning to show some of the same benefits for a much lower cost.

One such effort involves Cadence, ARM and TSMC, which together unveiled a 20nm Cortex A-15 chip. Mike Inglis, executive vice president and general manager of ARM’s processor division, said teams from each company worked closely together to find out what was broken on the process side, then fed that information back into performance optimization and packaging and worked it into the design flow.

“This is how you more easily get to a more optimized solution more quickly,” Inglis said. “It also enables the leading edge and the trailing edge to get to market more quickly.”

This is what IDMs have always done, taking information back and forth between the design teams and the fab and adding tweaks all along the way. But what’s changing is that fabless companies appear to be catching up more quickly than most industry observers believed was possible.

“We’re seeing collaboration that is both horizontal and vertical,” said Lip-Bu Tan, president and CEO of Cadence. “Horizontal involves industry standards among peers and does not differentiate end products. With vertical collaboration, the goal is an end product that is differentiated, whether that involves IP, EDA, the foundry or software.”

Mentor Graphics, meanwhile, rolled out the next version of its Nucleus real-time operating environment that was developed with partners such as Texas Instruments, GCT and Stonestreet One. In a move aimed at conserving power, Mentor has moved some of the power management capabilities such as dynamic voltage and frequency scaling into the kernel of the RTOS, according to Jan Klube, director of the Nucleus product line.

“The software design was built into the application from the beginning versus folding complexity onto the application,” said Klube. “So developers get a simple power management API and a power-aware RTOS.”

One of those developers is TI, which has been working with Mentor as well as ARM for its Stellaris microcontrollers. Miguel Morales, worldwide marketing manager for the MCUs, said the microcontrollers are sold with pre-written software wrapped up in kits.

“Collaboration will have to accelerate,” said Wally Rhines, Mentor’s chairman and CEO, who noted that Mentor is also working with TSMC on “reliability” kits. He added that it will be critical to respond together to new and emerging problems, particularly with stacked die where stress, thermal and parasitic effects will create as-yet unknown issues.

Synopsys, meanwhile, has been working closely with TSMC and ARM to improve yield and deal with process variations.

“As we look ahead, there is the notion that an upstream tool can know what a downstream tool must do,” said Aart de Geus, chairman and CEO of Synopsys. “We need to be able to move forward to place and route before we finish synthesis, and we need to be able to question why we should do all the work if an issue is not resolvable.”

De Geus noted that collaboration is the answer to systemic complexity. “We must be committed, and we will need to collaborate with partners that have competence.” He added that there also is a need for quick compromise, balancing a “great enough” solution against a better one that will take longer to develop.

Customers are integrating single or multiple ARM(r) Cortex(tm)-A15 processors into their SoC designs in order to take advantage of this industry-leading IP. In order to perform manufacturing test for the SoC, a test strategy needs to be adopted and the corresponding DFT implemented to achieve that test strategy. Traditionally, it has been up to the design-for-test (DFT) engineer to understand the test strategy and implement the DFT associated with it.

With the introduction of this jointly developed Mentor reference flow for ARM architecture, DFT engineers now have a guide so they can effectively and efficiently test designs that include the ARM Cortex-A15 processor.

To download this white paper, click here.

System-Level Design asked executives from across the SoC ecosystem what will change, what’s driving those changes and what the ideal SoC will look like in the next few years. Here are some projections, broken down by category:

EDA
Wally Rhines, chairman and CEO of Mentor Graphics—“The SoC at the leading edge will not be a standalone device. It will be adjacent or under other things, whether it’s a stack or an interposer, or whether it’s an SoC with memory attached. One big challenge we had was with the package verification tools for 3D. Rather than create one mega merge of GDSII we’ve had to do a careful partitioning of individual SoCs and interfaces. In our opinion 2.5D will overwhelm the other approaches for a while. Logic with memory and through silicon vias is in the early stages. An interposer with memory stacked on processors that are tightly integrated is much further along.”

Aart de Geus, chairman and CEO of Synopsys—“We’re looking at smart everything. There will be more and more cores with little IQs. There’s an Internet of people, but there’s also an Internet of things, which will be a combination of all capabilities and probably require a price decline. From a technological perspective this will be really hard, of course. But what’s new? The continuation of technology is still there and we still have all the same problems with test and verification. But we also have 25 years of backward compatibility.”

Lip-Bu Tan, president and CEO of Cadence—“Application-driven design will be the big shift. The software will drive the hardware and the hardware will drive the software. It will be both. At the foundatation will be complex digital blocks with analog blocks and key IP that has been optimized for the system. The reason is that the system guy now expects silicon and the entire hardware-software stack. Some of the apps and the IP will be able to be re-used, which will make the time to market shorter. Some will not. Right now the bottleneck is in the IP, software and total solution.”

Mike Gianfagna, vice president of marketing, Atrenta—“There are two threads to this. One is that the software guys will be driving the agenda. Software dictates the silicon and the battery life. You will have a rich library of building blocks put together against software requirements, and the hardware architecture will be abstracted so that software runs against that model. The second thread is that the tools will have to change. Early floor planning and physical analysis will be required with stacked die because there are multiple ways to put a stack together and you have to get it right the first time. A 3D stack will have to be planned and analyzed. There may be 20 possible ways to build it, but only one or two that make sense.”

IP
Simon Segars, executive vice president and general manager of ARM’s Physical IP Division—“The biggest change will be power management, which will require a collection of different processing elements. You won’t see a big, monster CPU in the future because that isn’t power efficient. The future will be distributed computing. It won’t be easy, of course. With software, physically building software that can deal with the whole system will be very difficult. There also is a big challenge in putting chips together in a cost-effective way.”

Simon Butler, CEO of Methodics—”The big challenge will be bringing business intelligence into SoC design. You need to know what EDA tools to use and what the quality is of the blocks that you are putting together. And you need to define the versions of all the IP blocks and where they’re being used around the company. The goal is to see a map of the IP fabric in a design. This isn’t being done today.”

Manufacturing/Assembly
Prasad Subramaniam, vice president of design technology at eSilicon—“SoCs will have to evolve into major platforms where 10% of the platform changes and there is commonality of 90%. Otherwise it will be completely unwieldy. That 10% will still be 20 million gates. That also includes the software infrastructure, which will allow you to do performance analysis at the system level and make tradeoffs at the architectural level.”

Tom Quan, director at TSMC—“At the advanced nodes we’re looking at baseband and digital for 28/20/14nm. We’ll need 2.5D and 3D to bring the rest of the system together. So we’re getting ‘More of Moore’ coupled with ‘More than Moore.’ There will be fewer design starts, but there will be more derivatives. The base platform will be programmable with a lot of diversity, so you may see a company sell a platform and build applications on that.”

On another front, Synopsys is collaborating with UMC to develop IP for the foundry’s 28nm HLP Poly SiON process.

Mentor Graphics is working with Freescale to accelerate automotive infotainment that relies on ARM A9-based processors. Mentor’s In-Vehicle Infotainment base platform is compliant with the requirements of the GENIVI Alliance, the association of automotive and consumer electronics companies.

Russia-based IntegrIT has ported its NatureDSP Math Library to Tensilica’s baseband DSPs. The traditional emphasis on science and math is still alive and well in Russia—and expanding into some new markets. IntegrIT develops signal-processing routines for DSP functions.