By Ed Sperling
Mentor Graphics taped out a 20nm test chip with STMicroelectronics using its Olympus SoC place and route system and verified it using Calibre nmDRC. If the leading edge companies are this far along, it means they’re already starting to look at 14nm. Things should get very interesting from here. Mentor also turned out a verification solution for ARM’s Cortex processors and its AMBA bus that includes everything from simulation to emulation.

Apache Design introduced an RTL Power Model solution, which accurately predicts IC power behavior at the RTL level in context of the physical implementation.

Arteris won a deal with China’s Spreadtrum for high-speed chip-to-chip communication between mobile baseband chips and application processors.

By Ed Sperling
It was a good week for emulation. Mentor Graphics joined forces with MoreThanIP to create emulation solutions for multi-gigabit Ethernet SoCs.  Mentor also won a deal from ZTE for its Veloce emulator, and it added emulation solutions for USB 3.0 products.

Cadence and Samsung have developed a 32nm HD digital camera SoC for Ambarella, which has been creating digital still cameras with high-definition video capabilities. Translation: lots and lots of pixels. Cadence also teamed up with Xilinx for system design, software development and testing of Xilinx’s Zynq platform. And Cadence announced its quarterly numbers, showing net income of $28.1 million for the quarter ended Oct. 1 ($37.3 million non-GAAP) vs. $126.8 million in the same period in 2010 ($11.2 million non-GAAP). Revenue for the quarter was $292 million vs. $238 million in 2010.

eSilicon inked a deal to use Synopsys’ Custom IC design solution for 28nm SoCs. And Synopsys’ DesignWare Audio IP achieved first-pass silicon for 65nm and 55nm process technologies from multiple foundries.

Open-Silicon launched an ARM Center of Excellence to provide complete SoC development solutions for low-power chip development for the networking, telecommunications storage and computing markets. This is becoming a very cozy relationship. Open-Silicon already has a multi-year licensing agreement in place with ARM.

Atrenta introduced early PPA analysis for ARM’s AMBA designer using its SpyGlass and GenSys products.  Atrenta also joined Cadence’s System Realization Alliance, which is no surprise considering it was one of the first to adopt Cadence’s EDA360 terminology.

Arteris won a deal from VIA Telecom for its high-speed inter-chip communications IP between mobile phone baseband chips and application processors.

Tensilica won a deal from EnVerv, which licensed Tensilica’s ConnX DSP cores for its smart grid power line communications SoCs.

By Ed Sperling
Mentor Graphics rolled out the next generation of its Nucleus Real-Time OS, adding power management and improved connectivity for embedded systems. The company also added a business intelligence component to its PCB software line to improve production efficiency and reduce inventory.

ARM, Cadence and TSMC teamed up to tape out a 20nm ARM Cortex-A15 processor. This must mean work is starting on 14nm.
Cadence also is working with TSMC to create a library characterization kit for the foundry’s standard cell libraries.

China’s CYIT, aka Chongqing Chonyou Information Technologies Co., completed tapeout of its low-power 65nm baseband chip in five months, which is about a month ahead of schedule, using Synopsys’ Galaxy low-power design flow. That’s quick turnaround of a mainstream-node baseband design.

By Ed Sperling
A series of recent announcements by the Big Three EDA vendors and their well-known partners from across the disaggregated SoC ecosystem is lending new credence to the impact of collaboration.

While IDMs such as Apple, Intel, Samsung and IBM continue to blaze their own trail, developing in-house tools, methodologies, processes and chips, fabless companies working with foundries and tools developers are beginning to show some of the same benefits for a much lower cost.

One such effort involves Cadence, ARM and TSMC, which together unveiled a 20nm Cortex A-15 chip. Mike Inglis, executive vice president and general manager of ARM’s processor division, said teams from each company worked closely together to find out what was broken on the process side, then fed that information back into performance optimization and packaging and worked it into the design flow.

“This is how you more easily get to a more optimized solution more quickly,” Inglis said. “It also enables the leading edge and the trailing edge to get to market more quickly.”

This is what IDMs have always done, taking information back and forth between the design teams and the fab and adding tweaks all along the way. But what’s changing is that fabless companies appear to be catching up more quickly than most industry observers believed was possible.

“We’re seeing collaboration that is both horizontal and vertical,” said Lip-Bu Tan, president and CEO of Cadence. “Horizontal involves industry standards among peers and does not differentiate end products. With vertical collaboration, the goal is an end product that is differentiated, whether that involves IP, EDA, the foundry or software.”

Mentor Graphics, meanwhile, rolled out the next version of its Nucleus real-time operating environment that was developed with partners such as Texas Instruments, GCT and Stonestreet One. In a move aimed at conserving power, Mentor has moved some of the power management capabilities such as dynamic voltage and frequency scaling into the kernel of the RTOS, according to Jan Klube, director of the Nucleus product line.

“The software design was built into the application from the beginning versus folding complexity onto the application,” said Klube. “So developers get a simple power management API and a power-aware RTOS.”

One of those developers is TI, which has been working with Mentor as well as ARM for its Stellaris microcontrollers. Miguel Morales, worldwide marketing manager for the MCUs, said the microcontrollers are sold with pre-written software wrapped up in kits.

“Collaboration will have to accelerate,” said Wally Rhines, Mentor’s chairman and CEO, who noted that Mentor is also working with TSMC on “reliability” kits. He added that it will be critical to respond together to new and emerging problems, particularly with stacked die where stress, thermal and parasitic effects will create as-yet unknown issues.

Synopsys, meanwhile, has been working closely with TSMC and ARM to improve yield and deal with process variations.

“As we look ahead, there is the notion that an upstream tool can know what a downstream tool must do,” said Aart de Geus, chairman and CEO of Synopsys. “We need to be able to move forward to place and route before we finish synthesis, and we need to be able to question why we should do all the work if an issue is not resolvable.”

De Geus noted that collaboration is the answer to systemic complexity. “We must be committed, and we will need to collaborate with partners that have competence.” He added that there also is a need for quick compromise, balancing a “great enough” solution against a better one that will take longer to develop.

This white paper provides a high level overview of the Mentor reference flow for ARM architecture.

Customers are integrating single or multiple ARM(r) Cortex(tm)-A15 processors into their SoC designs in order to take advantage of this industry-leading IP. In order to perform manufacturing test for the SoC, a test strategy needs to be adopted and the corresponding DFT implemented to achieve that test strategy. Traditionally, it has been up to the design-for-test (DFT) engineer to understand the test strategy and implement the DFT associated with it.

With the introduction of this jointly developed Mentor reference flow for ARM architecture, DFT engineers now have a guide so they can effectively and efficiently test designs that include the ARM Cortex-A15 processor.

To download this white paper, click here.

By Ed Sperling
The number of changes that will hit the IC market over the next few years is almost staggering by any standard—past or present. In addition to the relentless pressure of Moore’s Law, there will be new materials, new structures, and new models for developing and packaging chips.

System-Level Design asked executives from across the SoC ecosystem what will change, what’s driving those changes and what the ideal SoC will look like in the next few years. Here are some projections, broken down by category:

EDA
Wally Rhines, chairman and CEO of Mentor Graphics—“The SoC at the leading edge will not be a standalone device. It will be adjacent or under other things, whether it’s a stack or an interposer, or whether it’s an SoC with memory attached. One big challenge we had was with the package verification tools for 3D. Rather than create one mega merge of GDSII we’ve had to do a careful partitioning of individual SoCs and interfaces. In our opinion 2.5D will overwhelm the other approaches for a while. Logic with memory and through silicon vias is in the early stages. An interposer with memory stacked on processors that are tightly integrated is much further along.”

Aart de Geus, chairman and CEO of Synopsys—“We’re looking at smart everything. There will be more and more cores with little IQs. There’s an Internet of people, but there’s also an Internet of things, which will be a combination of all capabilities and probably require a price decline. From a technological perspective this will be really hard, of course. But what’s new? The continuation of technology is still there and we still have all the same problems with test and verification. But we also have 25 years of backward compatibility.”

Lip-Bu Tan, president and CEO of Cadence—“Application-driven design will be the big shift. The software will drive the hardware and the hardware will drive the software. It will be both. At the foundatation will be complex digital blocks with analog blocks and key IP that has been optimized for the system. The reason is that the system guy now expects silicon and the entire hardware-software stack. Some of the apps and the IP will be able to be re-used, which will make the time to market shorter. Some will not. Right now the bottleneck is in the IP, software and total solution.”

Mike Gianfagna, vice president of marketing, Atrenta—“There are two threads to this. One is that the software guys will be driving the agenda. Software dictates the silicon and the battery life. You will have a rich library of building blocks put together against software requirements, and the hardware architecture will be abstracted so that software runs against that model. The second thread is that the tools will have to change. Early floor planning and physical analysis will be required with stacked die because there are multiple ways to put a stack together and you have to get it right the first time. A 3D stack will have to be planned and analyzed. There may be 20 possible ways to build it, but only one or two that make sense.”

IP
Simon Segars, executive vice president and general manager of ARM’s Physical IP Division—“The biggest change will be power management, which will require a collection of different processing elements. You won’t see a big, monster CPU in the future because that isn’t power efficient. The future will be distributed computing. It won’t be easy, of course. With software, physically building software that can deal with the whole system will be very difficult. There also is a big challenge in putting chips together in a cost-effective way.”

Simon Butler, CEO of Methodics—”The big challenge will be bringing business intelligence into SoC design. You need to know what EDA tools to use and what the quality is of the blocks that you are putting together. And you need to define the versions of all the IP blocks and where they’re being used around the company. The goal is to see a map of the IP fabric in a design. This isn’t being done today.”

Manufacturing/Assembly
Prasad Subramaniam, vice president of design technology at eSilicon—“SoCs will have to evolve into major platforms where 10% of the platform changes and there is commonality of 90%. Otherwise it will be completely unwieldy. That 10% will still be 20 million gates. That also includes the software infrastructure, which will allow you to do performance analysis at the system level and make tradeoffs at the architectural level.”

Tom Quan, director at TSMC—“At the advanced nodes we’re looking at baseband and digital for 28/20/14nm. We’ll need 2.5D and 3D to bring the rest of the system together. So we’re getting ‘More of Moore’ coupled with ‘More than Moore.’ There will be fewer design starts, but there will be more derivatives. The base platform will be programmable with a lot of diversity, so you may see a company sell a platform and build applications on that.”

By Ed Sperling
Altera is embedding Synopsys’ virtual prototyping technology in its ARM-based SoC FPGA products. Considering FPGA vendors have been giving away their tools for years, much to the chagrin of EDA vendors that have tried repeatedly to win a foothold in the FPGA tools market, this potentially is a big deal. And considering the existing market for virtual prototyping is still small and the FPGA opportunity is quite large…well, this gets very interesting.

On another front, Synopsys is collaborating with UMC to develop IP for the foundry’s 28nm HLP Poly SiON process.

Mentor Graphics is working with Freescale to accelerate automotive infotainment that relies on ARM A9-based processors. Mentor’s In-Vehicle Infotainment base platform is compliant with the requirements of the GENIVI Alliance, the association of automotive and consumer electronics companies.

Russia-based IntegrIT has ported its NatureDSP Math Library to Tensilica’s baseband DSPs. The traditional emphasis on science and math is still alive and well in Russia—and expanding into some new markets. IntegrIT develops signal-processing routines for DSP functions.

By Ed Sperling
Synopsys created the first TLM Web portal, complete with an initial offering of 600 models, and inked a deal to distribute ARM’s Cortex processor models from its new TLMCentral site. Synopsys said it hopes the portal will spur investment in virtual prototyping.

Mentor Graphics won a deal with Fujitsu for its embedded software development environment, which will be used for Fujitsu’s general-purpose 32-bit microcontrollers. What’s interesting here is that Fujitsu chose Mentor’s Embedded Sourcery CodeBench for ARM’s microcontroller IP, which will be included in the Fujitsu product. It’s an unusual keyhole into the microcontroller space.

ARM cut another deal, too, which must have had the corporate lawyers hopping. Open-Silicon signed a multi-year agreement to license a broad portfolio of ARM technology, which allows Open-Silicon to offer ARM’s IP with its own design and manufacturing services. We may be witnessing a change in the wholesale distribution model.

Tensilica inked a deal with Fraunhofer IIS, which allows Erlagen, Germany-based Fraunhofer to become a design center partner for Tensilica’s HiFi Audio DSPs. Fraunhofer, incidentally, is part of the Fraunhofer-Gesellschaft research organization, which is partly funded by the German government.

ST-Ericsson reportedly gained a 10x improvement in time by using using Cadence’s mixed-signal flow for its 40nm baseband chip. Create automation tools for analog engineers, force them to hit tight schedules within budget, and apparently they’ll use these tools.

By Ed Sperling
Summer is over, literally and figuratively.

Mentor Graphics extended its collaboration with NuFlare Technology for advanced mask generation, combining the Calibre DFM suite of tools with NuFlare mask writers.  Mentor also moved into Brazil with a Portuguese language version of PADS for designing PCBs, which gives an interesting indication of where that market is heading. It also rolled out new ATPG tools for test and is working with ARM for testing ARM processor-based designs.

Synopsys beefed up its own ATPG tools with a volume diagnostics flow and improved yield ramping.

Altis Semiconductor, the French specialty foundry, is standardizing on Cadence’s MaskCompose reticle and wafer synthesis technology. Shanghai-based Giantec Semiconductor has adopted Cadence’s Encounter and Virtuoso flows.  And Fujitsu is standardizing on Cadence’s DFM technology for 28nm and mixed-signal designs. In addition, Cadence introduced DFI 2.0-compliant design and verification IP.

Sonics rolled out the gigahertz version of its network-on-chip NoC technology, which provides lots of headroom for future derivative chips and stacked die. For anyone worried about a communications bottleneck, this should silence all fears.

By Ed Sperling
MIPS has positioned itself head-to-head with ARM in the Android world, adding yet another competitor. The other one is Intel’s Atom, of course. MIPS stake on this one involves a smartphone that passed the Android Compatibility Test Suite.

Moortec Semiconductor taped out its embedded temperature sensor IP using TSMC’s 40LP and 28HP processes and Synopsys’ custom design solution. Who says analog isn’t migrating down the process curve? Moortec is based in Plymouth, U.K. 8

TSMC’s net sales, which are a good indication of how the semiconductor industry is faring, were down 0.7% from April to May—basically flat—but they are still up 6.3% from last May, which was well into the recovery period. Revenue was up 12.2% in the same period compared with 2010.

GlobalFoundries, meanwhile, swapped out its top leadership team. Ajit Manocha will replace Doug Grose as acting CEO. James Norling will become executive chairman and Ibrahaim Ajami the vice chairman, while COO Chia Song Hwee—former CEO of Chartered Semiconductor, which was acquired by GlobalFoundries—will leave the company in August.