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The Evolution of TrustZone in an Insecure World

Thursday, January 22nd, 2015

By: Caroline Hayes, Senior Editor

If it’s important it should be kept safe—this maxim applies universally to data and operating systems, but just how to keep something safe effectively has changed, as data and operating needs have changed. This article looks at the evolution of the hardware isolation technology, TrustZone, and how it has evolved since its introduction, over a decade ago, to cater for new levels of data tasks and attack.

The launch of TrustZone was at London’s Tower of London, in 2003, where visitor attractions include the Crown Jewels (Figure 1). “This was a fitting venue,” says Rob Coombs, security marketing manager, ARM®, “Castles have keeps and moats to isolate and reduce the area of attack, protecting precious assets with layers of security.”

Figure 1: The Tower of London, where ARM launched TrustZone in 2003. (Image by Thomas Bredøl, www.bredol.dk/photo/ , courtesy Wiki Commons.)

Four Layers of Security

TrustZone is ARM’s hardware isolation technology that is OS-neutral and reduces the attack surface and increases isolation. There are four levels to security on high-performance computing platforms. The first is the “Normal World,” i.e., the normal operating state for the OS and applications software. (It is referred to as PL0/PL1 in the ARMv7 architecture or EL0 or EL1 in ARMv8.) Here, processes or applications are isolated from each other by the OS and the Memory Management Unit (MMU), and each executing process is isolated from others.

There may also be a hypervisor, which has hardware support and its own Exception Level (EL2) in the latest 64/32-bit ARMv8-A processors. A hypervisor allows multiple instances of an OS to execute on the same processor as a virtual machine. Each virtual machine can be isolated to protect and secure resources or assets from other virtual machines.

The “Trusted World,” a hidden, Secure World, is based on hardware isolation provided by TrustZone technology. the Secure World typically runs a small, certifiable microkernel alongside, and independently of, the much larger, main OS. In this mode, the area of code that is security certifiable is reduced to 100s of kbytes, rather than Gbytes, says Coombs. the software responsible for the switching between Normal World and Secure World runs at Secure EL3. The TrustZone security extends across the chip and physically partitions the system into secure and non-secure components. This isolates some parts and ensures that software operating within the normal OS cannot directly access Secure World assets, such as memory or peripherals.

Finally, a secure element is often included in the system and may include an ARM SecurCore® processor to provide a physically separate, tamper-proof IC that is protected against physical and software attack, thus increasing both levels of protection and levels of isolation to reduce the area of attack.

Figure 2: A typical processor, combing a TrustZone-based Trusted Execution Environment (TEE) and hypervisor.

“There are two ways to look at security,” explains Coombs. “Protection against threats and delivering better user experiences, or computational trust, which builds on strong authentication of users and devices.”

Evolution Stages

The first use case of TrustZone isolation is for a trusted boot. “Not glamorous,” says Coombs, “but necessary.” He goes on to say “People need a trusted boot that is hidden away, and that will make it difficult for others to attack at this critical stage of set up.”

Security designed into the hardware, as is the case with TrustZone, means that it is an inherent feature of a device, and security applications can be built that run on the secure kernel, without affecting system performance.

[Editor-in-Chief, Embedded; Extension Media Chris Ciufo speaks to ARM’s Zach Shelby about other security protocols for mobile and IoT devices at http://eecatalog.com/IoT/2014/12/08/talking-iot-beyond-the-silicon-architectures-protocols-and-standards

and Marc Canel about securing the IoT at http://eecatalog.com/chipdesign/2014/12/09/securing-the-iot-from-silicon-to-system-an-interview-with-arm%E2%80%99s-marc-canel-vp-of-security-technologies/

From 2009/2010, over-the-top (OTT) content, for example Digital Rights Management (DRM) used in streaming media was the target for secure operations—and the second evolution stage of ARM’s TrustZone. This could be an iPlayer, film services like Netflix, mobile or smart TV, explains Coombs. The OS-neutral TrustZone allows the device to protect DRM and its crypto keys enabling the decode of premium content for secure over-the-top services.

Enterprise Security

As the lines between work and social use of mobile devices blurred, the nature of securing content had to keep pace. This created the need for the third stage of evolution, enhanced integrity management. In 2013, Samsung introduced KNOX on the Galaxy S4 smartphone, recognizing the Bring Your Own Device (BYOD) trend in workplaces. The Enterprise and Government category is the fourth stage in the evolution of TrustZone, says Coombs. It offers higher integrity of execution, he adds.

Part of the Samsung Approved For Enterprise (SAFE) program, KNOX compartmentalizes the work and personal areas on the phone, with management systems and security capabilities. The initial KNOX platform had Security Enhanced Android, to separate the personal and professional areas on the phone; secure boot whereby only verified software can run on the device; and TrustZone-based Integrity Measurement Architecture to protect the kernel. The password protected work area encrypts any data stored on it and allows IT staff to work on files without deleting content in the personal area.

Figure 3: Overview of Samsung KNOX platform security (image from Samsung KNOX Premium white paper, September 2014 - http://www.samsung.com/uk/business/insights/white-paper/).

At Mobile World Congress 2014, Samsung introduced KNOX 2.0 with biometric authentication, management systems and customization features, on the Galaxy S5 smartphone.

A fourth stage in the evolution of TrustZone is a new market for security hardened apps. Trustonic (https://www.trustonic.com/about-us/what-we-do), a joint venture between ARM Secure Services Division, Giesecke & Devrient and Trusted Logic Mobility, has integrated enabled Over the Air (OTA) downloadable Trusted applications that run on the Trusted Execution Environment (TEE). Its t-base TEE isolates and protects assets (pass codes, fingerprints and certificates) for secure digital tasks, such as payments, OTT content and for work tasks.

Trustonic sells access to service providers to enable devices manufactured with a root-of-trust and TEE. Trusted apps are installed by the OEM or later as Over The Air (OTA) apps. Access is provided on demand as and when service providers need to install TEE protected applications.

Apps typically have most of their functionality in the Normal World but may have critical or sensitive operations provided by a separately installed Trusted App in the hardware isolated Secure World, e.g. for encryption or secure storage. This does not affect performance as the secure world operations are normally non-blocking to normal world processes.

A Password-less World

Passwords are commonly used but are vulnerable and fraught with problems, going forward. “They are weak in a number of ways,” says Coombs. “People choose “easy” words and reuse them across multiple websites, hackers find them easy to phish: they are not strong enough to protect your digital lives. Once the account is taken over, it can be used as a gateway to get more credentials.” A stronger, simpler solution to authentication is needed.

Figure 4: TrustZone TEE is where a trusted Fast Identity Online (FIDO) Trusted app can protect sensitive operations such as key management and storage.

He believes that FIDO Fast Identity Online (FIDO) is a better solution (Figure 4). The FIDO Alliance was formed in 2012 to create specifications to define open, interoperable and scalable mechanisms to replace passwords for online authentication. FIDO embraces the idea of multi factor authentication, i.e. the use of different types of authenticator, such as fingerprint sensor or PIN entry, via a trusted touchscreen that only provides information to the TEE.

“TrustZone and TEE are a good way to implement FIDO secure peripherals,” says Coombs. “The FIDO world app can be for key generation, storage, communication to the fingerprint driver or the touchscreen. I am expecting most of the mobile phone based FIDO implementations this year to use the integrity and confidentiality that the TrustZone based TEE provides.”

FIDO offers the exciting future of a world without passwords and the TrustZone based TEE is a great way to implement it,” he confirms.

Although FIDO Version I specifications are in place now, Samsung was an early adopter and used the draft specification for PayPal transactions on its Galaxy S5 for pay by fingerprint (Figure 5). Coombs says there is a lot of momentum behind FIDO, and is expecting a lot of take up, with an acceleration of adoption by OEMs in 2015 leading to it being mainstream by 2016.

Figure 5: Secure payments can be made using FIDO.

ARM Trusted Firmware

Another prospect for 2015 is the introduction of many ARMv8-A 64/32-bit based platforms. To help reduce the complexity of the low level secure software, ARM has created an open source project which can be found on GitHub: ARM’s Trusted Firmware. Version 1.0 was released last year and version 1.1 is scheduled for the end of January. The low-level, highly privileged Secure World software for ARM v8A is provided as an open source code (Figure 6) with a permissive license. It enables a common layer of software that silicon partners can use as a reference implementation for Trusted Boot and the interface layer to a trusted OS.

Figure 6: ARM Trusted Firmware for 64bit ARM v8A architecture reduces the integration workload in secure OS development.

The work to ensure secure, isolated areas to protect precious code and data continues today, more than 10 years after TrustZone was launched. It plays a significant part in the front line of defense against malicious attack.

This article was sponsored by ARM.

Smart ARM MCU Steps Up without Compromise

Thursday, January 22nd, 2015

By: Caroline Hayes, senior editor

ST Microelectronics has won the race to produce the first ARM® Cortex®-M7 32-bit microcontroller. Announced nearly simultaneously with ARM’s announcement of the Cortex-M7, ST’s STM32 F7 series MCUs are scalable and pin-compatible with the earlier F4 series and promise to reduce time to market for embedded developers.

It is intended for highly demanding MCU operations and is, says Renaud Bouzereau, STM32 High Performance MCU Marketing Manager, STMicroelectronics, a “quantum leap from the F4 series, the previous performance champion within the Cortex-M market.”

The Cortex-M7 is scalable, opening up possibilities to access the F4’s 500-plus parts catalog for development opportunities across embedded, industrial, medical and IoT applications. The compatibility saves developers having to optimize code for use, thereby decreasing the time to market.

Increasing Connectivity

A significant feature of the STM32 F7 series is the new set of peripherals, such as a dual clock domain to reduce the system’s and CPU’s speeds independently from the peripherals to lower power consumption. The peripherals and I/Os are connected to two Advanced Peripheral Buses (APBs), two Advanced High-performance Buses (AHBs) and a 32-bit multi-AHB matrix. Additionally, STM has implemented a multi-layer, 64-bit wide AXI bridge to the multi-AHB matrix to access different masters, whether general-purpose DMAs, a dedicated DMA or a graphics accelerator, to efficiently exchange data over the entire system (see Figure 1).
The core has a single floating point unit (SPFU) to support single-precision data processing instructions and data types. This can be exploited in industrial applications where real-time data processing plays an increasingly important role as well as in some emerging IoT applications.
Memory is a major part of the STM32 F7 and will play a role in finding new applications for a “smart” MCU. The series is offered with Flash memory up to 1 MByte, 320 kByte of SRAM, which includes 64 kByte of data tightly coupled memory RAM for critical, real-time data, 16 kByte of instruction tightly coupled memory (TCM) RAM for critical real-time routines and 4 kByte of back-up SRAM available in the lowest power modes.

Figure 1: The STM32 F7 has 50% more processing power than the earlier STM32 F4, yet with the same low power budget.

Creating a smart MCU is not about brain size, says Bouzereau, but about assembling the right embedded features and connecting them the correct way around the core to deliver a smart solution. The STM32 F7 does this with the inclusion of the company’s Chrom-ART (Adaptive Real-Time) graphics accelerator, which allows zero wait states from the embedded cache to increase performance for data transfer. An L1 cache enables performance from either internal or external memory to further increase design options (see Figure 2).

The F7 devices are pin-to-pin compatible with the earlier F4 MCUs. With over 500 parts, this allows developers to access a plethora of MCUs—from entry-level to high-performance. For Bouzereau, this allows extra room for performance innovation as well as reducing time-to-market, with the developer able to spend less time on optimizing the MCU for resources and performance targets.

Laurent Vera, EMEA Microcontroller Marketing Director, STMicroelectronics, explains that the FM32F7 nearly doubles the CoreMark of the earlier STM32F4 from the company. The F7 achieves a CoreMark of 1,000, whereas the F4 achieves 600 CoreMark. “This is pure processing power,” says Vera. The customer can process their own algorithm for their own IP, he continues, to add functionality.

One example is IoT applications, where connecting to a network pushes the performance of products. He cites the example of the smart meter. The STM32F4 can be used in a smart meter, but as the complexity increases with the advent of the smart grid, the F4’s 180 MHz operation can be exceeded with the 1 MByte Flash, 320 kByte SRAM F7. Vera explains that the F7’s Flash-SRAM ratio increase delivers more SRAM connectivity, allowing devices to process more data, in line with the trend for data-hungry, connected devices.

Power Management

Another example where connectivity is key is the connected watch or wearable device. When an update is available, the device can be updated via software. “Adding a microcontroller can bring new features live by updating the firmware,” he says. At present there are build issues with a smart watch, using a microcontroller, explains Vera. Users have to recharge batteries every day. “Now, a smart watch built using a microcontroller allows the battery to last longer. The F7 system-based solution smart watch lasts at least five times longer—this has been achieved by some customers in sport watches,” he confirms. Using the F7 adds functionality, for example a driver for a display or Internet connection. “The limit is the IP and creativity of the hardware and software developers,” he says.

For example, in a ray tracer comparison, two STM32 F439 evaluation boards run the same 3D demonstration. One uses the STM32 F4, based on the ARM Cortex-M4, running at 180 MHz, and the other is equipped with an ARM Cortex-M7-based STM32 F7, operating at 200 MHz. The high levels of picture computation use DSP and FPU to process three different types of data. The F7 board completed the task in 22173 ms, ahead of the F4 board, which completed the compute-intensive operation in 40244 ms.

Figure 2: The STM32 F7 embeds features and connects them around the ARM Cortex -M7 core.

Performance increase is not at the expense of power efficiency, insists Bouzereau. “We reached this step-up in performance with no compromise on power efficiency,” he says. “We achieved the same dynamic power consumption, executing code form embedded memory with 7 CoreMark /mW at 1.8 V and 180 MHz on both F4 and F7 and kept the same low-power mode, with stop mode, down to 120 µA typical with all SRAM and contacts saved.”

For software support, the proven Java and ARM mbed™ tools are available, together with STMicroelectronics’ Nucelo boards and STMicroelectronics’ partners’ solutions.

Target Applications

The level of functionality offered by the STM32 F7 means that developers no longer have to consider a split between the MCU and the DSP when developing applications. The result of this merging of disciplines is a reduction in complexity, size, power consumption and cost. This reduction will have obvious benefits in consumer devices, where small form factors and power efficiency are key metrics.

They will also be advantageous in medical devices, which share many of the same demands and where a human machine interface (HMI) may be required. The boost to audio and graphics processing will also mean that medical devices can have enhanced capabilities in a small, power-efficient format. Another use is as an industrial gateway or motor control, where real-time operation is important.

Roadmap

The STM32 F7 is sampling now and has been released to privileged customers, with general release scheduled for the first half of 2015, confirms Vera. It is based on a mature, 90nm process, initially, and the first model operates at 105 °C, which is lower than the other STM32 devices, which operate at up to 125 °C.

The next generation of F7 will achieve double the CoreMark rating, according to Vera, achieving 2000 CoreMark, which is possible on an ARM Cortex-M7 running at 400 MHz.

This article was sponsored by ARM.

Why ARM makes development tools: Interview with Hobson Bullman

Wednesday, January 21st, 2015

By: Chris A. Ciufo, Editor-in-Chief, Embedded, Extension Media

As 2014′s ARM TechCon wound down, I sat down with a relaxed Hobson Bullman, general manager of ARM’s Development Solutions Group. He was at ease, satisfied with the company’s recent 1-2-3 red hot announcements: the new ARM® Cortex®-M7processor, HP’s Moonshot enterprise server based upon an ARM core and a new emphasis on OpenCL and safety applications in ARM’s DS-5 tools. Edited excerpts follow.

—Chris “C2” Ciufo, editor

Summary quotes from the interview:

  • It’s revolutionary, we find, because the Streamline™ [profiler] helps people solve system performance issues.
  • While CPUs have had performance counters for a long time, more and more the fabric is getting some performance counters as well.
  • Strong visibility of OpenCL on the CPU and the GPU is a new thing for this year.
  • Recently announced at TechCon is a new safety focus for our compiler.
  • Safe systems are getting more intelligent.
  • Tools are strategic to ARM. Without tools you have nothing.
  • ARM-based servers are here and it is very, very exciting.

Chris Ciufo: Why does ARM have tools at all? Why not rely on your credible tools partners?

Hobson Bullman: Tools are strategic to ARM. Without tools you have no software and without software you have nothing, right? Two things are important. It is important to have a vibrant ecosystem of tools, but it is also important that ARM has its own tools so it is not too dependent on the ecosystem. For example: this is critical when introducing new architectures or new IP.

The ecosystem is not going to be up to speed as quickly as we are, and it’s easier for me to release products early. I will support everything ARM does whereas the ecosystem is quite rightly driven by the markets, which will pick and choose based on the domains where they are strong.

I provide a standard level across everything that ARM does, I keep to the core and build the fundamentals. What you find with our very important ecosystem partners is they will pick a segment, and thus they will support that really well. And they will go further than I go in that segment. There will be more plug-ins, more add-ons and more specific things. An example might be that they might have their own MISRA C checkers. I don’t have a MISRA C checker; I integrate with a third-party one.

My mandate is to make sure that ARM, the architecture, has the best possible tool support, whether or not it comes from ARM, the company. So I have people in the organization who are working with a partner to make sure that we are enabling the partnership with all the information they need at the right time so that the third-party system is strong. And I have people in my organization who work on my products. What is important for ARM is that the whole view is strong. You could argue that maybe ARM wouldn’t need to invest in the ecosystem while funding everything, but we have seen architectures in the past that took that approach and it’s quite a weak approach because you can’t introduce new products that way. That [approach] just depends too much on the ecosystem. We believe we have found, over the last 20 years, exactly the right balance.

C2: Hobson, tell me. What is DS™-5?

Bullman: DS-5 is an integrated development environment (IDE) for developing software on ARM. What is special about it is the way we have got full coverage, not only of all of ARM’s CPUs and GPUs, but also we cover all stages of development flow from virtual prototyping down to final product. So we make sure we can provide a single IDE and you can connect what you are doing. [That’s the case] whether you are doing RTL simulation or RTL emulation and whether you’re doing virtual prototyping on some kind of software model or connecting to an FPGA or a final piece of silicon. Whether that final piece of silicon has debug or trace or JTAG or nothing at all, we have the right sort of connections for these different stages in the flow.

Because what we find with ARM is the partnership produces an enormous variety of devices, which is exactly the purpose of us providing some key technology from ARM and then you differentiate around it, you build your devices, 1, 2, 4, 8, 16 cores, with a mixture of our products. There might be Cortex-A, Cortex-R, Cortex-M mixed with third-party IP on there for DSPs for CPU and for data path accelerators. As an ARM tool kit builder, I have to support the people closest to ARM, which is the silicon companies, but if I build a tool kit which is applicable beyond that, it helps the silicon companies then work downstream with their OEMs, and then they work with the software developers and eventually the apps developers. A single flow is really designed to help everybody with time to market.

C2: Specifically, what’s in DS-5?

Bullman: DS-5 has tools you’d expect, and some that might surprise you. We start with a complete compiler tool chain consisting of compiler, linker, assembler, debugger and so on. We have a multicore heterogeneous debugger that can do SMP and AMP with [a] very high degree of configurability. SMP is clearly important for things like Linux and Android use cases, but AMP is absolutely critical if you want to have any hope of cross triggering or understanding of your cross process independencies. So, we offer a full-fledged multicore heterogeneous debugger. Alongside that we have a profiler, actually a system profiler, called Streamline.

C2: I’m unfamiliar with your profiler, Streamline.
Bullman: It’s the poster child. It’s a development I’m very proud of, and the innovations in the debugger make multicore work very well. We think we have solved some of the ease-of-use issues around multicore and tool configuration. Streamline’s innovation is new; there isn’t anything else like it actually.

Specifically, it’s a full system-level profiler for CPU plus GPU plus fabric with full visibility on the timeline with all of the software, and we have hooks into the runtime environment. So if you’re running on the system [something] like OpenCL, you have visibility of the software status as well. It’s revolutionary, we find, because Streamline helps people solve system performance issues. And really tools are here for three things: time to market, engineering productivity and system performance. And everyone knows that compilers help the system performance, but these days, actually the software architecture is at least as important as getting a good compiler, and we struggled with that until we invested seriously in a system profiler.

We find that multicore and system issues in the fabric—the cache-coherent fabric, whether it is interconnect or network—plays a bigger and bigger part in the performance of a system. This system performance problem moves from being purely about computation to at least as much about communication, so we have moved Streamline from being a purely CPU tool like our previous profiler to a system-based tool.

C2: Please cite an example use case for system-level profiling; that is, can it help in optimization?

Bullman: It can, because of the features that are in the ARM IP for performance measurement. So, Streamline can only help as much as the fundamentals of the IP give you the data. A good performance analyzer would give the right data in the right place, but you have to get the data first of all. Where did the data come from? Some of it comes from Linux, which as an OS has got a whole bunch of information about how well things are going. But, for an ARM-based SoC it’s very important to get the data from the SoC itself. So the CPUs have had performance counters for a long time, but more and more the fabric is getting some performance counters as well. So you can get metrics from the interconnector, or the network on chip, which includes information [about] cache hits, cache misses, where the traffic’s going and where the bottlenecks are.

By the way it’s not a new tool. It’s maybe four years old but what’s new this year is OpenCL. So, there have been some announcements this week from ARM around OpenCL for NEON™, and Streamline supports this SIMD vectorizing engine used today for multimedia accelerators. So in Pete Hutton’s keynote we spoke about load balancing effectively using OpenCL to partition your software for maximum system use. Some of it on the Mali™, some of it on the CPU’s NEON unit. OpenCL is ARM’s language of choice for doing that, and ARM decided that good support for OpenCL would be a good broadly applicable approach to solving this problem. So strong visibility of OpenCL on the CPU and the GPU is a new thing for this year.

C2: ARM has added DSP functions and associated partner libraries to the Cortex-M7, perhaps as part of the company’s move to a “higher level of abstraction” to make designs easier. Can you comment?

Bullman: We find that people use these higher levels of abstraction and can effectively devolve some of the creation in these bits of targeted software to libraries and tools that are above the classic C/C++ level. So, it’s not a core part of what [my team] does, but it is an important part of the ecosystem, so we make sure we have good integration with these third-party tools.

I think Mathworks that makes MATLAB, for example, could use tools that can be very much applied to the ARM-based world, so my role is to make sure that those tools integrate with my tools—not DS-5 yet but with the microcontroller-focused Keil® tools, which is another tool chain that I have. We have had integration with MATLAB for a while now because they’re found in the industrial use cases and people tend to use them for time-to-market reasons. My group acts as an enabler to get these integrations right.

C2: Besides with libraries and third-party add-ins, to what extent do your tools enable that higher level of abstraction from a software or a coding standpoint?

Bullman: Higher-level abstractions are quite domain-specific. Particular market segments adopt high-level tools whether it is a Python scripting approach or a UML-based modeling flow with UML code generation. And so again our approach is to try and partner with the right people for that. And either that’s through taking our shrink-wrapped products and integrating on top, or it’s through subcomponent licensing. So, if there’s somebody out there maybe in the graphics space, in the gaming space, there are plenty of higher-level tools and game engines that people use, and then they can get by and do that with great support for ARM and Mali, sometimes with licensing components from ARM, but often without needing too much help at all.

C2: To what extent do ARM’s tools enable security?

Bullman: In two ways. One: specifically with TrustZone® on the hardware side. Because there are definitely tool systems that help throughout the TrustZone. And secondly: there’s a purely software quality side to your question.

Regarding TrustZone, we work closely with ARM’s people writing trusted operating systems to make sure that the tools are able to help those OS vendors create both a secure side and the non-secure side of their system. Once the secure side is created, that tends to be locked down, and then their customers use it to access the insecure (or “non-secure”) side. But, there is a lot of work to be done in engineering to get these two sides working and communicating over a secure channel. So, we put support in our tools for the secure side that mainly targets those secure OS vendors to make sure they can create the right operating system.

On general software quality there is lots going on, actually. We do have partnerships, and we have partnerships with static analysis companies such as Coverity, for example. So there’s integration between Coverity and the DS-5 tools. On the Keil side for microcontrollers we find that there are even things like Lint tools that make a big difference, even in the 21st century.

And recently announced at TechCon is a new safety focus for our compiler. This is not quite “security;” it’s safety. We find that as the state-of-the-art for safety keeps rising, and as ARM starts to get more into safety, people are demanding more from the tools in order to satisfy their own audiences to assure that the product they are creating with the tools is safe.

We take our guidance on providing safe supporting tools from the IEC 61508 standard and from ISO 26262. For both of these standards we have done a couple of things to make our customer’s life easier. We produced a set of artifacts around the compiler, which explains how we built the compiler and how we test the compiler. It also explains how we deal with bugs, it explains our development process, and there is a safety manual that explains how you, the customer, can use these things safely—which options you might want to use without being too concerned. We provide as much information as we can; the information artifacts are in a 200-page set of books.

C2: Why the emphasis on safety?

Bullman: The customer wouldn’t read that big set of documentation, if he or she didn’t need to read it. But more and more the customer needs to read it because safe systems are getting more intelligent. For example, we have customers who have used these artifacts for projects that are covered by US FAA standard DO-178B/C. We have gone one step further with 61508 and 26262 in that we have worked with the certification body in Germany called TÜV SÜD. We have worked with them over the last few years to provide an independent assessment of our collateral, which is indeed suitable for these two particular standards.

We are happy that people apply [our artifacts] to many other standards as well, and we think that it is important to have an independent view on this. We are very proud of what we have done, and an independent point of view gives a customer more confidence.

C2: Any final comments?

Bullman: I will talk a little bit about one segment we are active in, which is enterprise infrastructure. ARM is investing a lot in this market. At TechCon you heard about HP’s first server to use the ARM architecture. Their Moonshot program has been in the works, and [in October at TechCon] it was announced to be available. ARM-based servers are here and it is very, very exciting. Whenever there is a new market that ARM enters, then we have to make sure we are supporting the silicon partners and OEMs at the beginning of that market.

While a lot of what we do in tools is around our more established markets like mobile and embedded, we make sure that the tools are right for these new markets as well. In the case of enterprise and servers, heterogeneous and large multicore systems are clearly very important in this infrastructure domain. Where you have multicore devices and [things like] specialist accelerators, there will be a requirement for tools. Look at the [now open source] DPDK that is important in this space.

We’ll have third-party and silicon IP sitting in the corner of the chip with the ARM architecture around it. So one of the things we do, which perhaps is not always visible, is working on that leading edge of those segments to make sure ARM is well supported. Many of the features in DS-5 are beneficial for mobile, but they’ve also been put in place to deal with large fabrics and large connected systems. The growth environment in new markets is just as exciting as the rapid developments we’re seeing on the smartphone side.

This article was sponsored by ARM.

Blog Review – Monday, January 19 2015

Monday, January 19th, 2015

Test case for lazybones; Mongoose in space, heads for Pluto; solar tracker design; new age shopping; IoT insight – the real challenge

The size of SoCs, security around EDA tools and the effort needed to test tool issues are all hurdles that can be mounted, asserts Uwe Simm, Cadence. His comprehensive post explains how the Test Case Optimizer (TCO) – a small generic (as in no special tools required or design styles are required) – can strip down simulation source files and reduce overal source input data size by over 99%.

After a stellar break, NASA’s New Horizons spacecraft reached Pluto. Not only does it have the ashes of astronomer Clyde Tombaugh, the discoverer of Pluto, it has a Mongoose on board – in the form of a MIPS-based Mongoose-V chip. Alexandru Voica, Imagination, tells us more about the rad-hard device manufactured by Synova.

An interesting project, and a worthy one too, is relayed in the blog post by John McMillan (Mentor Graphics). Cool Earth Solar designs and develops solar products and uses PADS to develop some of the monitoring hardware for the equipment that tracks the sun, and transmits data for the project.

A subject close to my heart, shopping, is explored by David McKinney, Intel, who has a guest blog from Jon Bird, Y&R Labstore. How to harness the data that make up shopping patterns, without freaking out shoppers. A startling obvious observation is “Retailers must first and foremost be shopper-centric” but what does that mean in the digital age and the Internet of Things era?

Demonstrating a helpful nature, David Blaza, ARM, points us to a report by McKinsey, about the Internet of Things. As well as Blaza’s observation relating to ARM’s Cortex-M devices on the edge of the IoT and ARM Cortex-A at the hub and gateway level, I was struck by Joep Van Beurden’s observation that the IoT is not about prices or power but connecting the hardware in a smart way to the cloud.

By Caroline Hayes, Senior Editor

Smart Bluetooth, Sensors and Hackers Showcased at CES 2015

Wednesday, January 14th, 2015

Internet of Things (IoT) devices ranged from Bluetooth gateways and smart sensors to intensive cloud-based data processors and hackathons – all powered by ARM.

By John Blyler, Editorial Director

Connectivity continues to be a major theme at the International Consumer Electronics Show (CES). The only difference each year is the way in which the connectivity is express in products. For example, this year’s (2015) event showcased an increase in gateway networking devices that permitted Bluetooth Low Energy-equipped gadgets to connect to a WiFi router or other interfaces with the outside world.

According to a recent IHS report, the global market for low-power, Bluetooth Smart integrated circuits (IC) will see shipments rise nearly tenfold over the next 5 years. This is good news for very low power wireless semiconductor intellectual property (IP) and device manufacturers in the wearable and connected markets. One example out of many is Atmel’s BTLC1000 chip, which the company claims will help improve battery life by over 30% of current devices. The chip architecture is based on a ARM® Cortex®-M0 processor.

Bluetooth Smart is the intelligent, low-power version of traditional Bluetooth wireless technology that works with existing smartphone and tablet applications. The technology brings smart connectivity to every day devices such as toothbrushes, heart-rate monitors, fitness devices and more. (See, Wearable Technologies Meet Bluetooth Low Energy)

For the IoT to be useful, sensor data at the edge of the connectivity node must be communicated to the cloud for high performance processing of all the IoT data. This year’s CES showcased a number of multicore 64-bit devices like NVIDIA ARM-based Tegra X1. Another example of a high-end computing system is Samsung’s Exynos 5422 processor that is based upon ARM’s big.LITTLE™ technology and contains four Cortex-A15 cores and four Cortex-A7 cores. These types of products can run Android and 4K video displays on a 28nm process node.

Team mbed

Many embedded software developers enjoy the challenge of creating something new. Today, it is fashionable to call these people hackers, in part because they exhibit the prerequisite mindset, namely, “one who programs enthusiastically…”  – from the Hacker’s Jargon File, circa 1988.

Special events called hackathons have been created for these enthusiastic programmers to practice and demonstrate their skills. For example, back in August of 2014, ARM provided a group of hackers know as Team mbed™ with hardware and software development platforms for the AT&T Hackathon at Super Mobility Week. Last week, Team mbed returned to participate in the ATT Hackathon at the CES 2015. The team consisted of Internet of Things (IoT) industry participants from Freescale, Multi-Tech, Nordic Semiconductor, STMicroelectronics, u-blox and ARM. The team was supplied with a number of cool resources including ARM mbed-enabled development boards, connectivity modules, and a variety of different actuators and sensors. These resources combined with available guidance and inspiration enabled the developers to bring their own ideas to reality.

Following the show’s IoT theme, these software developer were given a ‘smorgasbord’ of sensors and actuators to go along with a variety of hardware platforms and I/O connectivity subsystems including Bluetooth®, cellular, Ethernet, and Wi-Fi®.  Recent projects are built around this IoT platform are highlighted at haster.io/mbed (see Figure 1).

Figure 1: Krisztian Flautner, GM of IoTBU at ARM, discusses this new mbed offering that sets out to simplify and speed up the creation and deployment of Internet of Things (IoT) products

Next to connectivity, sensors are the defining component of any IoT technology. Maybe that is why sensor companies have been a growing presence on the CES show floor. This year, sensor-related vendors accounted for over 10% of total exhibitors. Many new IoT sensor technology is implemented using tiny MEMS physical structures. At CES, a relatively new company known as Invensense announced a Sensor System on Chip that combines an ARM Cortex-M0 processor with 2 motion co-processors (see Figure 2). This combination enables a 6-axis motion measurement all in a 3mm x 3mm x 1mm package. To complete the package, this device has its own RTOS that is compatible with Android Lollipop.

Figure 2: InverSense chip with sensors.

Such sensor systems on chip would make a fine addition for the resources available for Team mbed at their next hackathon.

Blog Review – Monday, January 12, 2015

Monday, January 12th, 2015

New year resolutions from ARM, IP Extreme; CES highlights from Cadence, Synopsys, ARM partners; Mentor looks back at 2014; Imagination looks ahead

It wouldn’t be a January Blog Review without a mention of resolutions. Jacob Beningo, ARM, is disappointed that DeLoreans and hover boards are not filling the skies as predicted in Back to the Future, but he does believe that 2015 should be the year of sound, embedded software development resolutions.

A challenge is thrown down by McKenzie, IP Extreme, to ensure the company meets its new year resolution to update its blog. If you find that the company has missed posting a blog by midnight Wednesday (Pacific time) you can claim a $100 voucher for a chop or restaurant of your choice.

It wouldn’t be the week after CES, if there were no mentions of ‘that show’. Michael Posner, Synopsys, looked beneath the cars, entertainment devices and robots to focus on sensors (and to mention DesignWare Sensor and Control Subsystem, which designs them).

Brian Fuller, Cadence, interviews Martin Lund, senior vice president for Cadence’s IP Group, at CES. Lund has some interesting observations about audio and video demos at the show and insight into the role of IP.

ARM was everywhere at CES, and Brad Nemire, ARM, has some great videos on his blog, with demos of partners’ devices, and also a link to a Bloomberg interview with CEO Simon Segars.

International finance was not covered at CES, but the mobile money payment services described in the blog by Catherine Bolgar, Dassault Systemes has a lot of ‘CES criteria’, connectivity, innovation and commercial applications, as well as the Vegas connection with cash. It is an enlightening view of how technology can help those without deemed to expensive to reach and service by conventional banking institutions.

Looking back at 2014, Vern Wnek, Mentor, considers the overall winner of the longest running EDA awards, the Technology Leadership Awards, Alcatel-Lucent. The award winnning project was the 1X100GE packet module includes 100Gb/s of total processing power and signals operating at 6/12/28GHz.

A world without wired cables, is the vision of Alexandru Voica, Imagination, who checks just how close a cable-free life is; encouraged with some introductions from the company, of course.

By Caroline Hayes, Senior Editor.

Blog Review – Thurs, January 08 2015

Thursday, January 8th, 2015

CES, no I mean CPS; CES 2015, 2016 and beyond; Connected cars at CES; ISO 26262 help; Constraint coding clinic

No doubt anticipating a wearables deluge at CES, Margaret Schmitt, Ansys, cleverly uses this to her advantage and tailors her blog, not to ‘that Vegas show’ but to arguing the point for CPS (Chip Package System) co-analysis for shareable, workable data. She also avoids all mention of CES but reminds readers that the company will be at DesignCon later this month.

This time of year it is always a trial to find decent blog material. If it’s not a review of 2014, it will be preview of trends at CES, but some bloggers do it well. David Blaza, goes behind the glitz and straight to the semiconductor business of CES. He takes the view that looking at devices being launched will reveal more about CES 2016 or 2017 than this week’s show.

Sounding a little world-weary (or is that Vegas-weary?) Dick James and Jim Morrison, ChipWorks, fought the crowds at CES Unveiled, the press preview. Their tech-fatigue is entertaining and they also came up with five top themes. Most you could guess but the connected car is a new addition. It is a theme embraced by Drue Freeman, NXP, which is not surprising as the company is showcasing its RoadLINK secure connected car technology in Vegas this week.

Intel CEO Brian Krzanich delivered a keynote at CES, illustrating how computer and human interactions are vital in this world of mobile computing everywhere. Scott Apeland refers to it in this blog about Intel’s RealSense technology and his enthusiasm knows no bounds. He includes descriptions of application examples and has sympathy for ‘those who haven’t had the good fortune’ to try the technology first hand. All that can be put right at the company’s booth.

This industry is the kind that wants to share and help fellow engineers and Kurt Shuler, Arteris, does just that with a glossary of ISO 26262 abbreviations and acronyms to help those attempting to wade through the functional safety standards.

Another helpful, detailed and timely blog is from Daniel Bayer, Cadence, discussing generative list pseudo methods in constraint for modelling and debugging. It is timely, as Ethernet-based communication is increasing in popularity and will require a different take on constraint coding.

Blog Review – Monday December 22 2014

Monday, December 22nd, 2014

Women in engineering; Santa’s CFD plan; VIP list; Cadence focus at CES 2015; Microsoft Band teardown; DDR 4 disruption; celebrate energy efficiency

A daughter’s enjoyment in toy trains and train tracks is the source of inspiration for a genuinely concerned blog by Keith Hanna, Mentor. Why aren’t more girls studying engineering? He takes his parental knowledge and knowledge of engineering to ponder the question.

Computational fluid dynamics also provides a back-up plan for Father Christmas – just in case the premier sleigh develops a fault (bug?) on the night of the 24 th! Gilles Eggenspieler, Ansys and helper elves, have designed a new sleigh and his blog has the graphics to demonstrate effectiveness. He has even thoughtfully added in wind shield factor and stealth mode.

Things to remember about memory VIP: VIP Experts at Synopsys, advise of a technical seminar: Strategy to Verify an AXI/ACE Compliant Interconnect (1 of 4) – just in case the Christmas TV schedules lets you down this year.

Looking ahead to the 2015 CES, Jacek Duda, Cadence, gives a glimpse of what Cadence will show in Las Vegas, reflecting the company’s focus on system solutions, including a TIP/DIP combination for mobile devices (and next year’s Christmas presents?).

Tear-downs are always fun and David Maidment, ARM, takes a look inside a Microsoft Band and have taken a look inside. He uncovers the treasure trove of an ARM Cortex-M4-based Kinetis K24 microcontroller for wearable devices.

Self-confessed candidate for the naughty list, Nazita Saye, Mentor Graphics, finds an excuse to celebrate the energy saving that electronics devices enjoy with a list of must-haves and a snap of the office Christmas tree.

Double data rate memory is set to turn the industry on its head, predicts Brian Fuller, Cadence. His blog cites Kevin Yee, Cadence product marketing director, and speculates on economics as well as the physics of the memory form.

Merry Christmas, happy new year and keep on blogging!

Blog Review – Monday, December 15 2014

Monday, December 15th, 2014

Rolling up her sleeves and getting down to some hard work – not just words, Carissa Labriola, ARM, opens a promised series of posts with an intelligent, and through analysis of the Arduino Due and there is even the chance to win one. This is a refreshingly interactive, focused blog for the engineering community.

It’s coming to the end of the year, so it is only to be expected that there is a blog round-up. Real Intent does not disappoint, and Graham Bell provides his ‘Best of’ with links to blog posts, an interview at TechCon and a survey.

There is a medical feel to the blog by Shelly Stalnake, Mentor Graphics, beginning with a biology text book image of an organism to lead into an interesting discussion on parasitic extraction. She lists some advice – and more importantly – links to resources to beat the ‘pests’.

Always considerate of his readers, Michael Posner, Synopsys, opens his blog with a warning that it contains technical content. He goes on to unlock the secrets of ASIC clock conversion, referencing Synopsys of course, but also some other sources to get to grips with this prototyping tool. And in the spirit of Christmas, he also has a giveaway, a signed copy of an FPGA-Based Prototyping Methodology Manual if you can answer a question about HAPS shipments.

Another list is presented by Steve Carlson, Cadence, but his is no wishlists or ‘best of’ in fact it’s a worst-of, with the top five issues that can cause mixed-signal verification misery. This blog is one of the liveliest and most colorful this week, with some quirky graphics to accompany the sound advice that he shares on this topic.

Blog Review – Monday December 08 2014

Wednesday, December 10th, 2014

Industry forecasts sustained semi growth; EVs just go on and on; Second-chance webinar; Tickets please; Play time; Missed parade

By Caroline Hayes, Senior Editor

Bringing 2014 to a close on an optimistic note, Falan Yinug, director, Industry Statistics & Economic Policy, Semiconductor Industry Association (SIA) tries to understand the industry’s quirky sense of timing while reporting that the World Semiconductor Trade Statistics (WSTS) program revised its full-year 2014 global semiconductor sales growth forecast to 9% ($333.2 billion in total sales) an increase from the 6.5% it forecast in June. It also forecasts that positive sales trend to continue with a 3.4% increase in sales in 2015 ($344.5 billion in total sales) and beyond, with $355.3 billion in 2016.

First road rage, now range anxiety. Apparently it is a common ailment for EV (electric vehicle) drivers. John Day, Mentor Graphics, takes heart from a report by IDTechEx which says that a range extender will be fitted to each of the 8million hybrid cards produced in 2025 and predicts the introduction in 2015 of hybrid EVs with fuel cell range extenders and multi-fuel jet engines to increase driver options.

It’s hardly a stretch to find someone who remembers using public transport before MIFARE ticketing, but Nav Bains, NXP looks at the next stage for commuters using a single, interoperable programming interface for commuters to tap NFC mobile devices to provide the ticketing service.

More time-warp timings, as Phil Dworsky, ARM, tells of a webinar entitled Avoiding Common Pitfalls in Verifying Cache-Coherent ARM-based Designs, which has been and gone but can be watched again, simply by registering. He even lists the speakers (Neill Mullinger and Tushar Mattu, both Synopsys) and lists what you missed but what you can catch again in the recorded webinar.

Enamoured with e code, Hannes, Cadence, directs people who just don’t get it to the edaplayground website, with links to a video for e-beginners.

Recap of what you missed, impactful blogs from the last 3 months
Perhaps frustrated that no-one seems to have notice, Michael Posner, Synopsys, patiently outlines some of his favourite blog posts from the last couple of months. He wants to draw your attention to prototyping in particular (it features heavily in the list) as well as abstract partitioning and the joy of vertical boards.

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