By John Blyler

A just completed EDA tools and technology survey of 140 engineers conducted over the past several weeks shows a strong push into full-custom devices and FPGAs. In fact, 32% of the ICs being designed by engineers using EDA tools were building full custom devices, and another 24% were building FPGAs. Only 9% were working on ASICs, although the ASICs tend to be large and extremely complex chips.

About 14% were designing analog arrays and another 11% were using gate arrays. Another 10% were building ASSPs.

Layoffs and stock prices were the big news for technology companies over the past couple weeks, and even in places where there weren’t layoffs there were cautious or negative predictions of things to come.

The economic news hit all sectors of the semiconductor industry, from the equipment to make the chips to the tools to design them, and it is affecting all geographies. On the capital equipment and manufacturing area, Applied Materials, KLA-Tencor both announced staffing cuts as a means of slashing SG&A expenses and boosting profitability. Applied Materials will cut 12% of its workforce, or 1,800 employees, while KLA will cut 900 positions.

In lock step with those cuts, Chartered Semiconductor warned of possible staffing reductions in its quarterly earnings last month. The company has not issued any other statements, but sources say the axe is already falling inside the company. Given the fact that Chartered is one-leg of the three-legs of the Common Platform, along with Samsung and IBM, this is probably the best sign yet of how many chips are being produced. Chartered had two consecutive losses in the past two quarters, but the loss in Q3, $13.6 million, is almost double the Q2 loss of $7.1 million.

On the design side, Cadence Design Systems cut 625 jobs, although it’s hard to tell whether that’s a result of internal bookkeeping or a slowdown in the EDA tools world. The changes at the top of the company and a restatement make it hard to figure out exactly what is happening inside of Cadence, something that likely will take several quarters to sort out.

Other EDA companies showed some pain, but not at that level. “The current economic outlook has delayed the typical contract renewal pattern we had been seeing,” said Mentor Graphics CEO Wally Rhines. “Customers are now more typically waiting until the quarter of contract expiration to renew. One of the consequences of this pattern is that we see greater strength going into fiscal 2010.”

The remaining EDA giant, Synopsys, does not report results until next month.

On the chipmaker side, AMD will cut about 500 jobs. It’s impossible to say whether this is the result of a soft market or Intel’s relentless competition. Intel revised its fourth-quarter outlook down to $9 billion in sales from a projected $10.1 billion, blaming lower-than-expected demand in all geographies and aggressive inventory reduction.

Most companies wish they had Intel’s outlook. National Semiconductor revised its outlook downward and said it will lay off 330 employees.

It will take a couple quarters to figure out exactly what trends are under way in the industry. It’s clear there is a downturn, but not all segments will be affected equally and not all are happening for the same reason. Some companies tend to react quickly to cut costs, while others already made deep cuts making it hard to draw blanket comparisons.

On a global basis, all geographies are dealing with the same issues of tight credit and cautious consumers, which is reflected in the bailout packages by all major economies and falling stock and housing prices in many places. China, which has greatly outpaced the semicondutor industry for years with double-digit growth is expected to show increases of only 6.7 percent in semiconductor sales revenue this year, according to iSuppli. That amounts to $81.7 billion, up from $76.6 billion in 2007.

China’s fabless business is expected to show 12.3 percent growth, driven by wireless and consumer electronics, the research firm said.

For years, top executives in semiconductors have been wary of a global downturn because of the increasing globalization of semiconductors. In the past, one market typically was strong while others were weak. This is the first time all major markets have shrunk at the same time. The silver lining: Design starts usually increase in a downturn.

–Ed Sperling

By Ed Sperling & John Blyler

For all the concern about 45nm chip development—and there have been a number of design investigations at that process node since the beginning of the year—the vast majority of activity is still at 130nm.

This is an indication of just how costly it has become to stay on the Moore’s Law road map—and how many companies have stopped trying to keep up. It’s also an indication of just how much life is left in the older process nodes. Since the beginning of the year, there have been more than 13,000 design investigations—trying out new tools, architectures and processes. Roughly 12 percent of those were at 45nm, with 60 percent at either 90nm or 130nm.

This has multiple implications for the industry, and particularly the fabless development model. While companies such as Broadcom, Qualcomm, Nvidia and AMD continue to live on the bleeding edge of the fabless world, the vast majority of chip developers have adopted strategies that either hang back one or two nodes or skip nodes entirely. Because of the expense of developing new chips, the number of chips that need to be sold to generate a profit has been steadily rising.

Within the foundry business, however, there have been two very distinct models. While companies such as TSMC, UMC and the Common Platform triumvirate of IBM, Samsung and Chartered Semiconductor continue to lead the pack to the next process node, that leadership comes at a very high price. Others, such as China’s SMIC, Israel’s Tower and Malaysia’s Silterra continue to erode their profits several nodes back where volume is significantly higher.

Joanne Itow, managing director for manufacturing at Semico Research, said the number of wafers processed at the leading edge continues to grow. That’s a function of how much volume is necessary to break even at advanced nodes. But Itow said that also translates into more foundry business at the leading edge than there was five years ago. Within that scenario, there also is more competition.

At the same time, she said 130nm remains popular for a variety of reasons: “It can be run with or without copper, on 200mm or 300mm wafers, and there is still a lot of capacity at 130nm. So the price is very competitive and it is not surprising that companies will continue to utilize that technology for a long time. As the price to manufacture declines, we (consumers) benefit from the new electronic applications that emerge. New designs at 130nm are taking advantage of the technology at very good price points.” Apple’s iPhone is only one example of new consumer designs that use 130nm technology.

For capital equipment makers, this isn’t particularly good news. Fewer foundries at the leading edge mean fewer sales. The abandonment of the 200mm fab equipment by memory makers has left a lot of used equipment for sale, said Itow. Big foundries have depreciated their equipment and remain competitive on pricing against second-tier foundries, but the overall effect on capital equipment sales is significant.

This also has implications for the EDA industry, although low-power design starts and a focus on business objectives versus raw performance could pry open a replacement market as well as drive new markets. As expected, the vast majority of design investigations occurred at 100MHz and 50MHz. Low power has become not only a mandate but an opportunity for chip developers, and many companies have begun developing multicore chips that run at lower clock speeds—or are using multiple chips at lower clock speeds.

Systems on chip, in particular, seem to be gaining momentum. Of all design activity, nearly 40 percent of those questioned used at least one block of non-memory IP, and some used more than 30 blocks. That figure is a strong indication of time-to-market pressures and the maturity of the IP industry, as well as an indication of how companies are crafting their chips.

Interestingly, the bulk of the lower clock speeds are being developed at older process nodes, not at the bleeding edge. Speed is still important, but as a selling point power is at least as important, if not more important. In fact, since January there have been only 23 investigations into chips running at clock speeds greater than 3GHz.

By region, most of the design activity occurred in North America. Asia, including Japan, saw only about one-fourth as much activity as North America in 2008. Despite all the startups in China and the preponderance of manufacturing there, the bulk of the design activity remains in North America. Asia was tied with Europe.

By Ed Sperling

The crossover for system on insulator (SOI) versus bulk CMOS was supposed to happen at the 22nm, but that was before software developers ran into problems programming multicore chips.

For years, SOI was considered the high-performance cousin of CMOS—more expensive, more difficult to manufacture and unnecessary for most applications. It is the heart of the Cell processor, for example, which drives Sony’s Playstation 3, the latest versions of digital televisions and some network appliances that need the benefits of always-on active power.

But with the persistent problems of writing general-purpose applications that can scale with multicore processors, SOI is quietly gaining more mainstream appeal. By running either faster or cooler—or both—it can provide the performance gains that multicore chips would provide if the software could take advantage of all the cores.

“SOI does offer a way out,” says Horacio Mendez, executive director of the SOI Consortium. “The big issue is the scalability of bulk CMOS, and there are significant challenges there. When you shrink the transistors, they’re not stable. And with stability comes a power consumption problem.”

The instability is caused in large part by voltage threshold variations. As companies continue down the Moore’s Law road map, short-channel effects (see Fig. 1 below), an increase in parasitic leakage as a result of scaling gate-length dimension and gate oxide leakage all contribute to power dissipation. SOI chips use up to 40% less power due to lower parasitic capacitance, and because they can use higher current they operate at lower voltages.

In practical terms, that means SOI chips can at least keep the number of cores constant and still add performance at each process node. And because they run cooler, they also can use less expensive packages—something that affects when they become economically feasible to use in lower-performance applications.

Short Channel Effects — Source: IBM

Given the advantages, it should come as no surprise that IBM has opened its SOI fab to commercial business at 45nm. Mark Ireland, IBM’s vice president of semiconductor platforms, said SOI is expected to be adopted by the Common Platform group—IBM, Samsung and Chartered Semiconductor—at 32nm.

“What we’re doing now is creating an industry ecosystem,” Ireland said. “From a design standpoint, this is more about education of engineers. At IBM we moved our entire ASIC business to SOI at 45nm. A lot of the hesitation is just about the unknown. But it’s the same design tools and ARM physical IP.”

Opening SOI technology to a broader market also should drop the cost even further, bringing it much closer to parity even at 45nm. But the biggest advantage is still on the software side. While many applications can be threaded to deal with between two and eight cores, far fewer will gain from the addition of more cores. On top of that, very few applications are scalable so they can be written once and recompiled for as many cores as become available.

“Customers already are coming to us looking for higher single-threaded performance,” Ireland said. “Clearly, that legacy market is not going away. Applications will not change overnight. And you do get a performance gain every time you move to the next node, so at 32nm vs. 45nm, there is a performance gain.”

Intel developed a similar technology called TerraHertz in 2000, but so far has done nothing with it commercially. It is one of several possibilities that Intel can tap into at future process nodes, along with its Tri-gate technology. Likewise, IBM has been developing its own tool bag of options, which includes everything from FinFETS to AirGap insulation between structures on a chip.

All of these technologies can be manufactured using existing equipment, and likely will have a significant role in future system development

John Isaac, director of system market development at Mentor Graphics, talks about problems at the board level.

By Ed Sperling

IBM and ARM are teaming up to simplify silicon-on-insulator chip development, cutting the time it takes to bring SOI to the next process node and making it more competitive with CMOS.

The big advantage is that SOI is significantly more energy-efficient than CMOS. But the complexity of developing in SOI has deterred many companies. With increasing pressure on electronics companies to reduce the energy consumption of devices, both IBM and ARM see a major opportunity.

“It’s been hard for companies to see past the challenges of learning a whole new design methodology,” said Joanne Itow, managing director at Semico Research. “They all think SOI has too many idiosyncrasies. ARM’s support provides a significant amount of credibility. And the timing is right. If a company starts a design now, they can have a product ready when 45nm reaches a sweet spot in terms of volume and pricing at the foundries.”

The deal calls for ARM to provide an SOI physical IP library, including standard cell, memory and I/O libraries for IBM’s 45nm SOI foundry. ARM’s entry into this market was made possible by its 2006 acquisition of SOISIC, a French company that was developing physical IP for SOI.

Tom Lantzch, vice president of marketing for the ARM physical IP division, said that SOI offers 30% more power efficiency over bulk CMOS, which is particularly important in such applications as gaming or digital TV where there is constant compression. He said the digitization of almost everything and the need for constant-on functions will push more of the market toward SOI, in part driven by consumer demand and in part by the availability of power in some markets.

SOI has been at a disadvantage in the past, however. It has run several years behind CMOS in terms of reaching the next process node, and subtrate costs have been higher for SOI than CMOS. ARM contends the availability of physical IP for SOI will cut the lag time between process nodes to about a year at 32nm, which is typically faster than most companies can adopt it. In addition, performance will be comparable, and overall differences in pricing will be reduced and offset by gains in power efficiency.

By Ed Sperling

The upcoming semiconductor industry road map, which sets up the industry’s strategy and identifies trends for the next 15 years, is filled with three very interesting shifts and gaps.

The road map, which will be formally unveiled next month, consists of findings gleaned from all the top chip companies. Juan-Antonio Carballo, a partner at IBM Venture Capital Group who spearheads that report’s design chapters, says the shifts around the edges of the industry are particularly interesting. He cited three major changes and problems that will have a profound effect on system-level design:

Software: There needs to be 1,000% improvement in software just to maintain the level of chip development that exists today. Right now, software accounts for about 50 percent of the development budget for semiconductors.In the past, semiconductor companies were required to generate only the code embedded in the chip. In the future they will be expected to include everything from the operating system and middleware all the way to the browser.

“The software crisis has finally hit,” said Carballo. “We need a 100% improvement every year in software development.”

Carballo said Chinese companies will jump into this market with both feet, fueled by a significant rise in skills in the past couple years and lower labor costs. “It takes more people to develop software in China, but that’s still a smaller percentage of the overall budget. So in China, software is 20% of the overall development cost vs. 40% in Silicon Valley or a similar location.”

Power: Energy usage is emerging as the top priority in developing economies because it’s part of the overall total cost of ownership for a device. While power-efficient devices are convenient in established economies because they offer better battery life, they are a competitive differentiator in extremely price-sensitive markets.

Carballo said this was a surprise to most chip companies. “We thought this was more likely to happen in the Western Hemisphere first,” he said. “We believe there will be a dramatic shift, though, where power consumption will move to the top of the list of features. We’re expecting to see variability in energy consumption over the next 15 years in 600% and 700% increments.

Globalization: Investments in China, in particular, and other developing economies has reached the point of critical mass. That means R&D is being spread out across all geographies rather than being confined to Silicon Valley.

“A typical semiconductor startup in the West requires $20 million to $40 million to get to first product—or maybe just a prototype—and that takes five to six years. In China, the price is $10 million to $15 million, and in two to three years the company will be shipping products valued between $1 million and $10 million. That may be a simpler design and there may be more competition, but the return is quicker.”

Getting to the next step is more difficult, because that frequently involves moving from a single product that may be based upon standard parts and a reference design to internally developed IP. But Carballo said there are enough entrepreneurs in China now, who have worked at startups in Silicon Valley and moved back to China, to make a difference. He said that shift has been noticeable in the past year.

“The differences are starting to blur,” he said. “R&D is starting to shift to Asia. The result will be the amorphous company where they combine products, sales and marketing and R&D from all geographies. This will mean a dramatic change in technology and business. In Silicon Valley, you can still choose from 1,000 vice presidents of business development. In China it’s not 1,000 yet, but it is now in the 100s.”

By John Blyler

Chips continue to grow in complexity. This is nothing new. But even at the existing process nodes of 180nm and 130nm, complexity is increasing as designers attempt to squeeze in more feature sets while shrinking the power budget and chip size. This growing complexity, married with the shift to time sensitive consumer product markets has led to an increase in the use of prototypes to verify these chips prior to production.

But what do users really seek in prototyping tools? The report that follows contains the summary and analysis of a survey conducted with more than 270 qualified respondents in the ASIC and related markets. The results track well with similar surveys in this space, but the details present some surprising implications.

Application Markets

Most responders listed the communication market as their primary product area, followed closely by the Consumer, Computer and Other markets (see Figure 1). Most prevalent “Other” markets were Industrial, followed Mil/Aero, Automotive and Medical.

Figure 1

In the category of communications, most respondents listed wireless handsets and wireless and wired networking as their chief application areas, followed closely by wireless base station design, telephony/VOIP and wireless Metro Area Networks (MANs). A small percent listed research, remote controllers, CDMA networks, fixed networks, telemetry and military as other areas of focus within communication category.

In the consumer market most respondents list multimedia designs – involving both video and audio subsystem – as their primary area for developing ASIC prototypes. Multimedia design concerns will be reflected proportionately in other parts of this survey, i.e., processor types, interfaces, etc. Interestingly, several designers listed games as their chief concern. That’s a trend we will watch in future surveys.

Computer design issues were most closely tied to peripherals such as storage, printers and the like. PC and workstation systems came next, with others including prototyping systems, servers, data acquisition modules, and instrumentation and software/firmware design issues.

Job Function

Most of the respondents identified themselves as ASIC or ASSP designers, followed by engineering management, corporate management, verification engineers, system architects and software designers. A small percent of users listed their function as applications engineers, business development, academia and sales/marketing.

Figure 2

ASIC/ASSP/SOC Design Details

When asked to describe their current ASIC/ASSP/SoC design, more than half of the respondents indicated a design size of less than 5M gates, with that majority below 2M gates.

In terms of memory, most designers focus on SRAM memory, suggesting the strength of on-chip memory prototyping. Still, DDR and Flash memory account for about 22% each of memory usages.

Embedded processors usage is led by the MIPS processor, which matches up with the respondents’ applications markets. ARM, Tensilica and Intel comprised roughly 16% each of the remaining usage. Other processors used for ASIC prototyping ran the gamut from microcontrollers like the 8051, Microchip’s PIC and Xilinc’s MicroBlaze to proprietary cores. A large number of DSP cores also were cited, including Ceva Teak Lite, TI and in-house multimedia DSPs.

To the question concerning the types of external interfaces used in ASIC prototyping projects, the top three busses were PCI, USB and Ethernet. SPI, SATA, XAUI and HDMI finish up the lower quadrant. Though not listed in the survey, questions have arisen about the use of the PC-104 bus. Several experts believe PCI Express represents the path forward for PC-104. This projected growth will be the subject of a future survey.

The majority of users listed Serial RapidIO (sRIO) as the main external bus of choice under the “other interface” category. This is no surprise, since the sRIO interface is commonly used to connect multiprocessor designs, especially for DSPs. This tracks well with the use of DSPs highlight in the “Processor” usage category cited earlier. Other interfaces include I2C – a low-speed serial bus used to attached peripherals to a motherboard, embedded system, or cellphone; DVI, RS-232, parallel bus, CAN – automotive bus, DigRF – digital serial interface for 3G air standards; and even UART.

Re-spins

A little over half of the respondents indicated their previous design project required no re-spin. Of those acknowledging re-spins were necessary, 50 percent stated that only one re-spin was needed. About half as many reported by two re-spins were required and slightly less than 10 percent admitted to three re-spins.

The main reason for chip re-spins was the presence of logical and functional errors. This result tracks well with other recent studies that indicate more than 60 percent of re-spun ASICs fail due to logical/functional errors, not because of timing or power issues. This means that functional verification is now the most critical phase of the chip development cycle.

Figure 3

Verification Environments

When asked what type of verification was used for a current project and planned for future work, the largest groups of respondents selected Mentor’s ModelSim/Questa. This was followed by Cadence NC Simulator and Synopsys VCS.

Figure 4

Other software simulation environments consisted of tools from IBM, Altera’s QuartusII and Xilinx’s ISE, Synplicity’s Synplify, Dolphin’s SMASH and Catena’s Analog and Mixed Signal (AMS) Simulators, Aldec’s Active-HDL Simulator and homegrown systems.

In terms of emulators, most users listed Cadence systems, followed by Mentor and Eve. An interesting side note is that only Eve emulators saw a planned increase for future projects. Formal verification favorite was Formality, followed distantly by OneSpin, Real Intent and Certess. System Verilog lead the way in Assertion-based tools, followed by OVL and PSL.

Here’s where the results get interesting. When asked what type of virtual prototyping environments were currently being used, ARM was the favorite – but by a decreasing margin for future projects. Synopsys’s Virtio was the second most popular choice, showing projected growth along with CoWare, VaST and Virtutech. One should exercise caution when interpreting these results, since the slower pace in usage of ARM tools may simply reflect the growth of virtual prototypes in non-telecom related industries.

Figure 5

Looking at the other end of the prototyping spectrum revealed that Synplicity was used more often for ASIC prototyping with FGPA-based systems – at least in the market areas highlighted by this study. ProDesign followed second, then came Dini and Gidel. It must be noted, however, that 36 percent of respondents still used custom-built FPGA-based prototyping, though the percentage was on the decline for future projects. This marked decrease in custom-built systems may attest to the growing complexity of ASIC designs and hence the corresponding complexity of FPGA prototypes.

Conclusions

This survey points to the changing dynamics in ASIC prototyping tools and methodologies. Prototyping of specific blocks on an ASIC core now seems mandatory, especially since ASICs continue to increase in design complexity. This complexity is manifested by an increase in logical and functional errors in the chips, which has resulted in a need for more complete verification tools and methodologies.

But prototyping itself has taken on a new dimension with the advent of virtual prototypes – used more often by software designers – and FPGA-based prototypes used by chip hardware engineers.

These trends have been confirmed by other studies. For example, Aberdeen’s “Best in Class” study cites verification as one of the most prevalent concerns in chip companies. Chip Design Trends reports, which tracks ASIC pre-silicon architectural trends, confirms the growing complexity of ASIC chips – at all levels of design metrics. Contrasting this complexity with the continued decrease in ASIC starts suggest that ASICs may be getting larger in size though less numerous in unique projects. All of these trends support the growth of prototyping as a key element in future chip designs.

On the business side of the equation, one should note the shift away from corporate electronic expenditures to the rapid increase in consumer’s consumption of electronic products. The consumer world is outpacing the corporate world in the purchase of electronic goods, but there is a caveat: Consumer electronics have a shorter time to market, high product volume but lower cost per unit that corporate electronics. What does this mean to chip designer? It means that they must find a way to reduce ASIC re-spins, such as with ASIC prototyping.

The rising copper prices are leading some companies to re-examine aluminum, particularly for price-sensitive commodity products at older process nodes.

Copper interconnects, which completely changed design at 130nm—along with a shift to 300mm wafers and low-k dielectric insulation—are getting a second look. In fact, they’re actually being used in some chips at 110 nm and larger.

The reason is the cost, say industry sources. When copper interconnects were first under consideration in the late 1990s, copper sold for less than $1 a pound. The price peaked at $4 a pound this summer, before retreating to the current $3.25. But no matter how you cut it, that’s a significant price hike.

Aluminum isn’t free of significant price increases, either, although it’s not rising as quickly. A story by TimesOnline said that aluminum prices are expected to increase by about a third in the next couple years, in large part because the cost of running aluminum smelting plants is skyrocketing. That would increase the price to about $4,000 a ton, compared with $6,000 to $8,000 a ton for copper over the past few months.

While it’s true that chips require very small quantities of either copper or aluminum, in volume the numbers can mean the difference between a vendor winning a contract or losing it to a lower-priced competitor.

Copper will continue to be used in the most advanced chips, and road maps from the Common Platform, Intel and TSMC all show copper interconnects in future generations of chips. But in commodity applications, particularly those running at older process nodes, every penny counts.

“Some applications do not need to go to advanced geometries,” said an industry source. “These are particularly cost-sensitive applications. You will see aluminum interconnects at 110 nm and 130 nm become qualified for automotive applications in the near future.”

–Ed Sperling

By Ed Sperling

From a distance it looks like a game of hot potato. But this version is played by hardware and software engineers, who normally don’t have much to do with each other.

The hardware engineers say you can’t get any more performance out of a single core on a chip without cooking it, so they’ve added more cores and tossed the problem over the wall to the software engineers. But the software engineers say that while they can thread functions across cores, there are very few applications that actually will scale to use more cores without completely rewriting every software application at each new process node.

Companies such as Intel and IBM and most of the computer science departments at major universities are feverishly working on this problem. Unfortunately, they still haven’t come up with a solution, and the reason isn’t because this is a new problem. It’s been festering for four decades, and so far there isn’t a breakthrough. Programmers think serially, not in parallel, and there is no magic bullet to automate the programming.

David Patterson, the Pardee Professor of Computer Science at UC Berkeley and head of the parallelization effort there, calls multicore programming “the El Dorado of computer science” and refers to parallel computing as “an open research project.”

That may prove to be a polite assessment of the problem. More to the point, if there’s no breakthrough in software there will be no compelling reasons to upgrade computers or even handheld devices such as cell phones. Without performance upgrades, sales cycles will slip and the tech boom of the past 60 years either will begin slowing at an alarming pace or there will be massive shifts in how technology is sold and used.

“There is no killer multiprocessor,” Patterson says. “But programmers needing more performance have no choice except parallel processing.”

Where it works, where it doesn’t

That doesn’t mean parallel processing doesn’t work. Some applications adapt exceptionally well to multiple cores. In the commercial enterprise, databases and search functionality, for example, are showcases for what can be done with multiple cores. The individual tasks can be parsed onto as many cores or processors as are available. Often referred to as embarrassingly parallel tasks, these kinds of applications can scale almost infinitely with minimal tweaking of the application.

The same is true in the simulation world. Mentor Graphics last week introduced a parallel version of its Olympus SoC timing analysis and optimization engine that shows very little performance reduction when parsed onto different cores. The result is that two cores offers almost double the performance of a single core, and four cores roughly quadruples it.

“The problem is parsing into independent tasks and then bringing it back together again,” said Sudhakar Jilla, director of marketing in Mentor’s place and route group. To no small extent, that means understanding the application and its interaction with the processor so well that it can be broken down into distinct processes.

The same will never be true for most personal productivity applications. While you might be able to split some functions off of an Excel spreadsheet or Microsoft Word to take advantage of two cores, the same process would have to be repeated at four cores, eight cores, and so on.

UC Berkeley’s Patterson said people have been trying to achieve automatic parallelization for years. “We see hundreds of cores on a chip seven years out. Today, there is very little software taking advantage of the cores. Cores are idle almost all the time, and there’s plenty of reason for pessimism.”

Back to the drawing board

One solution may be a new language or languages to run on multicore chips. That ultimately may prove to be the best choice, but many people remain skeptical.

Intel has taken a first stab at the problem with a language called CT. Until now, Ct has worked largely on a shared memory system, but the company is considering whether to use a distributed computing environment approach so that an application can scale to every node on the system.

All of this will take time, of course. The first step is for libraries and frameworks to be parallel-enabled, which Intel believes will happen in the next one to two years. After that, it could take 5 to 10 years for the development language to become mainstream—something that will require lots of work on the part of Intel, its partners, and research currently being done by universities around the globe.

IBM and Microsoft also are working on their own versions of parallel programming. So far the companies have not released details of their efforts. But the goal in all cases is to “divide and conquer” by breaking down the pieces that can be run in parallel.

Add to that an inherent incompatibility between future chip strategies by both IBM and Intel. IBM has opted for heterogeneous cores in its future chips. Intel is focusing its efforts on homogeneous cores. It’s likely that the two worlds will merge with a mix of homogeneous and heterogeneous cores, but it raises some programming issues that are not yet resolved.

Security Issues

There are other challenges in the multicore world that don’t exist in the single core chip. Security, in particular, is much more of a concern because of the flow of data between cores.

“With multicore, there are new challenges to utilize the individual cores,” says Andrew Sloss, the ARM’s liason to Microsoft, said the difficulty is controlling communication across cores and avoiding “excessive broadcasting.”

“We define security as hardware protection that makes it too expensive to break into the system,” Sloss says, adding that in all systems important data needs to be isolated.

Business Issues

No matter how big this challenge looks, or how much pessimism accompanies it, most people involved believe the electronics industry has no choice but to solve it—or radically change their focus.

While corporate IT will continue to buy servers, the vast majority of electronics these days are sold into the consumer world. Typically, what sells new products are either dramatically lower power consumption and equal or improved performance.

If no one can figure out how to scale programs on multicore chips, or the uptake is limited to the current scientific and highly mathematical applications, then the road map for future chips shifts. Moore’s Law is still feasible, but it may no longer be relevant.