By John Blyler and Staff
Runaway complexity in design, implementation, verification and manufacturing is being mirrored across an increasingly complex supply chain. Now the question is what to do about it.
Complexity is being driven by the continued shrinking of feature sizes and the clamor for more functionality to leverage the real estate that becomes available with each new process node. But the increased density also requires a slew of new technologies, such as finFETs, new processes such as double patterning, and potentially even new materials. On top of that, market windows are actually shrinking rather than remaining constant, putting pressure on teams to ramp up their IP reuse when possible, or to buy commercially available IP when it isn’t.
This all sounds straightforward enough, except that the number of partners critical to an SoC’s success is growing, as well. And the more partners in the supply chain for any given chip, the more chances that something will go wrong. Moreover, given the huge investment required for chips and their derivatives these days, that’s causing companies to scramble in an effort to contain the risk.
“Who you decide to work with is almost becoming a bet-your-company strategy,” said Mike Gianfagna, vice president of corporate marketing at Atrenta. “If you’re buying IP from 10 or 15 sources, you also have to worry about the interoperability of tools. Over the next few years, as we move into stacked die, you’re going to have custom, standard and FPGAs, all of which will need to be put into a package with an interposer. Then you need to get the package to yield. Who takes on the risk to manage the inventory, assemble it and fix it if it doesn’t yield?”
He’s not the only one asking that question.
“A lot of companies have tried a supermarket approach to IP,” said Kurt Shuler, vice president of marketing at Arteris. “That’s fine for standard IP. It either works or it doesn’t. But when you’re dealing with all the other stuff—the processors, the memory controller, the interconnect, there are huge differences in performance, area and ease of integration.”
But there also are subtle differences, as well. An IP block, or even a subsystem, may be fully characterized for one process node and in one configuration and still not work well in another SoC. Noise, heat, and even different user profiles can change the characteristics for how well a piece of IP functions from one design to the next.
One way to ensure that IP actually works as planned is to harden it—actually turn out a test chip so that physical measurements can be taken to completely characterize it. The problem with soft IP is that it’s never completely characterized. The problem with hard IP is that once it’s in silicon, it’s impossible to change. The goal—and this is a new approach—is to harden it, fully characterize the IP, and then take it back to the lab for more tweaking and more test chips. It’s also a much more expensive way to make sure everything goes as planned, but one that appears to be increasingly necessary at advanced nodes.
“Customers want one throat to choke, and the strategy to allow that is to have bigger and more integrated pieces of IP,” said John Koeter, vice president of marketing in the solutions group at Synopsys. “Otherwise you end up with lots of finger pointing. That also means working with fellow IP partners more closely. So what we’ve been doing is to harden ARM cores. We’ve been doing the same with Imagination. We’re essentially doing test chips for IP. We’ve done this with a multi-way collaboration at 14nm with Samsung and ARM. And with most IP we’re also doing split lots, so we process characteristics over time to improve reliability.”
Collaborative test chips are a rare phenomenon in the history of the semiconductor industry, but doing that to better understanding how to integrate IP is brand new. It’s also evidence of just how complicated integration has become, and how concerned the big IP vendors are about getting the formulas right.
Massive ecosystem investments
But integration of IP is only part of the change. There has been plenty of talk about creating virtual IDM partnerships. Making that approach actually work is quite expensive, and it’s likely to have significant repercussions on both who’s successful and who’s left standing after the next wave of consolidation.
“Between the segmentation there has to be tremendous collaboration and coordination,” Chi-Ping Hsu, senior vice president of R&D in Cadence’s Silicon Realization Group. “If the PDK file from the foundry doesn’t work, who do you look for? Is it the tool vendor, the foundry? And the tool vendor has so many different versions of software coming out and the foundries definitely don’t use all of them. They can’t afford them. So how this whole coordination and validation gets done is one of the big challenges.”
He noted that the lines between IC, foundry and EDA have blurred, requiring vertical collaboration. But that collaboration is very expensive in terms of R&D. “And this is not about tools. It’s purely about collaboration.”
That collaboration takes the form of R&D, joint marketing, and an ongoing series of technical papers. In addition, it has to be repeated by each EDA vendor with every major foundry they want to work closely with, each IP vendor, and each major customer.
Other changes ahead
Another important shift that has occurred across the supply chain involves the assignment of risk. At 65nm, foundries typically sold known good die to customers. At 28nm, they are selling wafers, passing bad yields onto their customers rather than absorbing the cost. The result has been a boom in EDA and advanced tooling, and in particular a surge in both verification and design for manufacturing tools.
Coupled with that is a blurring of the lines between IDMs and fabless companies. “We are seeing IDM’s leasing parts of their fabs to external companies,” said Michael Munsey, director of product management and strategy at Dassault Systemes. “In addition, all manufacturing stages need total flexibility so that cost, yield, risk can be modeled to allow the company to meet their high level and operational KPI’s. In the future, due to the capital investment required for semiconductor manufacturing, the industry has no choice but to go to a completely flexible model that allows for dual/multi sourcing, and to manage cost, yield and risk.”
He noted that with that shift also comes a different bill of materials. “We are managing process, such as the diffusion process, test/sorting, assembly/marking, etc. A single die could have different tests applied to it, or may be characterized differently, meaning dies from the same wafer may end up in different packages, and sales may be at the wafer level, die level or at the package level. There could be many configurations that need to be precisely managed and controlled. In addition, some devices could be stacked dies or multi-chip modules or package-on-package, so any system also has to support these multi-level constructs. And when you overlay the sourcing network (different manufacturing sites may be qualified for different processes), then the configuration management problem scales to another dimension.”
Rich get richer, but not everyone goes away
This potentially bodes well for larger IP companies. Massive investments in tighter partnerships means companies are more in sync about both technology and market opportunities. For smaller companies, it’s a question of where to place much more limited resources.
“Smaller IP companies need to pick and choose their customers and partners much more carefully,” said Arteris’ Shuler. “For the overall industry this is probably a good thing. But you do have to worry about the very small semiconductor vendors. The pain level of complexity is already high at 28nm. The leading edge companies know what they want. Still, the sales cycle is getting shorter, too, and people are just starting to realize how much pain they have.”
John Heinlein, vice president of marketing for ARM’s Physical IP Division, noted a similar division from a different vantage point. “There is a lot of inequality in the ecosystem,” he said. “What that means for ARM is that we have to work with a wide range of companies. We have to support customer flows and all the EDA flows and the major interfaces and standards.”
So far, ecosystems are still enormous. ARM’s, for example, includes more than 1,000 partners. But pressures are rising everywhere and in all directions, as witnessed by ongoing consolidation in all segments, the shifts in alignment of partnerships, and the increased acceptance of commercial IP. While these changes are complex and hard to generalize across a disaggregated global infrastructure, virtually everyone agrees that changes will accelerate as the industry pushes to the next process nodes and into stacked die, where packaging and test will be required at different stages of the manufacturing flow.