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Mixed-Signal Platform Extends Charging

Monday, September 19th, 2016

Mixed-signal platforms such as Silego’s GreenPAK simplify the design of an extended battery charger with minimal external components.

by Ramkumar Ramaswamy, PhD

Lead acid batteries, once charged, are typically held at a float voltage that is higher than the open-circuit voltage (OCV). The intent of this float charge is to compensate for self-discharge. Not that this is without problems: there is greater water loss due to gas evolution, when compared to being held at OCV. It has also been argued by many that maintaining stationary batteries at float voltage does more harm than good – see, eg., Nguyen et. al. [1]. Using a reduced float voltage with intermittent charge can be a superior method of battery management in many applications. One specific context of application for such battery management is in on-grid solar applications. In such applications, the battery is only used as a standby, yet it may represent a sizeable chunk of the investment in the solar system. Therefore, the battery life needs to be extended, and its maintenance and watering needs must be reduced also.

On initiating a charging cycle for a lead acid battery, it goes through several states. We summarize the process very briefly; more detailed information is readily available in the public domain, e.g. at websites such as The Battery University [2]. Charging begins in a constant current (CC) regime called the Bulk phase, which ends when the voltage reaches Bulk Voltage (see Table 1). The regime then changes to constant voltage (CV). The battery enters the Absorption state, in which the voltage is held constant at the Bulk Voltage for a specified period of time. Then the voltage is reduced to the Float Voltage which, in the standard case, signals the end of charging. In this application note we are not content with stopping with that. Rather, we want to hold the battery at the Float Voltage for a specified period of time, then reduce the voltage further to what we call the Reduced Float Voltage, which represents the end of the charge cycle. Typically, the Reduced Voltage will be close to the battery’s OCV. However, a battery cannot be held at OCV for too long because it starts to lose capacity and then sulfate. Therefore, the battery must intermittently be taken to a higher voltage (Float or Absorption Voltage) to compensate for this loss of capacity, then brought back to the Reduced Voltage. This may seem like an obvious feature to have in a solar inverter for example, but in the author’s experience it is not always available, even in premium inverter brands.

The below state diagram represents the above states and their transitions.

Figure 1. The Battery State Machine

Solution Architecture using GreenPAK 5

In this application note we will demonstrated how a mixed-signal platform like GreenPAK simplifies the design of an extended battery charger with minimal external components. We start by describing how the various building blocks of GreenPAK5 as well as external elements are brought together to create this platform. (We will henceforth use programming-style variable names such as BulkVoltage, FloatDuration etc.) The chip chosen is SLG46531V.

Figure 2. The GreenPAK 5 Design

Asynchronous State Machine (ASM). GreenPAK 5 was chosen because it offers an ASM that makes it particularly convenient to capture the battery states and transitions. The state and transition definitions as per Figure 1 above.

ACMP0-2. For this application note, we take a case where the nominal battery voltage is 12V. The design can easily be extended to other voltages. We can scale the battery voltage with a resistive voltage divider, but we choose an alternate strategy given that we are not interested in voltages less than 12.5V or greater than 14.5V. We subtract 12.5V using shunt references of 10V and 2.5V, as shown in Figure 3, leaving us with a much smaller voltage range of about 2V to contend with, thereby allowing greater accuracy in voltage measurement. This transformed battery voltage of 0-2V is run through a 0.5X gain stage at each analog comparator (ACMP) IN+ input[R8] .

Thus each ACMP input IN+ sees a voltage of 0-1V.

For example if we take a 12V Exide SolaTubular battery, the manufacturer-specified values and the transformed values for the respective ACMPs are as follows:

Parameter Value for 12V Battery Transformed Value at VIN+
Bulk voltage 14.5V 1.0V
Float voltage 13.7V 0.6V
Reduced Float voltage 12.6V 0.1V

Table 1: Typical voltages associated with a lead-acid battery

The above voltage thresholds for the ACMPs are conveniently derived from the internal voltage reference and no external voltage reference is required. The external components used in the design are shown below; the rationale behind the component values is explained in the section “Example Implementation.’

Figure 3. External Components Used

One of the ACMPs, ACMP0, is referenced to BulkVoltage; when the ASM is in Bulk and the battery reaches BulkVoltage, the AND gate triggers the state change from Bulk to Absorb. The other ACMPs are used to effect the CV regimes by holding the battery voltage at the respective value such as FloatVoltage and ReducedFloatVoltage as we will describe shortly.

Figure 4. DLY Config

Delays/Counters. Once the battery exits the bulk phase, the rest of the state transitions for the remainder of the charge cycle maybe conveniently triggered by the passage of time. For example, the battery moves from Absorb to Float after AbsorbDuration (2 hours) and from Float to ReducedFloat after FloatDuration (1 hour). After spending several days at ReducedFloatVoltage, the battery will be taken up to FloatVoltage again for FloatDuration and the process iterates. These time-based triggers are achieved using delay/counter blocks CNT1/2/3. We wire these as delays rather than counters because a counter outputs a high when it is reset which behavior upsets the operation. Instead, we configure these as rising-edge delays as shown alongside. For example, DLY3′s DLY_IN comes from the ASM’s Float state output; therefore when Float is entered, the high state is detected by DLY3 and fed to the Float-Reduced float transition after FloatDuration. As soon as the ASM moves from Float to ReducedFloat, DLY_IN returns to zero dragging the output also to zero. The clock source for all these delays is CNT0 whose input is the 25kHz clock and output period is set to 60 seconds.

GPIOs. A new charge cycle is initiated by driving a HIGH input on Pin3. In an actual application this could be used to initiate a new cycle manually, based on time or based on the battery voltage going too low. The last use case requires an external comparator, and effectively defines NewCycleVoltage as a trigger. Typically its value would be 11.5V for a 12V battery.

In the CC regime, current must typically be limited to C/10 where C is the battery capacity in AH. This is achieved by the output transistors Q1 and Q2 driven into an ON or OFF state by Pin4, wired as a digital output. The current-determining resistor is on the emitter of Q1, and as indicated its value should be 10/C for a battery of capacity C that is rated for a maximum charge current C/10. The battery is in the collector of Q1 so its voltage does not significantly affect the charge current.

ACMP1, ACMP2. Only one state transition is driven by voltage – the BulkVoltage. In contrast to this, the other voltages – e.g. FloatVoltage and ReducedFloatVoltage are not triggers for state transitions. Rather, these are outcomes of the state that the battery is in.  Because all these voltages are associated with a CV regime, we may use them as references for ACMP1 and ACMP2 respectively, which allows us to trigger a state change based on the current state and the battery voltage. These comparators are in turn used to drive the charging transistor Q1 as described now.

In the CV regime, there are two ways of charging a battery. One is by the use of a steady current and the other is by using a pulsed current of higher magnitude. For example, pulsed current is used in PWM charging which is popular for lead acid batteries as it supposedly helps reduce sulfation (See The Battery University article [3] and the accompanying comments). We use pulsed charging in the CV regime too, using the same PNP transistor used for CC charging. Based on the state of the battery, we select the appropriate ACMP to also drive the bias to Q1.  We use a 25mV hysteresis setting for the ACMPs so that the transistor switches on and off to maintain the average battery voltage at the desired level, equal to the selected ACMP’s reference voltage and within the chosen hysteresis band.

For instance, FloatVoltage is a reference for ACMP2. When the battery enters the Floating phase, we would like to use ACMP2′s output to determine when to bias Q1. Since ACMP2′s input IN+ pin is reading the actual battery voltage, it output will switch the transistor on and off repeatedly as the actual battery voltage oscillates slightly about FloatVoltage (within ACMP2′s hysteresis band). Similar logic holds for CV charging at the other voltages BulkVoltage and ReducedFloatVoltage. This logic is captured in the truth tables for LUT0/1/2, ORed together by L7.

Example Implementation. The design was implemented with the external components of Figure 3 and used to charge an Exide 12V 4.5AH battery. Z1 and Z2 must have a similar operating current range. Here they are LM4040s that operate with a current range of 60 uA to 10mA. Along with R3 = 330R, the current range falls within spec for the desired battery voltage range.  C1 is required to avoid forcing the GreenPAK to respond too fast when the comparator is in the hysteresis range, otherwise spurious behavior can result. Q2 is driven to saturation whenever Pin 4 goes high; this drives nearly 10mA through the LED with Vcc = 15V. With a red LED, the voltage drop across R1 is about 1V, so R1 should be set to 10/C ohms to limit charge current to C/10.

The following photographs show the waveform at Pin 4 when the battery is in the Absorb and Float  CV regimes. The pulsing nature of the charger is evident, the charge pulse in this test setup was about 5ms with a 300mA charge current.

Figure 5. Pin 4 level, Absorb

Figure 6. Pin 4 level, Float

(Note: In the accompanying .GP5 file we have, for testing and evaluation purposes, set CNT0 to output 1s pulses rather than 60s pulses, and the DLY block data have been set so that AbsorbDuration, FloatDuration and ReducedFloatDuration are 1 minute each. The labels attached to the CNT0 and DLY blocks indicate the values that would make more sense in a real deployment.)

Conclusion and Further Extensions. In this application note we demonstrated how a mixed-signal platform like the GreenPAK simplifies the design of an extended battery charger with minimal external components. Several extensions to the design are possible and desirable in a robust, field-deployable system. For complete generality we may add a current sensor that triggers a state change in the CV regimes based not on time but on the current dropping below a certain value. Temperature compensation of battery voltages is an important aspect that we have not considered here. We could also do with a load-dependent voltage trigger for a new charge cycle to begin. Parameters such as AbsorbDuration, FloatDuration etc may be made to depend on the frequency of charge/discharge cycles experienced in the application. And so on. Ultimately the objective is to squeeze the maximum life out of a battery and, though lead acid batteries are almost as old as sliced bread and have been analyzed to death, they are temperamental creatures and battery life optimization is easier said than done!


  1. “Traditional float charges: are they suited to stationary antimony-free lead acid batteries?” T. M. Phuong Nguyen, Guillaume Dillenseger, Christian Glaize and Jean Alzieu, in Trends in Telecommunications Technologies, Christos J. Bouras (ed), INTECH Publishing, 2010.

About the Author

Ramkumar Ramaswamy (Ram) is an electronics engineer based in Bangalore, India. He received his MSc in Physics from the University of Delhi and his PhD in Operations Research from the Indian Institute of Management Calcutta. He has authored several technical articles.

The EDA Industry Macro Projections for 2016

Monday, January 25th, 2016

Gabe Moretti, Senior Editor

How the EDA industry will fare in 2016 will be influenced by the worldwide financial climate. Instability in oil prices, the Middle East wars and the unpredictability of the Chinese market will indirectly influence the EDA industry.  EDA has seen significant growth since 1996, but the growth is indirectly influenced by the overall health of the financial community (see Figure 1).

Figure 1. EDA Quarterly Revenue Report from EDA Consortium

China has been a growing market for EDA tools and Chinese consumers have purchased a significant number of semiconductors based products in the recent past.  Consumer products demand is slowing, and China’s financial health is being questioned.  The result is that demand for EDA tools may be less than in 2015.   I have received so many forecasts for 2016 that I have decided to brake the subject into two articles.  The first article will cover the macro aspects, while the second will focus more on specific tools and market segments.

Economy and Technology

EDA itself is changing.  Here is what Bob Smith, executive director of the EDA consortium has to say:

“Cooperation and competition will be the watchwords for 2016 in our industry. The ecosystem and all the players are responsible for driving designs into the semiconductor manufacturing ecosystem. Success is highly dependent on traditional EDA, but we are realizing that there are many other critical components, including semiconductor IP, embedded software and advanced packaging such as 3D-IC. In other words, our industry is a “design ecosystem” feeding the manufacturing sector. The various players in our ecosystem are realizing that we can and should work together to increase the collective growth of our industry. Expect to see industry organizations serving as the intermediaries to bring these various constituents together.”

Bob Smith’s words acknowledge that the term “system” has taken a new meaning in EDA.  We are no longer talking about developing a hardware system, or even a hardware/software system.  A system today includes digital and analog hardware, software both at the system and application level, MEMS, third party IP, and connectivity and co-execution with other systems.  EDA vendors are morphing in order to accommodate these new requirements.  Change is difficult because it implies error as well as successes, and 2016 will be a year of changes.

Lucio Lanza, managing director of Lanza techVentures and a recipient of the Phil Kaufman award, describes it this way:

“We’ve gone from computers talking to each other to an era of PCs connecting people using PCs. Today, the connections of people and devices seem irrelevant. As we move to the Internet of Things, things will get connected to other things and won’t go through people. In fact, I call it the World of Things not IoT and the implications are vast for EDA, the semiconductor industry and society. The EDA community has been the enabler for this connected phenomenon. We now have a rare opportunity to be more creative in our thinking about where the technology is going and how we can assist in getting there in a positive and meaningful way.”

Ranjit Adhikary, director of Marketing at Cliosoft acknowledges the growing need for tools integration in his remarks:

“The world is currently undergoing a quiet revolution akin to the dot com boom in the late 1990s. There has been a growing effort to slowly but surely provide connectivity between various physical objects and enable them to share and exchange data and manage the devices using smartphones. The labors of these efforts have started to bear fruit and we can see that in the automotive and consumables industries. What this implies from a semiconductor standpoint is that the number of shipments of analog and RF ICs will grow at a remarkable pace and there will be increased efforts from design companies to have digital, analog and RF components in the same SoC. From an EDA standpoint, different players will also collaborate to share the same databases. An example of this would be Keysight Technologies and Cadence Designs Systems on OpenAccess libraries. Design companies will seek to improve the design methodologies and increase the use of IPs to ensure a faster turnaround time for SoCs. From an infrastructure standpoint a growing number of design companies will invest more in the design data and IP management to ensure better design collaboration between design teams located at geographically dispersed locations as well as to maximize their resources.”

Michiel Ligthart, president and chief operating officer at Verific Design Automation points to the need to integrate tools from various sources to achieve the most effective design flow:

“One of the more interesting trends Verific has observed over the last five years is the differentiation strategy adopted by a variety of large and small CAD departments. Single-vendor tool flows do not meet all requirements. Instead, IDMs outline their needs and devise their own design and verification flow to improve over their competition. That trend will only become more pronounced in 2016.”

New and Expanding Markets

The focus toward IoT applications has opened up new markets as well as expanded existing ones.  For example the automotive market is looking to new functionalities both in car and car-to-car applications.

Raik Brinkmann, president and chief executive officer at OneSpin Solutions wrote:

“OneSpin Solutions has witnessed the push toward automotive safety for more than two years. Demand will further increase as designers learn how to apply the ISO26262 standard. I’m not sure that security will come to the forefront in 2016 because there no standards as yet and ad hoc approaches will dominate. However, the pressure for security standards will be high, just as ISO26262 was for automotive.”

Michael Buehler-Garcia, Mentor Graphics Calibre Design Solutions, Senior Director of Marketing notes that many of the established and thought of as obsolete process nodes will instead see increased volume due to the technologies required to implement IoT architectures.

“As cutting-edge process nodes entail ever higher non-recurring engineering (NRE) costs, ‘More than Moore’ technologies are moving from the “press release” stage to broader adoption. One consequence of this adoption has been a renewed interest in more established processes. Historical older process node users, such as analog design, RFCMOS, and microelectromechanical systems (MEMS), are now being joined by silicon photonics, standalone radios, and standalone memory controllers as part of a 3D-IC implementation. In addition, the Internet of Things (IoT) functionality we crave is being driven by a “milli-cents for nano-acres of silicon,” which aligns with the increase in designs targeted for established nodes (130 nm and older). New physical verification techniques developed for advanced nodes can simplify life for design companies working at established nodes by reducing the dependency on human intervention. In 2016, we expect to see more adoption of advanced software solutions such as reliability checking, pattern matching, “smart” fill, advanced extraction solutions, “chip out” package assembly verification, and waiver processing to help IC designers implement more complex designs on established nodes. We also foresee this renewed interest in established nodes driving tighter capacity access, which in turn will drive increased use of design optimization techniques, such as DFM scoring, filling analysis, and critical area analysis, to help maximize the robustness of designs in established nodes.”

Warren Kurisu, Director of Product Management, Mentor Graphics Embedded Systems Division points to wearables, another sector within the IoT market, as an opportunity for expansion.

“We are seeing multiple trends. Wearables are increasing in functionality and complexity enabled by the availability of advanced low-power heterogeneous multicore architectures and the availability of power management tools. The IoT continues to gain momentum as we are now seeing a heavier demand for intelligent, customizable IoT gateways. Further, the emergence of IoT 2.0 has placed a new emphasis on end-to-end security from the cloud and gateway right down to the edge device.”

Power management is one of the areas that has seen significant concentration on the part of EDA vendors.  But not much has been said about battery technology.  Shreefal Mehta, president and CEO of Paper Battery Company offered the following observations.

“The year 2016 will be the year we see tremendous advances in energy storage and management.   The gap between the rate of growth of our electronic devices and the battery energy that fuels them will increase to a tipping point.   On average, battery energy density has only grown 12% while electronic capabilities have more than doubled annually.  The need for increased energy and power density will be a major trend in 2016.  More energy-efficient processors and sensors will be deployed into the market, requiring smaller, safer, longer-lasting and higher-performing energy sources. Today’s batteries won’t cut it.

Wireless devices and sensors that need pulses of peak power to transmit compute and/or perform analog functions will continue to create a tension between the need for peak power pulses and long energy cycles. For example, cell phone transmission and Bluetooth peripherals are, as a whole, low power but the peak power requirements are several orders of magnitude greater than the average power consumption.  Hence, new, hybrid power solutions will begin to emerge especially where energy-efficient delivery is needed with peak power and as the ratio of average to peak grows significantly. 

Traditional batteries will continue to improve in offering higher energy at lower prices, but current lithium ion will reach a limit in the balance between energy and power in a single cell with new materials and nanostructure electrodes being needed to provide high power and energy.  This situation is aggravated by the push towards physically smaller form factors where energy and power densities diverge significantly. Current efforts in various companies and universities are promising but will take a few more years to bring to market.

The Supercapacitor market is poised for growth in 2016 with an expected CAGR of 19% through 2020.  Between the need for more efficient form factors, high energy density and peak power performance, a new form of supercapacitors will power the ever increasing demands of portable electronics. The Hybrid supercapacitor is the bridge between the high energy batteries and high power supercapacitors. Because these devices are higher energy than traditional supercapacitors and higher power than batteries they may either be used in conjunction with or completely replace battery systems. Due to the way we are using our smartphones, supercapacitors will find a good use model there as well as applications ranging from transportation to enterprise storage.

Memory in smartphones and tablets containing solid state drives (SSDs) will become more and more accustomed to architectures which manage non-volatile cache in a manner which preserves content in the event of power failure. These devices will use large swaths of video and the media data will be stored on RAM (backed with FLASH) which can allow frequent overwrites in these mobile devices without the wear-out degradation that would significantly reduce the life of the FLASH memory if used for all storage. To meet the data integrity concerns of this shadowed memory, supercapacitors will take a prominent role in supplying bridge power in the event of an energy-depleted battery, thereby adding significant value and performance to mobile entertainment and computing devices.

Finally, safety issues with lithium ion batteries have just become front and center and will continue to plague the industry and manufacturing environments.  Flaming hoverboards, shipment and air travel restrictions on lithium batteries render the future of personal battery power questionable. Improved testing and more regulations will come to pass, however because of the widespread use of battery-powered devices safety will become a key factor.   What we will see in 2016 is the emergence of the hybrid supercapacitor, which offers a high-capacity alternative to Lithium batteries in terms of power efficiency. This alternative can operate over a wide temperature range, have long cycle lives and – most importantly are safe. “

Greg Schmergel, CEO, Founder and President of memory-maker Nantero, Inc points out that just as new power storage devices will open new opportunities so will new memory devices.

“With the traditional memories, DRAM and flash, nearing the end of the scaling roadmap, new memories will emerge and change memory from a standard commodity to a potentially powerful competitive advantage.  As an example, NRAM products such as multi-GB high-speed DDR4-compatible nonvolatile standalone memories are already being designed, giving new options to designers who can take advantage of the combination of nonvolatility, high speed, high density and low power.  The emergence of next-generation nonvolatile memory which is faster than flash will enable new and creative systems architectures to be created which will provide substantial customer value.”

Jin Zhang, Vice President of Marketing and Customer Relations at Oski Technology is of the opinion that the formal methods sector is an excellent prospect to increase the EDA market.

“Formal verification adoption is growing rapidly worldwide and that will continue into 2016. Not surprisingly, the U.S. market leads the way, with China following a close second. Usage is especially apparent in China where a heavy investment has been made in the semiconductor industry, particularly in CPU designs. Many companies are starting to build internal formal groups. Chinese project teams are discovering the benefits of improving design qualities using Formal Sign-off Methodology.”

These market forces are fueling the growth of specific design areas that are supported by EDA tools.  In the companion article some of these areas will be discussed.