EDA revenue increased nearly 18% in Q2, rising to $1.44 billion compared with $1.22 billion in the same period in 2010, according to the latest EDA Consortium numbers. Revenue was down 0.6% sequentially from Q1.

All geographies were up, year over year, with double-digit growth in the Americas, Japan, and Asia/Pacific. In addition, EDA employment was up about 3% year over year, and 1% sequentially. In the Americas, revenue was up 21% year over year; 18% each in Japan and Asia/Pacific, and 9% in Europe, the Middle East and Africa.

By category, CAE grew about 20%; IC physical design and verification grew 6%; PCBs and MCMs grew 22%; intellectual property grew 23%, and services revenue increased 20%.

EDA companies weren’t the only ones showing optimism. Semico Research issued its forecast that analog within the computing consumer and communications markets will grow 14%, 9% and 13% in 2011, 2012 and 2013 respectively.

Semico anticipates the market for analog will reach $61.9 billion in 2015. What’s particularly interesting is the consumer market will only account for about 23% of that number in four years; it currently represents 33% of the total analog pie.

Open-Silicon’s CEO talks with System-Level Design about getting the business priorities of designing a complex SoC in line with the technology; why getting chips out the door on time is critical and why it’s not happening.

By Ed Sperling
System-Level Design sat down to discuss what’s broken in EDA with Riko Radojcic, director of engineering for CDMA Technologies at Qualcomm; Surinder Dahaliwal, executive director for VLSI Core Engineering at Mindspeed Technologies; Andy Brotman, vice president of design infrastructure at GlobalFoundries, and Paul McLellan, a start-up CEO and blogger. What follows are excerpts of that conversation.

SLD: Where are the problems in chip design these days?
Brotman: We are taping out chips and getting chips out the door, but the real issue we’re see is time to volume. There’s lots of stuff that would allow us to get that fixed and ramp to volume sooner. At advanced nodes there are all sorts of new effects. We need better ways to analyze them to get to working silicon sooner. That includes all the stress effects, layout effects. How do we take layout effects into account early—maybe even estimate them.
Radojcic: We are working on the leading edge, and my sense of what’s broken is the stuff on the fringes of traditional EDA.

SLD: Where there isn’t enough volume to make it worthwhile for the big EDA companies to invest?
Radojcic: Yes. Five years ago the things on the fringes included DFM. A startup company needed to hire one or two guys to understand DFM. Now the fringes are package-chip co-design, or hardware-software co-design. They’re quite broad, fairly separate disciplines, and it’s a hard thing for startups to span and it’s not quite big enough for the big companies to feed yet. That’s where the gap is right now.
Dahaliwal: The industry has been focused on the physical side for some time with DFM and the tools that allow people to get reasonable yields and predict their yields. What they haven’t been focused on is the implementation side. When you have 100 clocks in a chip and get all those clocks synced up correctly, that brings up all sorts of new issues. I agree with the comment about co-design, as well. You may have a chip ready to go but it typically takes you another two years to develop the software. How do you bridge that gap? People have tried to do it with modeling tools, but you can’t model everything. The industry is going through an FPGA prototyping phase now. That will help drive software development ahead of silicon.

SLD: Is Qualcomm doing FPGA prototyping?
Radojcic: We do for some chips.
Dahaliwal: The FPGA gives you the test benches. Either you need a whole new testbench verification or you wing it.

SLD: Are more things broken at each new node, or is it the same stuff plus new stuff?
Radojcic: The new stuff amplifies the Band-Aid from the last node. Stress is a good example.
Brotman: Yes, it was always there but it wasn’t as significant.
Radojcic: Right, we didn’t worry about it. With 3D [stacking] we start worrying about stress in spades. It’s thinning down silicon to nothing.
Brotman: The hardware-software issues are getting bigger because things are getting so complex. And then there are physical effects that are becoming more important. They’ve always been there, but they haven’t been as important. I remember doing a study on the effect of fill at 65nm and it was negligible. At 28nm it’s not negligible.
Radojcic: That was always there, too. But what technology tends to make harder at every node has been something that a point tool could solve. What’s new is that point tools can’t solve it.

SLD: How about the big flows from Synopsys, Mentor and Cadence? How are they holding up?
Brotman: They’re adding stuff. All three of them and Magma have timing-aware fill. They force you to use a DRC (design-rule checking) tool you’re not used to using. It would be smoother with better standards and integration.
Radojcic: They are adding stuff on the leading edge of mainstream. One can argue they’re too slow. But with the fringes they’re not sure it’s going to be big enough. Synopsys has all the pieces, particularly after all the acquisitions. But I don’t see them driving this yet.
Brotman: But even with co-design, they’re talking about the need to develop models to do the co-design. Typically those are more abstract than synthesizable Verilog. On the analog side, you need models for that, too. We don’t see a whole lot of activity in connecting those models to what you’re implementing. Sometimes there’s a disconnect between your model and the analog block.
Dahaliwal: In order to do that you need all the models.
Brotman: And they need to be matched to what you’re implementing.
Dahaliwal: Exactly.
Radojcic: Which is part of the problem. Qualcomm does architectural work and hardware-software co-design two years before the technologies exist. Sitting and waiting for all the pieces—the early development stuff needs to happen two years before the technology exists.
Dahaliwal: And that’s definitely difficult for a small company.
Brotman: It’s also new for the chip developers. They have to develop models, in languages you don’t know.
Radojcic: It’s being able to do early estimating of a design to find the sweet spot for architecture and process technology before all the pieces are in place if you want to tape out at the leading edge.

SLD: The most advanced chip developers have no choice, right? That goes with the turf.
Radojcic: Yes, and in the past you could do that. A smart guru could sit down and say, ‘I know what’s going to happen at 45nm after doing a tapeout at 65nm, or 28nm after 45nm.’ You know it’s going to be smaller and leakier. When a disruptive technology like 3D comes in, you can’t extrapolate from your experience into the future.

SLD: Is it broken or just uncharted?
Radojcic: The fact that we’ve doing all of this early stuff based on a guru’s gut feeling means it’s broken. In uncharted water, that isn’t good enough anymore. So it’s broken.
McLellan: When we’ve had disruptive technologies come along in this industry, historically it’s been startup companies that produce the technology and big companies that apply them. There are almost no examples of big companies generating this stuff internally. Calibre is probably the one big exception. But startups aren’t being funded anymore. It’s not clear where this technology will come from. 3D technology is an example. There are people doing bits and pieces.
Radojcic: There are two issues here. One is that the things that are broken are too big for startups. The other is that startups aren’t funded. I think they will be. The recession is over. Startups will begin again. But the gaps are still too big for startups. Those gaps will remain even if there is funding.
Dahaliwal: What we’re also seeing is the EDA companies are focusing outside the EDA business. Synopsys is adding to its IP business. Cadence is buying Denali. How much will they invest in true EDA as opposed to leveraging adjacent markets?
McLellan: The business model for mainline EDA is broken. It used to be the case that you worked with the leading edge guys, then the mainstream would come through and that would be the cash cow. The mainstream doesn’t come through anymore.
Dahaliwal: The number of companies has gone down, too. There aren’t the companies out there to buy the tools. You’re left with a few large companies buying expensive tools and the small guys trying to live with the tools they have, taking them off maintenance.
McLellan: The small guys are doing FPGA design.

SLD: What you all seem to be agreeing on is that the business model for EDA needs to change, right?
Radojcic: We get the EDA we deserve and are willing to pay for.

SLD: But at the same time, you need EDA more than ever to solve some of these issues.
Radojcic: There’s no doubt that its scope is expanding. The EDA business model grew up when the industry was in expansion mode.
McLellan: The ideal business model for EDA is when loads of people are doing designs and lots of lots of them need tools.

SLD: How about IP? How much of a chip uses third-party IP?
Dahaliwal: In our chips it’s a very large percentage of the content. It’s external IP you build into an architecture. You wrap your own IP around it.
Radojcic: We use a lot of third-party IP, whether it’s soft, like ARM, or harder stuff, like SerDes.
Brotman: We work with the IP vendors. When we’re doing IP with a lead customer and we’re developing it with the IP vendor, there are DFM signoff models. I’ve seen IP that’s better quality and some that’s worse quality from a manufacturing standpoint. A lot of times when we’re working on the development of the IP, there are DFM criteria for them to get paid for the IP.

System Level Design talks with Tom Quan of TSMC, John Koeter of Synopsys, Kalar Rajendiran of eSilicon and Phil Yastrow of Avago about where the value has shifted in the semiconductor design chain and why.

By John Blyler

Today’s newspapers and websites are cluttered with companies reporting increased revenues on lower sales. Simply put, this means that companies have laid off employees and cut other costs in order to show a profit. One big result of these cutbacks in workers, which this time included engineers and sometimes entire design teams, is that companies will have fewer resources to bring new products to market or to maintain existing product lines.

Such cuts may save the company money in the short term, but they may also limit what the company can do in the future. One interesting effect is to shift the task of product development further up the market supply chain. If an original equipment manufacturer (OEM) in the electronics market has cut its design team, it may mean the chip supplier to the OEM must now pick up the task of actually manufacturing their portion of the end-product.

While this is hardly a new trend, the recent downturn has accelerated it. Consider the case of Stretch, a fabless chip company that provides video surveillance and digital video recorder chips and add-in reference board designs to large end-product manufacturers. In the past, Stretch’s big focus was on developing complex video algorithm systems and associated intellectual property (IP) for the growing video surveillance market. Board-level reference designs for its chips were provided as matter of business, an essential but complementary part of its main business.

Today, however, Stretch’s OEM customers – the makers of commercial video surveillance equipment and video recording devices – are asking for a lot more. They now want Stretch to turn its board-level reference designs, which are basically prototypes, into high volume, manufacturability subsystem which the OEM will then incorporate into their larger end product.

Many start-up companies have been caught off guard by their customer’s requests to create the manufacturing ecosystem necessary for volume production of reference board designs. Bob Beachler, Stretch’s vice president of marketing, operations and systems design, explains that most start-up companies expect their customers to take the reference design, modify them as needed for product differentiation and then manufacture the modified designs themselves. Today, though, many of these same customers are asking the startup chip supplier to use the reference design as is and manufacture these designs in volume for the OEM.

What has this meant for a start-up like Stretch? “We’ve had to invest time – not really add more manpower – to find the right contract manufacturers to build the reference design board,” Beachler said. It has also meant that the chip company had to do all of the qualification (EMI) and environmental (shake-rattle-roll) testing, plus the defect screening. He confirmed that Stretch doesn’t do the actual manufacturing. That task has been outsourced to two firms in China. But the board-level manufacturing portion of the business has grown to become half of the company’s total business while the other half is surveillance chips—the place this all started.

This trend won’t work for every business. It seems to work best for well-defined products and markets, where form factors of the boards (add-in cards) and functionality are standard. Beachler said that two pioneers of this approach are Intel in the CPU and CPU motherboard market, and nVidia in the graphics card space. Both of these companies were primarily chip companies that expanded to include a system-level (printed circuit board) business.

Both companies now do substantial volumes in board-level manufacturing, even though they have an ecosystem of other manufacturers that make similar products. For example, Intel produces several slightly different motherboards for a given chipset. But companies like Asus, Gigabyte, MSI and others take Intel’s basic reference designs and customize them to produce a wide variety of mother boards. Such supply-chain companies then sell these boards in volumes that far outstrip the Intel’s versions.

The trend toward more complete system solutions within the semiconductor and board-level supply chains is nothing new. What is new is the disappearance of design teams within some of the OEMs. That is a development that is being watched closely by many within the chip design industry.

By Cheryl Ajluni

On Monday, October 12, the National Association of Business Economists (NABE) announced the results of a survey of professional forecasters regarding the economy. Their consensus was clear: the worst U.S. recession since the Great Depression has ended. While many Americans still think the country’s economy is in poor shape, a CNN/Opinion Research Corp. poll taken between Oct. 16th and 18th seemed to echo this sentiment—a growing number of Americans think the worst of the recession is over.

For the electronics industry, there also appears to be a bit of good news. According to Gartner, the end-user electronics industry is in the early stages of recovery. The mobile-phone market will likely be the first sector to show sustainable recovery, starting in the first quarter of 2010.

Given the economic turmoil of the last few years, any sort of economic recovery sounds good, but if anyone in the electronics industry believes things will go back to business as usual they may be in for a rude awakening. The rules of engagement have most definitely changed. Nowhere is this more evident than when it involves system engineers charged with developing and designing new electronic products. For them, creating that next killer product now requires more than just a great idea, money and resources for development, the right design tools, and a bit of luck and good timing. It may also require something that many of them have never even considered—social media.

For those engineers who spend more time correctly focused on the nuances of their design tools and their design, as opposed to the intricacies of the Internet and its impact on society, let me take a moment to bring you up to speed. Social media is really exactly what it sounds like—the various forms of media available on the Internet that enable people to be social. That media could be some sort of platform or service, essentially anything that allows people to interact and network (Figure 1).

Prime examples of social media platforms and services include facebook, flickr, Linkedin, MySpace, twitter and YouTube. People commonly use facebook to keep tabs on friends and family. Linkedin offers a way for professionals to stay linked into professional organizations, networks and with other colleagues in their respective fields. MySpace and twitter enable people to share pertinent information and their thoughts on a whole range of topics and interests. YouTube needs no explanation and flickr is primarily for sharing video along with images. Each of these platforms and services, in their own unique way, help define social media. Most are things that engineers have likely come across in their personal lives. Social media has even begun crossing over into the business world for use in customer support and sales and marketing. Perhaps what’s more interesting though is that, when used appropriately, it can also play a critical role in electronic product development.

Figure 1. Social media encompasses different concepts all related to technology, social interaction and building/providing content such as text, photos or videos. Graphic source.

How exactly can social media aide in product development? Consider a very basic example. Imagine that Joe, a system engineer, wants to design the next great smart phone. Perhaps he has a starting concept in his head and simply wants to refine it, or maybe he just doesn’t quite know where to start. So he checks various blogs to see if there are any complaints/problems or positive comments about functionality in his last smart phone design. He may even go to Linkedin to connect with like-minded professionals to discuss possible features that might be incorporated into the design. Or, he could check out a forum of existing smartphone users to see what they are talking about—do they have any likes or dislikes with their current phones, for example? (Figure 2) Given all this information, Joe is able to get a clearer idea of what existing and potential future customers want. He can then translate these needs into specific, concrete requirements for his design.

Figure 2. Designers wanting to keep up with consumer’s views/reviews on existing smartphones might access a social media platform like the Smartphone Blast! Forums. This site is the smartphone source for shareware, Visor freeware, reviews, hardware, discussion, and more.

Essentially, by using the information obtained from social media, Joe is able to turn his product development process from an art into a science. It allows everyone involved in the product development to more freely communicate and collaborate, not just internally but with customers and suppliers. It also enables Joe to find out information about customer’s changing requirements that he can use to very quickly revise next product variants in an existing line of products.

Such functionality may prove critical for system designers, especially considering that a lot has changed since the recession began. As Klaus Rinnen, managing vice president at Gartner’s semiconductor manufacturing group, points out, “The damage from the current industry recession will be felt for a long time. This is seen in our current five-year semiconductor revenue forecast, which does not show recovery to 2007 levels until 2012. Vendors must prepare for significant changes in consumer buying behavior, technology demand patterns and a changed supplier landscape.”

In other words, as consumers in the United States and around the world see their disposable incomes rise, end-user requirements may change. Being able to effectively key into their new wants and needs will therefore be critical to developing that next killer electronic product or hot new product feature. Social media offers one viable solution to this dilemma and as a result, is fundamentally changing the way companies work and yes, even the way design teams may work one day.

For anyone looking to employ social media in product development, there are a few things to remember.

• Using social media for product development is not the same as using it for marketing—don’t treat it as if it were. Insights obtained from social media are generally used for product marketing and public relations, but today there are also social media monitoring and analysis solutions that can provide insight into consumer-generated content for use in product development activities.
• You will need to engage communities to help shape your product design, but you don’t want to end up with a product that appeals to only a small, niche market. Therefore, making sure you engage the right forums, communities and so on is crucial.
• Rather than using social media haphazardly, you should establish a framework for including it in your product development. As Gartner pointed out in its 2009 Top 10 Strategic Technologies document, social software in all its shapes and forms (e.g., social media, social collaboration and social validation) is something organizations need to consider, now rather than later, since the greatest risk lies in failure to engage by coming too late to the party.
• Employing social media for product development has been done before, so don’t jump in head first without taking the time to check out your available resources (e.g., case studies and best practices). One resource to check out is the “Using Social Media for Product Development” event archived at Forrester Research.

If there is one thing that’s been made clear by the battle-scarred global economy, it’s that things can’t and won’t continue the way they always have. This definitely holds true for the development of electronic products. Social media, an offspring of the continuing evolution in communications, may very well prove to be a key weapon in the system engineer’s quest to design and develop the next killer electronic product.

By Ed Sperling

System-Level Design sat down with Simon Bloch, vice president and general manager of ESL/HDL Design and Synthesis at Mentor Graphics; Mike Gianfagna, vice president of marketing at Atrenta; and Jim Hogan, a private investor. What follows are excerpts of a lively, often contentious two-hour conversation.

SLD: Where does the consolidation happen in the chip design world?

Gianfagna: It looks like an upside down triangle. At the top are the systems guys. They will differentiate, if not in hardware then in software. The guys in the middle who are creating the silicon building blocks and building the platform—that’s where the consolidation will happen. Below them in the foundry area there will be even more consolidation. But as you go up that inverted pyramid, now there are more users for new cell phones, netbooks and strange devices we haven’t thought about. Maybe there’s hope that as you serve that top part of the inverted pyramid that EDA can provide enabling value to bring those platforms to a broader range of users. There’s new money to be made.

Hogan: I’ve been scratching my head for weeks about what does (Intel’s) Atom being made by TSMC mean. Microsoft is Intel’s biggest partner, so all those applications run on Intel or AMD. ARM runs Linux. So now that Intel goes to TSMC at 28nm and you have a bootable Microsoft address sitting on the Atom, do you use ARM or Atom? Which market do you go after? That gets interesting.

SLD: It’s a war, no doubt. Is that good?

Hogan: We’re going to build a model for Atom and a model for ARM Cortex12 and the DDR model, a simulator and a cockpit to manage all this. We want the battle to happen. Having a monolithic model is bad. TSMC logic is SoC. That’s been ARM alone up until now. Now it’s Intel and ARM SoCs. The world has gotten a lot more interesting.

Gianfagna: But tell me who is more responsive in listening to their customers and adding their input into designs, Intel or ARM? I’ll give you one guess.

Hogan: I agree with you. ARM has the ecosystem. But Intel doesn’t care about ARM. They only care about ARM because it’s an enabler for Qualcomm, Broadcom and Samsung. They build billions of units. What does Intel want to do? Build billions of units. This is all about ensuring they don’t lose the netbook market to ARM. The SoC is the way do it. That’s a huge opportunity for us.

Bloch: I think it commoditizes the chip implementation. It’s a block. It’s a very complex block, but it’s still a block.

Hogan: Let’s say it’s a hard block from Intel. We know that TSMC isn’t going to create that. We know Intel well enough to say that will never happen. So it gets laid out on Synopsys’ tools. Synopsys already has done a deal with Intel. There are no more incremental dollars for place and route because Intel has already paid for that. So the money that’s available to us is in the TLM space.

Bloch: Implementation is difficult, but it will be done. What’s important for managers is that these end products must be different from a competitor’s product. If the products have similar features, you compete on price. People are paying more and more attention to the system-level design. The level of worries is moving up to the system-level design rather than implementation.

SLD: So what do you need to make that happen?

Bloch: Architectural design, virtual prototyping of software, verifying the system fast and designing your new functionality quickly through high-level synthesis.

SLD: How much of a factor is time to market now? We hear a lot of stories about missing deadlines and market windows.

Hogan: The Chinese semiconductor companies don’t have back ends. They just have front ends.  What I think will happen is they’re going to go to eSilicon and have them do all of that stuff for them. They’re going to hit it 80% or 90% first-time silicon because they have the methodology to do that.

Bloch: These misses happen when companies do a napkin design instead of a system-level design. They say, ‘This is what we’re going to build, this is the functionality and this is the power consumption.’ Then they go and build it and it doesn’t do what they expect.

Gianfagna: But people don’t admit it, and you’ll never hear about it. Time-to-market pressures are alive and well. Most of the market is consumer-driven and the consumer market will always be fast-paced.

Hogan: That back-end semiconductor process is a fixed time. It will take you nine months from logic to tapeout, if you’re really good, and then 12 weeks for manufacturing. You can’t get around that. The fact that you do it right once and get to market, that’s great. If you don’t do it right, that’s where you’re going to burn through a lot of money.

Gianfagna: We can talk about the sophisticated things like IP. But there are fundamental issues. If you have a complex project and you do a poor job of planning, implementation is a mess.

Hogan: This is what Nokia is really good at. Their platform is two generations and they spend about two years getting there. They have a virtual platform that they do the software development on and they can hand it off to NXP. You’re ready to ship 20 million units in two years, and they do it time after time.

SLD: That’s compared to the old days when they used to do 20 platforms in 1 year.

Hogan: They can’t do that anymore. And the guys right behind them are Samsung.

SLD: Will we start seeing consolidation of virtual platforms?

Hogan: If you start with cell phones, there are about six major players. At least one will go out in the next year. And of those who remain, how many have the money to invent a new platform every two years? Nokia will have three phones—high end, midrange and low-end. So yes, there will be fewer platforms.

SLD: As business decisions increasingly drive technology, do we see less innovation?

Bloch: I don’t think so. People are less patient and more interested in faster cycles of innovation. Product cycles are shrinking.

Gianfagna: In a vibrant economy, there will be new markets for new applications. Below that, which includes the silicon version and building blocks, there will be consolidation.

Hogan: And if you have a really strong balance sheet you begin buying up companies, which is what Intel is doing.

SLD: Are we still talking about EDA companies, or are these now broader in focus?

Hogan: No, it’s now system design automation.

Gianfagna: There are new markets above the traditional EDA market. It will be healthy for some suppliers. Above that, there is opportunity. Does that become traditional EDA or is it vertical-market focused? I’m not sure.

Hogan: If I’m going to bet on one area, it’s going to be the mobile/wireless market.

Bloch: Computing, wireless, imaging and video are all converging.

SLD: Let’s go back here. Does the end market drive the technology or does the technology drive the market?

Gianfagna: And that will slow down innovation. If you think about whether technology is driving the market or the market is driving technology, I think it’s a hybrid. What if Atom had 1,000 embedded processors in it, would that drive cell phone use? Absolutely. But it isn’t one thing driving the other. There’s a symbiotic relationship. As long as both are advancing in lock step, we have a healthy business.

Bloch: It’s what you want versus what you need. The price points have gotten to the point where what you want may not be what you need. If design costs skyrocket, these prices will go up.

Hogan: Would you ever have dreamed a decade ago that there would be 10 million text messages an hour in the United States? 

The stock market came roaring back to life on news that Wells Fargo Bank had a stellar quarter and job losses—still not good—were at least not worse than before.

You wouldn’t know that over at TSMC, which has held steady throughout the downturn. The foundry issued an announcement that it had terminated 200 employees due to what it called “deteriorating business conditions.” Chartered Semiconductor went through that exercise last year.

Job losses are a trailing indicator, though. The rest of the economy appears to be at least stabilizing, while the stock market, which is always volatile, is an early indicator of recovery. It goes up first, and it goes down last. Go figure.

Virage Logic inked a deal with IBM over the PowerPC platform, a deal that has more significance than you might guess. IBM has been building an ecosystem of partners, and one of the big attractions is legal protection over IP. IBM lawyers are legendary, even if they don’t always win. When the company went up against the U.S. Justice Department in 1955 (and subsequently lost in 1956) it had a photo taken of its team of 100 lawyers. All of them were impeccably dressed, of course. 

Synopsys rolled out a multicore version of its Discovery platform, both for multicore designs and running multicore systems. This is a trend, and others have already have hammered a stake in the ground. 

Mentor Graphics, meanwhile, added advanced low power features to its Olympus place-and-route platform, which is almost a prerequisite in any toolset these days. This is another trend, and they’re not alone here.

By Ed Sperling

The market for EDA and IP was down in Q4 of 2008. That should come as no surprise to anyone.

Nevertheless, there were a couple of bright spots even in that bleak picture. Statistics compiled by the EDA Consortium show IP sales were up 7.6 percent, which is a reflection of increased complexity in making SoCs at 65nm and 45nm, as well as better tools and standards for integrating that IP.

IP is about a $1 billion market, according to EDAC Chairman Wally Rhines. Within that sector, ARM is by far the largest single provider of IP and posted most of the gains, he said. Other beneficiaries include MIPS, Virage Logic, Denali, the IP divisions of Mentor Graphics and Synopsys, and a number of smaller players.

Other bright spots:

·      Parasitic extraction, up 10%

·      Process simulation, up 18%

·      Mixed Signal, up 39%

·      Services, up 25%, although much of that is due to eliminating contractors and taking the work in-house.

Most of the growth follows the trends in system-level design, with the greatest growth showing up in the areas of most pain. Since those numbers were recorded, however, there also are glimmers of life in other parts of the industry.

“What we’re seeing is a bounceback from desperation in the fourth quarter to a point now where there is a need for finished goods,” Rhines said. “The February [Semiconductor Industry Association] numbers were negative. In March, there were signs of a bounceback. But the semi industry and electronics tend to sort out early and prices readjust. EDA is one level removed from semiconductors, which makes it harder to read anything into the numbers.”

The total EDA industry was down 17.7%. But industry sources say at least part of that was skewed by Cadence’s change in the way it recognizes revenue, from up-front recognition to recording revenue as it is received. Taking Cadence out of the picture, the industry declined about 8%. That’s still severe, but at least it’s a single-digit decline.

Still, the tools industry is hardly on solid ground. More than half of semiconductor companies are rated “B” or worse. If a number of semiconductor companies go out of business, the overall effect on the EDA industry would be profound.

On a global basis, Europe’s decline was in the single digits while the rest of the world showed double-digit declines. Europe is very system-oriented, but some of its chip makers have stumbled badly in the downturn. 

If you think things are bad, be glad you’re not in the Taiwanese foundry business—where the pain level is strangely uniform.

TSMC’s sales dropped 59.5% in February compared to the same month last year, and 7.5% compared to January. How many ways can you spell ouch? 

UMC’s numbers are down 56.9 percent in February 2009 vs. the same period in 2008. That’s pretty close. In fact, it’s remarkably close.

This kind of information is only available in Taiwan. SMIC, based in Shanghai, and Chartered, based in Singapore, don’t report monthly sales numbers.

Nevertheless, there was at least some encouraging news out of Chartered. It said that sales seem to be stabilizing and wafer starts appear to be increasing for Q2. 

There is evidence of this showing up in other parts of the market. U.S. retail sales, excluding big-ticket items like cars, show modest increases in areas like clothes and consumer electronics. Numbers were up in January and February. It certainly wasn’t a robust gain, but it wasn’t negative, either. That will translate into new design starts sometime in the next few months, which barring any more major drops will start this whole cycle rolling again.

Design activity has to begin at least six months prior to any turnaround, which means that if the overall economy is expected to show growth in 2010,  electronic designs have to begin by mid-year—perhaps even sooner.

None of this is perfect, however. Why, for example, did National Semiconductor just announce plans to cut 26% of its workforce? At least part of that can be explained by closing of an assembly and test plant in China and a fab in Texas. Too much capacity is expensive, and we wouldn’t be surprised if National ultimately begins outsourcing some of its work to foundries. Yes, it’s analog, but is it still more efficient to run fabs yourself, even if they’re fully depreciated, when TSMC and UMC are begging for business?

Meanwhile, in the FPGA realm, chip design is getting so complex that EDA vendors are finally beginning to find inroads. This is a market previously owned by tools from the FPGA vendors, which they readily gave away to customers at little or even no cost. That worked fine before the industry got to 90nm, and at 45nm it’s tough enough even with the best of tools.

Mentor introduced its Precision Synthesis Tool family for Altera’s Stratix and Arria families. Our guess is that you can expect to see a lot of activity in this market in the near future, and not just from Mentor. Synopsys’ purchase of Synplicity gives it a vested interest in the FPGA market, as well.

–Ed Sperling