By Ann Steffora Mutschler

With the cost of failure at an astronomical high, the last thing chip designers want to worry about is the physical IP they will use to build their SoC.

In addition to less willingness on the customer’s behalf to take risks, complexity and economics have driven the need for more off-the-shelf IP and a corresponding rise in interest in verification IP. Compounding matters, IP investments are being stretched out for longer periods of time than in the past. That has made verification IP even more popular. Confidence in IP is critical, and this comes through a comprehensive IP validation discipline on the part of the IP provider.

However, the maturation of any method or tools means new focus on them, and so far the design industry has not even settled on what the optimal methodology should be for IP verification.

As a starting point, it helps to define types of verification. First, there is an intense level of unit-level verification where compliance to the relevant protocols is focused on and where the functionality of the block itself is detailed, said Mark Gogolewski, CTO at Denali Software. In addition, there is a separate step during which the subsystem or the system is constructed, with verification at this point being very different.

“For a time, there was a lot of IP verification when you had a bigger subsystem, but these days, the IP gets completely wrung out at the unit level and then when you construct the system, you are focused much more on connectivity and dataflow and how the system interacts,” he explained.

“If you are testing an IP block, there are two major dimensions of verification challenge. One is the protocols that are relevant to the IP block, and the other is the functionality, which is making sure the microarchitecture that was used to design the IP was correctly implemented,” Gogolewski said. “Correct” can have many meanings in terms of correct function and leading off performance objectives of that particular block of IP, he noted.

“Verification is all about observability and control. You need to make sure you are observing every aspect of the protocol, but then you have to give the customer control. One dimension for memories is giving easy control of the data space, and another is error injection and that’s another level of investment has to be made,” he added.

Carl Ruggiero president and CEO of Trilinear Technologies, agrees that common definitions of IP verification need to be established. “Depending on [a customer’s] point of view, everyone has a different idea of what verification ought to be, and that’s really making our job very challenging. Everybody says they want verification, but right now there is really no defined vocabulary for it. You cannot call it gates and flops like you can on the design side. People want to talk about coverage and percent of coverage, but at the same time coverage is very subjective. You can get 100% coverage with five coverage points. Therefore, it is hard to say what good coverage is because if you have 300 coverage points, you might be missing that 301^st, which is the critical one. How do we go about putting metrics on it? How do we define the vocabulary so we can all speak the same language? We struggle with this on a daily basis.”

In an effort to start out clearly with customers, Ruggiero says Trilinear talks about its verification in terms of functional coverage. “We talk about the actual things that we set out to do. We talk about garnering 100% functional coverage. While we don’t say that we’ve tested every ad nauseum combination of things, that for the things that our software drivers and reference drivers, the functions that are listed in the data sheet and in the specification, those are the ones we’ve tested to.”

IP Verification Challenges

Ken Brock, director of physical IP marketing at Virage Logic, said that when it comes to IP validation specifically for on-chip physical IP, challenges and solutions can include taking a standard cell library of more than 1,600 unique circuits and running them through one of several EDA vendors synthesis tools, running them again through the same or different EDA vendors’ physical synthesis/place and route tools and have them all work perfectly; taking a memory compiler with a dozen different knobs and switches and producing a fully functional memory IP over the number of words and bits with multiple aspect ratios, test options and power optimization configurations; mixing them together with other IP on an SoC; and doing all of these things over the full speed, voltage, temperature and process variability extremes of a specific leading edge silicon process.

He noted that the IP validation process requires a rigorous discipline, which includes unit validation, integration testing, platform validation and silicon validation.

Indeed, IP giant ARM is pursuing just that. Tom Lantzsch, VP of ARM’s Physical IP Division noted, “We spend a lot more time with the EDA partners integrating our IP under their flows much earlier and having them leverage it and test it themselves. It is a constant activity because when we do our verification, unlike an internal supplier, which probably has a limited EDA flow, and maybe even a limited customer set within their company, we have to be much more systematic and have to create a verification environment that supports us for multiple years.”

The Cost of Providing Verified IP

Whether making an investment into a new technology for entrepreneurial reasons or encouraged by major customers, the latter of which Denali did with its entry into the PCI Express arena, making it pay off is no small task both to the customer and for the IP provider.

As Gogolewski explained, with the company’s entry into PCI Express, “the world got a lot more complicated because it is extremely configurable, programmable and complicated. What we mean by configurable is that before you even put a design in silicon there are many choices. We have a couple hundred choices in our configuration spec just to correctly specify what that particular device even looks like at a specification level. It is programmable because it has all sorts of register settings that have to be set correctly and which can change the behavior of the device. And then it’s just complicated—our engineers had to become experts on two to three thousand pages of documentation. We had to make sure all the functionality was in there with the flexibility and programmability; we had to make sure all of those thousands of pages of spec became error checks and assertions. And then the way that [PCI Express] protocol works, your IP has to both handle correct functionality and incorrect functionality and respond properly. So there was a multitude of error injection that we had to make available to our customers as well as our own design team to make sure that they could inject all these levels of errors and validate whether or not their design caught it correctly.”

To deliver this level of backup data to customers for PCI Express, Denali estimates the extra engineering effort required is equal to approximately 70 to 75 man-years of effort over 7 years, with about 550,000 lines of new code created, not including the company’s Purespec library code.

The IP Verification Horizon

In the next phase of IP verification, one thing is for sure—there will be more of it provided by third parties.

“We’re at a tipping point from ‘make unless you have to buy’ to ‘buy unless you have to make,’ and the current economic climate is going to accelerate that. Basically the fundamental premise of third party IP is that if it is a ubiquitous problem and it is solved well, then the market is overall more efficient and better off when a third party solves it, rather than each customer solving it on its own,” Gogolewski said.

He also sees more IP verification moving toward third party IP vendors, even though there will always be customers that will create their own IP to maintain their place on the very bleeding edge of design. And he believes coverage-centric verification will be embraced. “It used to be something that leading-edge design teams would use, but now it is becoming ubiquitous,” he said.

By Ed Sperling

It was all about profit loss and retrenchment last week for EDA’s Big Three.

Mentor Graphics expanded its displaced worker program to provide free training—read that as retooling—for out of work electronics designers and engineers. The company is offering classes in-person and online.

This is not only a good idea, it’s something more companies should be doing. Aside from the obvious goodwill benefits, where else can you get so many qualified engineers up to speed on your latest tools? Apple figured this out years ago by offering huge discounts on Macs in the K-12 grades. And just in case you’re out of work or know someone who is, click here.

Cadence Design Systems continued with business as usual—refreshing all of its major product lines—despite a hail of financial bullets flying around. The company posted a loss of $1.85 billion in fiscal 2008, almost all of it inherited by the new management team, including a loss on Mentor Graphics stock when Cadence tried to buy the company last summer and some restructuring charges. How many ways can you spell “ouch?”

At least some of that money ended up in the hands of rival Synopsys. The EDA market leader posted a 7.7% increase, year-over-year, for the quarter ended Jan. 31. Compared to Cadence’s huge loss, Synopsys had a profit of $52.4 million vs. $46.4 million the previous year. Don’t be surprised to see someone spinning donuts in Synopsys’ parking lot.

In the embedded processor world, ARM shipped its 10 billionth mobile processor. Just as a point of reference, this is the market that Intel is targeting with its new Atom processor. Needless to say, it has a lot of catching up to do–once it gets the power requirements down to something comparable.

In the FPGA world, there were positive signs emerging. Actel posted growth in Q4, up 1% from the previous quarter and 2% from the same quarter in 2007. Given the depressing news from many chip companies, this is good. Flat is the new up, and up is even better.

Over at Xilinx, the company rather quietly replaced former CEO and long-time chairman of the board Wim Roelandts with Philip Gianos, a venture capitalist. There must be some sort of trend underway in the industry that we’re not quite getting. Cadence’s new CEO, Lip-Bu Tan is a VC, too. Is it that hard for VCs to get a return on investment these days? Eight years ago you couldn’t drag these guys into corporate life. Now they’re popping up everywhere.

By Ed Sperling

Santa Clara, Calif.—Feb. 5, 2009—Cross-cultural communication has always had its challenges, but globalization is raising it from the level of nuisance to necessity.

Across the board, from systems companies to those that develop the tools to build the components that go into those systems, building international teams that can embrace a single corporate culture has emerged as one of the big business challenges.

“The main learning about having different sites around the globe is respecting the culture of where that site is,” Rich Goldman, vice president of strategic alliances at Synopsys, said during a panel at DesignCon. “Engineers are the same around the world, so there is a certain level of communication that always works. But at another level, cultures are very different. What you may think is the worst thing possible is a normal part of culture for another country. You have to go to that country to experience it. That’s the only way to overcome differences.”

And overcoming those differences is essential. Cisco’s vice president of engineering, Sri Hosakote, said globalization is a core competency of every company that does business in a global economy. “It’s a skill that is mandatory,” he said.

Hosakote said one of the keys is getting employees in other countries to understand the corporate mission the same way employees do in a place like Silicon Valley. That frequently requires bringing managers to the United States, letting them sit in on meetings and work in Silicon Valley and sometimes even enrolling them in executive courses at schools like Stanford. He said when that happens, “they get it.”

“It takes two to five years to get a culture of globalization,” he said. “Collaboration is the hardest piece. It’s particularly hard when it comes to multiple sites.

But there’s more to operating in a global environment than just a common vision. There also has to be an efficient structure everywhere. Brani Buric, executive vice president of marketing and sales at Virage Logic, said that for every situation—whether the operation is located in a place where labor is cheap or expensive—the office has to be optimized.

“What we’re seeing with globalization is just the first phase,” Buric said. “A couple of years from now this will go way beyond product engineering and R&D. New markets are opening and we will see good product specs for markets in places like China. There will be R&D, specs, marketing, implementation and a sales channel in these places.

One facet of globalization is outsourcing. While outsourcing continues to gain ground in markets such as IT services and support, many technology companies believe the cost differential is not enough to offset the benefits of having their own operation—whether it’s R&D or sales—in a foreign country.

“Sometimes running it ourselves is cheaper in some ways,” said Kirk Law, vice president of systems products engineering at NetApp. “There are a lot of different ways to measure value. It’s not just a spreadsheet decision.”

By Ann Steffora Mutschler

Santa Clara, Calif. — Feb. 4, 2009 — A recession is a good time to question what is accepted as common wisdom, as it is a time when the greatest innovations occur, according to Mentor Graphics Corp. chairman and CEO Walden Rhines.

Rhines, in his keynote address at DesignCon, observed that the prevailing thought on the EDA industry is that it has reached its maturity point. He said some data does support this: Growth rates in the 1990s were on average more than 17%, compared to the past 10 years of approximately 5% annual growth.

However, looking at venture capital spent on EDA, it is the mirror image of the growth slide. Through the mid-1990s, there was very little spent, but in the past decade the venture community has invested approximately $200 to $300 million per year into EDA.

In terms of industry consolidation, which many point to as an indicator of EDA industry maturity, Rhines explained that based on data the number of new startups remains at about 50 companies per year, which at some point are acquired by the larger players. With that in mind, it is interesting to note that the net result is that no consolidation actually occurs, he said.

On the positive side of EDA is the fact that the largest share of revenue for EDA comes from semiconductor R&D spending, which is a remarkably stable and growing number.

“EDA is a great place to be during a recession as compared to being in a semiconductor or systems company because the one thing that companies in the electronics business continue is the design of new products,” he said. “They can cut down their factories, cut off marketing, even cut back on their sales force. But the one thing they know is someday this recession will be over, and when it is, if they don’t have competitive products, then they’re out of business. So the one thing they do is keep design activity going and that shows up in the EDA numbers.”

There are other positives to EDA as well. Previously the number of electronics-related engineers that graduated was about 5% worldwide, but in recent years that has grown to about 7%, which will also help to sustain EDA.

How does EDA grow?

Due to changes in methodologies, EDA goes through periods of relatively flat revenue until it hits a growth spurt thanks to new technology or a dramatic new capability comes along.

“If we look at where the growth has been occurring over the last five years, you find in EDA the established methodologies really don’t grow much—about 5%. The growth is in the new problems that are being solved, the things that weren’t required not so long ago. Design for manufacturing and resolution enhancement were zero revenue for the industry in 1999.
They are now a $200 million to $250 million a year business helping people improve their yields, helping them improve their photolithographic resolutions,” Rhines said. “ESL? Years of almost no revenue. Now, finally taking off in the $200 million range. So, the newer the technology, the more likely it is to represent the majority of the growth that occurs in the industry.”

What really has to happen in EDA, he believes, is that there must be new problems to solve, and the market has to grow not by selling people more of the solution for the same problem but to attack new problems. Fortunately, there are many problems to be solved. “When you change the technology, you introduce discontinuities that change the design methodology and require new tools,” he said.

Considering what has been happening with EDA over time, Rhines believes the industry has been in a phase in between major design methodology problems. “If you don’t think 22nm will be a big problem, you should talk to some design engineers about computational lithography and other things. We just need for the new technologies or the new problems to emerge and we’ll see another growth spurt in EDA in addition to the fact that there will be more designers to require software to do the design,” he said.

By Ann Steffora Mutschler

As individual blocks of IP in an IC design grow to more than 1 million gates, making sure each block functions reliably and interfaces with the system properly is a make-or-break scenario for many companies.

For one thing, getting it right is absolutely critical as the semiconductor industry reaches its maturity point with margins harder to reach. Coupled with an industry-wide downturn, even the largest IDMs are looking outside their internal teams for non-differentiated IP, which is standardized physical IP that is not a differentiator in a design.

“One of the factors that this economy will generate is more outsourcing of IP, which has been a very significant trend over the last several years, with the largest IDMs outsourcing a significant amount of IP,” says John Koeter, VP of marketing for IP solutions at Synopsys Inc., who notes that 17 of the top 20 semiconductor companies in the world buy IP from Synopsys. “So it’s pretty significant. And this includes digital and mixed signal IP that historically has been something large companies have viewed as a core competency,”

He believes the strong movement toward outsourcing, especially interface IP such as USB, DDR, PCI and SATA, is occurring because those types of IP are hard to design and are getting more complex. However, he points out, they don’t fundamentally differentiate a design.

In addition to outsourcing, consolidation in the overall semiconductor industry has been a major driver in IP industry consolidation, says Brani Buric, executive VP of marketing at Virage Logic.

Buric defines physical IP as IP that resides close to the silicon, including all kinds of digital IP, analog IP, memories, logic and high-speed interfaces. “With every new process node, complexity of reliable development and quality assurance for physical IP is becoming more and more expensive, and more and more timing critical. With physical IP, the key criteria of consolidation is that the barrier to entry of new players in the commercial market is very high because the cost of development and silicon validation,” Buric explains.

A second type of IP can be labeled system-level or RTL-level IP, which includes microprocessors. “Here,” he says, “the situation is different because there are a couple of fundamental blocks like microprocessors where there is market separation around a few companies that are leading in certain applications.” Also in this category are blocks that have a definite market window and thus a short lifetime, such as WIMAX and Bluetooth.

That said, with cost as king, semiconductor and systems companies are squeezing expenses and redeploying their engineers from non-differentiating tasks to more core-differentiating tasks.

Who’s buying whom?

To support the outsourcing, IP providers have made a number of consolidating moves over the past several years aimed at streamlining the IP delivery process and improving reliability for customers.

Most notably, IP industry leader ARM bought Artisan, while rival MIPS acquired Chip Idea.

Synopsys has made a number of acquisitions over the last four or five years, including InSilicon, which added PCI and USB to the company’s IP portfolio. Next, the company acquired Accelerant Networks for high speed, mixed signal CERTES capabilities, followed by Mosaid, Cascade and others.

Meanwhile, Virage purchased Ingot Design Systems for its DDR capabilities and Impinj for multiple time programmable memory.

Other players, like Mentor Graphics Corp. have scaled their investments in the IP space back, although still engaging with existing customers, according to Bill Martin, general manager of Mentor’s IP Division.

It is widely agreed that this consolidation will continue and will be of benefit to customers.

Tom Lantzsch, VP of Arm’s PIPD Division, says the semiconductor industry is hitting its maturity point, and like other industries that hit their maturity point there are fewer opportunities.

“From that perspective, this entire consolidation process is going through a natural evolution that most industries go through,” Lantzsch says. “Combined with the fact that the complexity of the products that we are asked to service our customers with are increasing rapidly, there is a corollary that they cost much more for us to develop. Based upon the IP business model that most companies use that has an upfront licensing fee and royalties, to get that investment back unfortunately takes much longer than most of us want to think about.”

What does this mean to customers? “In many cases, an improvement,” he says. “Our customers are becoming more global. The demands of supporting them are increasing. Incrementally, they have design centers working on products in multiple regions of the world. And even if they procure IP in one place, they may be using it in several. The ability to support them on a global basis is a key driving point. I don’t believe they’ve lost anything from a technical capability [due to consolidation] and they’ve probably gained in their ability to get support and investment on these products on a global basis.”

Further, the number of products that ARM brings out on a 32nm design platform versus at 180nm is approximately five times larger. Those products also are supported under a common EDA framework of all the major tool vendors, and they have been tested so the interoperability issues that historically drove customers to choose multiple vendors have been minimized.

Synopsys is seeing a similar trend for both technical and business reasons. “We’re seeing a huge push from our customer base in this direction,” Koeter says. “Buying IP is complex. There is a long technical process to evaluate a particular piece of IP, negotiating the business terms especially around things like warranty indemnification tends to be very difficult. And if you buy multiple pieces of IP and they don’t work together, you start to get finger pointing.”

For those reasons, as well as purchasing power, customers are trying to consolidate their IP vendors because IP is a volume-based business, wherein the more you buy the better discount you get. “They just have to put one legal contract in place, then can evaluate IP methodologies and apply them to future purchases so they don’t have to go through a detailed benchmark every time. They can buy in bulk and they get favorable payment terms. Typically a lot of our contracts are three year contracts and they are structured as IP VPAs, so customers commit a certain amount of dollars to us and in return get very favorable business terms and get to spread their payments over the duration of that contract,” he says.

Virage’s Buric believes reliability definitely rises with consolidation and is driving more careful choices on IP purchases. “It is becoming epidemic to see people being very conservative about quality because the cost of failure is too high. The cost of redesign has two components. One is tangible, which can be a couple of million or tens of millions of dollars. Or the intangible, like missing a market window, which is basically irrecoverable damage.”

For those reasons, end users are looking very carefully to avoid any damage from usage of unreliable IP components.

Foundries in the IP game

As semiconductor foundries have an interest in manufacturing chips with reliable IP, they have begun providing a limited set of pre-verified physical building blocks to coincide with advanced process development.

ARM’s Lantzsch recognizes that in some cases, a foundry would be viewed as a competitor, but stresses that very few foundries actually provide IP, and understanding why they do it is key.

He notes that historically the business model for Artisan (now part of ARM) was to service smaller companies largely on older technology nodes or more mature technology nodes, and market penetration for ARM/Artisan in those spaces is strong. “With that being the case, we weren’t really involved in early technology development at all,” he admits, but ARM now believes it is critically important as it moves on to the next class of customers, which are tier-one companies. Those larger companies are beginning to face some of the same challenges that fabless ASIC vendors have had in the past, where they don’t want to develop things that don’t add differentiation.

“It’s made us have to accelerate our technology road map significantly. What that means is bringing up the libraries in parallel with the process development. When we weren’t doing that, the foundries needed to do that,” Lantzsch says.

Still, ARM maintains strong relationships with a number of foundries including TSMC and the Common Platform. In fact, ARM and the Common Platform announced last September that ARM will develop and license a comprehensive physical IP design platform meant to help customers achieve optimal power, performance, and area for current and future ARM Cortex processors.

“We’d been working with them well in advance of that announcement on how to get the most out of the litho and creating the most density in the cells, what the tradeoffs are between design rules and standard cells and how does that then impact, in our case, ARM system performance on the CPUs. And that iterative process early on as part of process development, we believe is critically important,” he said of the close collaboration between the companies. The IDMs were used to doing that for years – they did that themselves internally. So for us to be able to address that market, we had to replicate, in many cases, what they were doing. Of the foundries that predominantly offer libraries, a significant reason to do so is largely this issue. They need to do that as part of their process development, and driving things even into the EDA space like routing technologies. It’s that iterative process on the advanced technologies that there’s a need to do that and if it’s not satisfied by a third party partner, then they were forced to do it themselves.

With IP consolidation to continue, closer partnerships and better reliability will be the result, with users ultimately benefitting from the activity.

By Ed Sperling

Uncle Sam wants you—but not on the battlefield.

The diminished pool of qualified engineering and science graduates is having a major impact on the defense market. There simply are too few trained engineers to design complex systems for the military at the rate they’re needed, creating a huge hole in a system that has been humming along for the better part of a century. And with many existing engineers retiring or retired, the need will only grow.

The problem started in the early 1990s with acquisition reform, which began tackling problems of custom-made tools. Stories about hammers and toilet seats costing hundreds of dollars made headlines across the country, and Congress reacted by moving to commercial off-the-shelf (COTS) parts. In the name of efficiency, not to mention the defense cuts of the Clinton administration, the government turned what was once an attractive career option for engineering and science graduates into an extremely unattractive option.

While it has been relatively easy for a company to get on the list of accepted suppliers—they have to meet the triple standards of reliable, safe and secure, with an established production process—the number of engineers who actually work for these companies has been in sharp decline. And so far, they haven’t returned.

“Science, technology and the underlying math and physics has been waning in schools,” said Paul Shebalin, retired U.S. Navy Rear Admiral and currently the director of the Wayne E. Meyer Institute of Systems Engineering at the Naval Postgraduate School in Monterey, Calif. “That’s especially true for those individuals who are eligible for DoD (Department of Defense) clearance.”

Enrollment at engineering schools dropped precipitously in the beginning of the decade, but it appears to be on the rise. In fact, enrollment of full-time foreign graduate students on temporary visas in science and engineering grew 16 percent in 2006, compared with only 4 percent in 2005, according to the National Science Foundation. Those numbers dropped 19 percent after the terrorist attacks on Sept. 11, 2001.

Looked at differently, the number of U.S students in those programs is growing, as well. The percentage of U.S. students in science and engineering increased to 71% of the total students enrolled in 2005, up from 69% in 2003. The good news is that it’s far easier for U.S. citizens to get DoD clearance for sensitive defense projects. But what percentage push further into graduate education and then into complex system-level design remains to be seen.

“The typical curriculum is that in undergraduate you have electrical and mechanical engineering and computer science, and then you try to integrate all of that at the end. In graduate school, it’s a systems approach—systems process, engineering economics and process management,” Shebalin said. “What we need are people who can integrate thermal with electronics, structures, weight and propulsion. In the systems engineering process, you have to come up with a system specification that includes functional and non-functional requirements.”

He noted that the Secretary of the Navy already has issued a mandate to boost the numbers of engineers and scientists, as well as the quality of their training. “We’ve seen the problems of systems engineering done badly,” he said.

By Ed Sperling

In the midst of the longest and deepest downturn since the invention of the transistor, not everyone is doing badly. In fact, there are some bright spots across the electronics industry that seem to defy gravity, so to speak.

In particular, design tools are doing well. When the industry is down, they’re typically down less because, as any successful executive in technology will tell you, the only way out of a recession is to design your way out. If the recession ends and there are no new designs ready for the rebound, that could be a career-limiting move at best. At worst, it can kill a company.

This is reflected in sales of EDA and other design tools. While the industry overall is down, some companies are posting record growth.

Synopsys, for one, saw its Q4 revenues rise by 11.9 percent. It expects to post year-over-year growth for the current quarter, as well, according to published statements. Mentor Graphics, while reporting some slippage in revenues due to delays in contract renewals, said the company is extremely well positioned heading into 2010.

In the virtual prototyping market, Carbon Design Systems posted 87% year-over-year growth for 2008 versus 2007, and 108% revenue growth. While that kind of growth is remarkable even in good times, it’s particularly noteworthy in a downturn that began in December 2007. Rick Lucier, Carbon’s president and CEO, said in a statement that he is confident that growth will continue based upon support from the IP community.

In the high-level synthesis world, Forte Design Systems posted 30% growth in Q4 and finishing off 2008 with a record year in terms of revenue and bookings.

In the embedded world, some areas are at least showing a pulse. Designs are under way in the retail point of sale market, signage and the medical electronics fields and third-party vendors anticipate these segments will be out of the recession relatively early.

Intel’s commitment to invest $7 billion in new fabs in the United States also is likely to stir up some business in areas such as capital equipment, EDA tools and the IP market.

And at least one investment banking firm has raised its opinion of chip stocks. In his blog in Seeking Alpha, Eric Savitz astutely noted that UBS has suddenly turned bullish on chip stocks, upgrading a slew of them. Given the fact that the market has been diving lately, that may seem like a stretch. But with banks lowering interest rates on short- and mid-term CDs, coupled with the likely design activity that will begin to bear fruit later this year, it doesn’t look like such an odd shift.

By Ed Sperling

San Jose, Calif.—Jan. 15, 2008—The EDA Consortium’s annual forecast meeting this year was focused on just how deep and how long the recession will go—to the point where the panelists actually polled the audience on their thoughts.

The overriding opinion among attendees was that the downturn would be long and deep, with a second group believing it would be long but short. Considering the recession already has dragged on for 13 months, and the longest two downturns in the past 40 years were 16 months, it’s hard to imagine it going short. Only the Great Depression was longer. It lasted for 43 months.

For the EDA world, in particular, the downturn will be significant but not debilitating. Wally Rhines, Mentor Graphics’ chairman and CEO, said the EDA industry will likely post a loss of 8 percent in 2009, based upon the impact of the overall economy and the way revenue is being recognized. It will be only the fourth time that EDA has posted negative growth, and the only time it has occurred in two consecutive years. The industry had negative growth in 2000 and 2003, as well.

In the meantime, he noted that semiconductor R&D growth has only been down once since 1980, which was the year 2001. The difference that time was the huge inventory surplus. There is none this time, and while that doesn’t lessen the impact from customer buying it should make for a quicker recovery.

When that recovery will occur in earnest is anyone’s guess, however. Aart de Geus, EDAC’s chairman, as well as chairman and CEO of Synopsys, said the downturn will accelerate all trends that have occurred so far in the industry, including the push to a fabless model and changes in R&D.

“Electronics is among the most protected sector,” de Geus said. “Obama and his team will go high tech. Science is coming back to the White House.”

And even in the down numbers, some sectors will do well. Chris Rowen, founder and CTO of Tensilica, said differentiation still brings a premium, although these days it has to happen within a constrained budget. He noted that bright spots in the mix were mixed signal and analog signal processing. Those areas continue to see double-digit growth even as the rest of the industry shows problems.

But as the industry does come back to life, it may be a different world that it returns to. Rajeev Madhavan, chairman and CEO of Magma, said the PC market may not be a major source of chip revenue in the future because of a shift there from PCs to handheld devices. At the same time, he said the move to electric vehicles and Green everything will be a huge opportunity for EDA.

“There will be a change in customers and a change in chips,” Madhavan said, noting that not all companies will survive the downturn. “The challenge in the short term is that companies will have to be profitable with a limited number of customers.”

Independent investor Jim Hogan talks about where the real value is and what companies need to do to survive in a changing market.

By John Blyler

How will the acquisition of ProDesign’s ChipIT business unit expand Synopsys market in the system-level rapid prototyping and possibly emulation space?

The short answer is that it’s probably too early to tell. But with the accelerating pace of EDA company consolidations, it’s important to quickly assess the pros and cons of each new acquisition.

Earlier this month, EDA and IP giant Synopsys said it had signed a definitive agreement to acquire the CHIPit business unit of ProDesign Electronic GmbH. ChipIT is a family of hardware-assisted verification and related software tools. This acquisition comes less than a year after Synopsys acquired Synplicity, allowing Synopsys to fully enter the FPGA implementation and debug market.

What does it mean?

With the acquisition of ChipIT and Synplicity, Synopsys now becomes a significant player in the fast-growing hardware-assisted verification market. The company brings additional strengths to this market with its existing verification technology, including IP and RTL simulation tools. At the system level, Synopsys also has a virtual prototyping platform for software development.

Hardware-assisted verification, you ask? Weren’t we talking about the rapid prototyping and perhaps emulation technology? Where does hardware-assisted verification fit into this mix? Although both FPGA-based rapid prototyping and emulation/acceleration are part of the same market segment – namely hardware-assisted verification – these two platforms are targeted at different markets.

“FPGA prototyping is being used mainly for IP verification and software development, where it runs small designs with great performance,” notes Ran Avinun, Group Director of Verification Marketing for Cadence. Conversely, emulation is being used for system and hardware-software verification of larger designs.

So is ChipIT a prototyping or emulation tool? Or perhaps both? Some have suggested that the ChipIT acquisition may be a way for Synopsys to enter the emulation space, through FPGA-based prototyping. Lauro Rizzatti, general manager of Emulation and Verification Engineering (EVE) USA, sees ChipIT as an FPGA-based rapid prototyping tool. “ChipIT is not really in the emulation business. It would take years for them to move from prototyping to emulation. We don’t think that is Synopsys’s intent, either,” explains Lauro.

Further, neither Cadence nor Mentor see FPGA-based (or hardware) prototypes as a direct threat or replacement for emulation because of performance and capacity differences. That is why each technology targets a different market, as noted earlier.

If ChipIT is really a prototyping hardware tool, then what unique features does it bring to Synopsys? The answer is transaction-based verification. ChipIT is an ASIC prototyping tool that uses the Standard Co-Emulation Modeling Interfaced – abbreviated SCE-MI - to perform high-speed, transaction level verification between different software simulation and hardware emulation systems. SCE-MI is the standard that allows the worlds of simulation, emulation and rapid-prototyping to interface.

“You can use C-Level models on the software side that connect to a device-under-test running on a hardware emulator,” explains Juergen Jaeger, Director of Product Marketing for the Synplicity Business Group. For example, C-level models run transaction-level data, such as an Ethernet package, whereas cycle-accurate hardware emulations run the actual data bits within the Ethernet package. Being able to run both levels of models enable system-level co-verification of a design.

Questions Remain

Synopsys’ acquisition of ChipIT would seem to strengthen its position in the system-level development market. Yet many questions remain. First and foremost is how Synopsys will integrate it most recent acquisitions of Synplicity and ProDesign’s ChipIT. For example, which of the two hardware platforms – Synplicity’s Hardi or ProDesign’s ChipIT – will it support, merge or remove? A similar question might be asked on the software side – Synplicity’s Confirma or ProDesign’s ChipIT?

Will ChipIT, a transaction-level tool, be used in conjunction with Synopsys virtual prototyping platform? Will this mean that Synopsys can now add behavioral synthesis and hardware-software partitioning to its existing RTL-based products. Behavioral ynthesis is a prerequisite for many system-level architecture activities.

When asked these questions, Juergen was careful to point out that Synopsys’ acquisition of ProDesign’s ChipIT was done to complement the earlier Synplicity purchase, not to overlap it. He was also quick to add that more news would be forthcoming, once the actual acquisition of ChipIT was complete.

Though too earlier to tell, this acquisition looks to have long-term implications for the chip design market.