By Ed Sperling
Docea Power rolled out the next version of its power and thermal analysis software, including an event scheduler that complements the existing timed flow chart creation and vcd import capabilities, as well as support for thermal models. Given the fact that power is now one of the top factors to consider at the architectural level, you can expect to see more of these kinds of tools.

Synopsys delivered solid financial results for its fiscal Q2. Revenue was $432.6 million compared with $393.7 million in the same period in 2011. Net income was $$21 million vs. $81.1 million last year. But factoring in the $30.2 million costs for the Magma acquisition this quarter, as well as a a one-time gain from an IRS tax settlement of $32.8 million last year—its net income was up about 6%.

Cadence won a deal with Nufront, which will use Cadence’s DDR memory interface IP in its mobile applications processor.

A new startup, SiCAD, came out of stealth mode. The company will focus on complete cloud-based design environments involving multiple EDA vendors’ tools.

With more than a year of production use, the Accellera Systems Initiative UVM is now clearly the methodology of choice for verification. The rush to adopt UVM has both matured the BCL quickly, producing UVM 1.1 and 1.1a bug-fix versions, as well as created a wealth of institutional know-how. Of course, the challenge with know-how is that it tends to be distributed among all the members of the community with little pearls appearing in various forums and contributions. While many sessions introduce the UVM to new users or specific aspects of it for advanced users, the critical tips and best practices are often diffused throughout that material if they are presented at all. So for all of the verification engineers that have been working this year and thought “I wonder if this is the best approach” or “should I use this UVM feature”, this presentation cuts right to the answer with specific pointers and code examples, gathered from live projects worldwide, that you can use immediately for more effective verification.

To view this white paper, click here.

By Ann Steffora Mutschler
It wasn’t that long ago that the promise of system-level models was an easy implementation path and the ability to then reuse the models in a different design, for a different target application. But how reusable are those models in reality? The answer depends on whom you ask.

First, it is important to define what a system-level model is, noted Frank Schirrmeister, group director of product marketing for system development in the system and software realization group at Cadence. “If a system-level model is defined as a TLM model or something even higher above then by virtue of its abstraction, it’s actually re-usable by definition so to speak. I always compare them to the gate-to-RTL jump. Is the RTL model re-usable? Absolutely, because we have automation underneath to remap it to several technologies. Is the TLM model/the system level model for, let’s say, your high-level synthesis input re-usable? Absolutely, it’s reusable for that particular implementation it does. And then, you have the automation around it to actually get the implementation done.”

Further, are these models reusable in general terms the higher up in levels of abstraction? From his perspective they are—they are reusable across different applications and different designs. Otherwise it wouldn’t be commercially feasible for system-level houses or EDA vendors to provide them, he argued.

However, Schirrmeister pointed out, “You need to be precise about what you re-use them for. If you go up from the RTL to the TLM level first, then these models are re-usable for sure when it comes to processor models because they are re-usable for every design that uses the processor model.”

But not so fast, said Drew Wingard, co-founder and chief technology officer at Sonics. “The place where the system models have the bigger challenge is in trying to imagine when I integrate these things together, how is it going to perform? And there we have some challenges.”

The challenges boil down to the fact that for most of these applications, the cost mandate requires that the cheapest DRAM system is used for the SoC. The SoC maker may want to sell its SoC for $10 while the DRAM cost was approximately $8, but if more expensive DRAM is needed it could bump the SoC price to $12. At that point the end user may say they are still willing to buy the SoC but are only willing to pay $7 for it.

“The real challenge of modeling the performance of DRAM with enough accuracy to predict is not the bailiwick of most of the system level modeling initiatives. The virtual platform models don’t give you any real concept of performance and certainly nothing near detailed enough,” he explained.

These cost pressures combined with design complexity is changing the perspective on how models should be used.

“The notion of having a seamless path from having a high-level model and synthesizing it to maybe VHDL/Verilog model and onto hardware—I don’t see it happening. It might still be an industry dream of a couple of people and it would help a lot. It would help proliferate virtual prototyping a lot and it would help proliferate platform architecture design a lot, but it just doesn’t seem feasible to really have that seamless flow,” asserted Tom De Schutter, senior product marketing manager for system-level solutions at Synopsys.

Instead of an implementation point of view, he believes the view on re-use of models currently is defined more on a use-case point of view.

Besides developing the use case for creating testbenches from models, De Schutter explained that work is being done on how can models be re-used across different types of use cases for different types of software developers, be it OS porting or middleware development onto more verification use cases of IP blocks or looking at it from a software performance and energy point of view.

“Because the software is becoming so important, maybe it’s not that important that the model has an implementation path as long it provides value across the lifecycle of the different stages of software and the different types of software—the value of the model establishes itself, as well,” he said.

Toward this end of making the models re-usable across different use case scenarios, it comes down to defining the different things that a model has to do to be useful for those use cases.

“In a lot of cases, the way we as an industry—customers and vendors—looked at it, there was always a notion that you need a lot of accuracy, you need a lot of timing for models to be useful and, of course, the more complex systems become the more that breaks,” De Schutter continued. This becomes clear particularly with the latest approaches to processor design such as ARM’s big.LITTLE approach. “If you look into those systems, just that specific subsystem has up to eight processors, and that’s not taking into account the rest of the system where the baseband, Bluetooth, WiFi, the power management system—everything has cores. So it’s becoming very hard to have very accurate models, and accuracy then defined as timing accuracy, and simulate them in a reasonable simulation speed.”

De Schutter said the current thinking is that the software itself doesn’t need timing accuracy or cycle accuracy to be developed or even optimized. “Again, looking at it from a different point of view rather than from a hardware point of view and an architecture design or an implementation point of view, we are starting to more and more look at it from a software point of view. How can this software help optimize the system? ARM big.LITTLE is actually a perfect example of this,” he added.

In closing, Wingard offered some harsh criticism for some approaches promoted by some vendors today. He believes the models some companies are providing to their customers are not accurate enough to do architectural sign-off exercises.

“While they might help the designer try to get to an intermediate design point, they’re still forcing the development team to go to an emulator to prove whether the architecture is viable or not. They have this additional problem that even if it works on the emulator, it doesn’t mean it will work on the layout of the chip…so that when they get into layout the floorplan changes associated with dealing with the actual layout constraints end up rippling back to their architecture and creating additional substantial performance problems that need to be re-architected. That generates an additional round of problems that basically force the customers to tape out sub-optimal solutions,” he concluded.

By Ann Steffora Mutschler
Since the dawn of EDA, the industry has largely operated under a traditional software distribution model whereby the customer would run the software it licensed on its own hardware equipment. With the sophistication of advanced IT management techniques as well as education surrounding “The Cloud,” it may be safe to predict that engineers in the not-to-distant future will be designing and verifying SoCs entirely in the cloud.

Right now, however, it’s a different story.

“As an industry, it’s pretty nascent for EDA applications,” observed Dave Desharnais, senior group director for product management in the silicon realization group at Cadence. “We ended up getting permission to use our tools in the cloud with constraints because there really was no formal way to do that in a third party cloud context. It’s really been large-scale companies that have been coming to us for about the last three years, on the tune of probably 10 to 12 a year, asking us because they are Cadence customers, ‘How do we use your tools in the cloud? We want to use your tools in the cloud.’

A frontrunner in this model, Cadence has offered its Hosted Design Solutions since 2007. It is a turnkey, private cloud offering born out of its design services. “It’s not a driver for our business but it’s certainly an option for a certain class of customers—mostly small and medium sized,” he said. With about 50 customers today, it has seen linear growth since the program began.

Desharnais is quick to point out, “This is really our entrance into the software as a service (SaaS) market because the customer owns the data but we want to provide that pathway in, all the compute resources, it’s turnkey and it’s beyond emulation, it’s everything: custom analog to digital ICs, all the physical and logic verification, emulation.”

Datacenter at Cadence Design Systems (Source: Cadence)

“It’s really no different from a business model in traditional EDA—you buy a license for a certain time. In this case you’d buy a set of licenses for a certain time with some bursting capabilities. That’s the SaaS model,” he said.

An even earlier player in the cloud arena is Sonics. Drew Wingard, co-founder and chief technology officer, said he feels like a grizzled veteran of this topic. He explained that way back in 2001, Sonics introduced a vehicle called SoCworks. Today it would be referred to as SoC- and IP-core-based design in the cloud.

“A challenge we were trying to address in those days, if you look at the basic business transaction model behind selecting IP cores to go onto an SoC, is that one of the big challenges is this horribly long dance that happens at the beginning before the customer can actually do the evaluation,” said Wingard. “It ends up being very messy, and in many cases it’s like six months to get through this process. The idea we had at the time was the reason for a lot of this protectiveness is around worries about the theft of the IP or worries about the pollution of the engineering, and that in the chip field we don’t worry about this as much because the chip that we distribute is pretty obscured. It’s buried inside a package, and you can’t really figure out what’s going on inside. The distributor can ship you a chip for evaluation purposes without all of this stuff. What if we could get to that same level of abstraction around IP cores?”

Sonics built a set of servers, in what would now be called the cloud, that ran the development environment that was part of its solutions. It still is, and it “allowed people to mix and match IP cores from who were then some of the major providers of IP cores—guys like MIPS and Tensilica, the inSilicon part of Synopsys—and actually plug and play them together around our interconnect fabrics, run some basic simulations so they could try before they had to go through all that legal stuff. We were way ahead of the curve on this clearly,” he added.

Mentor Graphics too is not new to the private cloud. Michael Buehler-Garcia, senior director of marketing for Calibre design solutions explained that as part of Calibre, there is a multi-thousand CPU farm in the floor of the building where the Calibre team is located, which is run as a private cloud to its different development teams around the world. “So are we doing cloud? Well, yes, and anybody who runs OPC accesses an SoC cloud because the size of designs requires multiple CPUs to run it.”

Datacenter at Mentor Graphics (Source: Mentor)

Today, the company expands its cloud play with its announcement (http://www.mentor.com/company/news/) of a cloud-based DFM Analysis Service based on the Calibre platform for TSMC 28nm and 40nm foundry customers, which analyzes the customer’s design database to meet the requirements for TSMC’s lithography process checking (LPC) flow. It delivers a results database containing hotspot locations and fixing hints that can be used by routers to perform corrections. Buehler-Garcia expects it to be attractive option for customers who tape out only a few advanced- node devices per year.

In addition, Synopsys has been offering verification-on-demand in the cloud for a few years.

IaaS Before SaaS
Before engineering teams embrace SaaS, Cadence’s Desharnais believes the infrastructure as a service (IaaS) model will take off as an interim step.

Interestingly, he said, customers are requesting permission to run Cadence software in the cloud…even if they don’t know what to do with it yet.

“What is shocking to me is very large sophisticated mobile telecom-type companies [like those] in the San Diego area—those guys aren’t doing it. Those guys are leading, bleeding edge, and they are the guys you would expect would have it. They want permission but they haven’t pulled the trigger on it yet because they are still trying to figure it out and how they are going to use it,” Desharnais continued.

“What I’m seeing the most, if you look at the semiconductor industry at large, it’s not so much a SaaS model, it’s more of an IaaS model. There’s a huge reluctance to put anything like an RTL on the Web or any sort of physical design that can be effectively pirated or moved so the security pieces scare them. As an EDA vendor, we’re actually not in a position to solve that. There are more systemic kind of things that are in the way. But we see companies taking a baby step in this direction, and this is where they are getting pressure from their CFO or their CIO or their CEO to start moving to more of an operational expense versus a capital expense model. And they say, ‘If we’re doing it for other things in our company (financials, HR) why not do it with EDA tools?’” he suggested.

In the long run, what probably makes the most sense is for EDA tools to be hosted by third party cloud providers such as Osmosix, Plunify and Xuropa, as opposed to private clouds hosted by the EDA vendors since customers won’t want a locked solution.

A newcomer to this scene is SiCAD, which comes out of stealth mode today. What’s different about this company is that it makes no tools of its own, but pulls together a cloud-based multivendor solution for a number of vendors’ products, including all of the Big 3 EDA companies and many point tools. As CEO Jai Iyer tells it, the key was to identify the pain points where utilization is extremely high but utilization over a year is low.

“The problem is that peak use for some of these tools last two to three months, and the rest of the time they’re sitting around idle,” said Iyer. “When you look at signoff tools for static timing analysis, extraction and DFM, they’ve all got low utilization and they’re expensive.”

It remains to be seen whether a multivendor complete solution will fare any better than previous attempts by established companies. At the end of the day, many will still argue that the business model is not working. But there are still those who believe that—at least someday—it will. The only question is when.

Customer IT Deployment Types (Source: Oracle)

By Ed Sperling and John Blyler
Virtualization and coherency, two concepts that can trace their origins back several decades, are suddenly gaining attention these days—but for entirely different reasons and uses.

A good way to think about virtualization is as an opportunistic use of available resources. Rather than waiting in a queue for a single processor core in a multicore SoC, for example, virtualization allows a compute task to take advantage of whatever processor is available if another is in use.

The concept is hardly a new one. Virtualization was invented by IBM in the late 1960s as a way of running batch processing while also still doing other work. But virtualization also creates a challenge for keeping caches in sync, which is why the concept of cache coherency was created. And as more cores are added into SoCs, rather than more processors within a single machine or on multiple machines, cache coherency has moved from mainframe to PC to processor and now across multiple processor cores.

What’s changing now is that these concepts are spreading well beyond just the processors. Virtualization is being applied to memory, storage, I/O and graphics processing units (GPU)s. But to make all of that work efficiently coherency will have to grow well beyond just the cache, and that may prove to be a very difficult problem, particularly in a multivendor ecosystem.

The starting point
Much of this shift has come into focus inside large data centers over the past decade as a way of reducing costs. In the 1990s, the availability of inexpensive blade servers and ever-increasing density made it possible to begin replacing expensive mainframes and minicomputers with off-the-shelf commodity machines. You could stuff them into a single cabinet and blast in chilled air to cool them sufficiently. Two things happened to change this equation. One is that the cost of electricity suddenly went up, because these cabinets were running hotter than ever before as density and current leakage increased. The second was that data centers had bought so many servers over a period of 15 years that just the cost of keeping them running was beginning to show up as seven-figure annual expenses for many large data centers.

Virtualization proved an effective way of reducing that cost because it allowed data centers to increase server utilization from an average of 5% to 15% utilization all the way up to 85% or more. That meant fewer servers overall, less electricity, less heat to remove, and far more available real estate. But with that problem now under control—at least for the moment—data center managers have shifted their attention to the exponential rise in the amount of data being stored. In the 1990s, most of the data was simply text or code. It is now a combination of text, video, data and voice, raising the same kinds of fiscal red flags about powering and cooling storage as servers prior to virtualization.

“What we’re seeing now is a move toward virtualized storage,” said Bob Pierce, flash business development group director at Cadence. “The next step is to merge storage and memory, which is why we’re seeing such strong interest in PCI Express. It’s a great transport vehicle. We’re also going to see back-end storage mixing with front-end storage data. What’s in between will be cache in the form of virtualized memory.”

This more fluid boundary between storage and cache has ramifications at all levels of design. It can affect everything from a processor to multiple processor cores on a single SoC, on multiple chips in a stacked die, and on multiple systems in a grid or mesh network.

“What’s happening is that you’re moving the back end closer to the processor,” said Pierce. “It changes the way big data and databases will be addressed in the future. If you have four CPUs, you can take them and, using PCI Express, prioritize them into a given drive sector and share them. That’s where all the VC startup money is these days. It’s the ability to configure servers for the function necessary at any given time. But you also have to virtualize storage and memory, and it has to be done dynamically.”

PCI Express has the dual advantage of adding a single protocol to keep all of this data coherent. While it’s useful to store and retrieve data quickly, it all has to be updated to reflect any changes that were made in any part of the system.

Adding other resources
Mixing storage and cache is fairly obvious, though. Less obvious is the mixing of processing between CPUs and GPUs.

“In the past, GPUs were directly assigned to a virtual machine (VM),” said Sumit Gupta, senior director of Tesla GPU Computing at Nvidia. “Every VM would get a full GPU, which meant that each server was limited by the number of GPUs it could hold.”

Nvidia’s new Kepler GPU architecture uses more cores—192 vs. 32—compared with its predecessors, and a significantly lower frequency of .175GHz compared with the old 1.35GHz. The result is faster processing with less power.

“We invented several technologies in order to virtualize the CPU, including an improved Memory Management Unit in the GPU,” he noted. “This is key because most of the data acted upon by the GPU comes from memory.”

But memory is being virtualized, as well, making this whole scheme even more complicated. Startup Memoir Systems, which touts its solution as algorithmic memory, is an intelligent virtualization scheme for almost any available memory in a system. And there are moves afoot to do the same for the multiple I/O feeds to improve the speed of downloads and uploads from a system.

Making it all work together
While virtualization all makes sense from a performance standpoint, complex systems aren’t just about performance. Coherency is a critical piece, and it’s an extremely difficult one.

“The reality is that I/O coherency has been around for a long time in the x86 world,” said Laurent Moll, CTO at Arteris (and formerly a systems architect at both Nvidia and Broadcom). “The next frontier is when you start adding in other devices, and there’s a big disruption when you’re adding full coherency between the CPU and other things. It’s easiest when you have a small team designing the cache and all the protocols. When you start plugging multiple things together it gets a lot harder. You need to be a lot clearer about the specification, the verification and the tests that need to be run.”

He said there are two key challenges in this scheme. One is simply getting it right, which is difficult for multiple companies using different teams and with different cultures. “It’s very easy to have corner cases that the guys who wrote the spec didn’t think about,” he said. The second challenge is that there is no known path to do this. Quite simply, it has never been done before.”

Conclusion
The upside of getting this right is a huge boost in performance. Being able to utilize more resources at any time can improve speed on almost every part of a chip or system, and virtualization plus coherency is a big win for the user.

The downside is that, assuming this can be done in the first place, it also could have an impact on power. The whole goal of most advanced SoC designs is to keep the majority of silicon dark except when it’s needed, and even then to run at maximum performance for a very short time to get everything done quickly. Having more resources to manage on an ad hoc basis solves the use model issue for performance, but it can create havoc on power management schemes.

In addition, it may require new software to even work in the first place. Cadence’s Pierce said some of this won’t even make sense on platforms such as Android until the multithreaded OS release called Ice Cream Sandwich becomes more prevalent.

By Ann Steffora Mutschler
Driven by high-speed interfaces, the demand for TSVs and the complexities that new process nodes bring, older packaging technologies like wirebonding can’t keep up.

The latest and greatest flip chip technologies offer much more flexibility, but at a cost. As such, the package plays a larger role than ever in determining system specifications because, depending on the packaging technology used, certain system parameters are either limited or not. For these reasons packaging is being considered up front in the design process—even at the very earliest planning stages. Moreover, the cost of packaging comprises a non-trivial portion of the total system cost. Throw 2.5D and 3D ICs into the mix and things get really interesting.

These issues are breaking down the brick walls between the IC designer and the packaging designer, observed Brad Griffin, product marketing director for Cadence’s Allegro product line. “I think we have hit a point where if you don’t at least consider some of the aspects simultaneously you’re going to end up with a system that either doesn’t perform like you would like it to or has additional cost than you would like it to have.”

Shafy Eltoukhy, vice president of manufacturing operations at Open-Silicon, agrees. “Essentially when we talk to the customer initially we try to understand from them what their thermal requirements are, like power, the footprint of the package, the thickness of the package and the cost. Also, if it’s a consumer part it will be different than if it’s a networking part. The cost has a big impact on the selling price. There are a lot of factors that come in at the very beginning, that being the power dissipation, signal integrity, form factor of the package and so on.”

There’s a complicated matrix to designing a package. “In some cases, at the very beginning, you don’t know exactly what the die size is going to be because customers keep adding functions and the die size keeps changing in the early stage. Having all the requirements from the mechanical to power to this and that, as well as the layout or the floorplan of the die, is also changing up front. The package has to be part of the very early stage of the design,” he said.

The company ties the package to the floor planning and the requirement as far as the speed and other considerations. Package design engineers get on board very early in the process—even before designing the die itself—to look at it from the floor planning point of view. That includes where to put high-speed interfaces, how fast these are going to be, packaging technology, i.e. flip chip or wirebond, power expectations, and so on. “It’s very complicated and people have started putting a very good interface between the packaging and floor planning engineers,” Eltoukhy added.

Broadcom recently detailed its experience making early tradeoffs during Cadence’s CDN Live event in March. The presentation can be viewed here (registration required).

In this case, using Cadence technology under development, Broadcom enabled its PCB designer to look at what the package footprint should be to best match the components on the board. From there it drives up from the package footprint to the bump matrix for the chip. They were able to determine the ideal bump matrix for the chip to be able to match the package footprint. Then from the bump matrix that drove the I/O pad ring to get the I/Os and chips placed properly.

Then, when it comes to 2.5D design, packaging issues are actually more complex than what they will be with true 3D ICs, according to John Park, methodology architect for IC packaging and pathfinding technologies in the Systems Design Division of Mentor Graphics. “I believe—and many of my customers believe—it is more complex because you have this intermediate substrate in which the die connect through these small microbumps, and there’s this die-to-die connectivity that happens on some unknown number.”

Engineering teams really want to save costs, or at least make the tradeoff of cost and thermal, etc., Park added. “They want some global routing technology that allows them to say, ‘What if, on the interposer, I limit it to three metal layers? Does that mean I need to add two more layers to my package substrate or does it mean that I have to add eight more layers to my package substrate?’ In that case, maybe they say, ‘I’m going to add one more metal layer to my silicon interposer so that I can reduce the layer count of the package.’ Now the costing gets very complex because you have this new intermediate routing structure that sits in between the traditional die to package connectivity that greatly impacts cost, routability, signal quality—all these types of things.”

Although some of these issues won’t be a problem with 3D, don’t expect a mass exodus from 2.5D when 3D becomes mainstream because it may be more expensive, noted Cadence’s Griffin. “You’re going to have to get to a certain quantity before you’re going to realize the value in going to 3D IC, so there’s going to be still a fair amount of chips in the lower to mid quantities for which they want to realize the performance gains of going to a silicon substrate to connect things together but they can’t necessarily go to the expensive TSMC to be able to connect all these things together properly. [Systems companies] will rely on less-expensive silicon interposer technology; it will have a little less performance but cost-wise, it will just be more efficient for them. I think you’re going to see both for quite some time, but i think you’re going to see the very-high-quantity things move to 3D IC as much as possible.”

By Ed Sperling
Synopsys’ Yaron Ilani talks about DVE and UVM while commuting to work in a video. It’s good info, but can you count the number of times he takes his eyes off the road to look at the camera? We lost count at 50, although admittedly he was stopped for some of those and this wasn’t the Autobahn. Still, is this legal in Israel?

Mentor’s Nazita Saye digs into the mechanical challenges at Bronswerk Heat Transfer, creator of the incredibly efficient “Whizz-Wheel” fan blade. If you want to see what a Whizz-Wheel looks like, check out the photo. This kind of design is long overdue, and it’s an interesting intersection of mechanical engineering and EDA.

Cadence’s Richard Goering interviews one of his colleagues, Ken Potts, about the GSA’s 3D IC working group. For an ecosystem to build technology this complex, we’re going to need lots of standards groups like this one.

DeepChip’s John Cooley raises questions about venture capitalist Jim Hogan’s SPICE rankings. Considering there isn’t much discussion about any of this stuff, and no official stats, it’s rather difficult to figure out who’s right.

Semico’s Rich Wawrzyniak examines Synopsys’ move into IP subsystems and why this trend is so important. Conclusion: Expect to see lots more of this kind of pre-integration.

No one enjoys home entertainment systems like engineers. But the truth is, most engineers don’t spend a lot of time playing games or watching movies. They do spend time deconstructing and improving the systems, though. Synopsys’ Navraj Nandra is in good company on this one.

Mentor’s Colin Walls recounts the activities at Nvidia’s recent GPU conference. Of particularly note is the programming for task and data parallelism, which may be easier with a GPU than a CPU. Nonetheless, it’s been a tough nut to crack for four decades.

Cadence’s Axel Scherer is stuck on the Saturday Night Live cowbell skit and has somehow tied it to UVMe. Call that loosely timed—or maybe just a loose thread.

Speaking of UVM, JL Gray is back with some tips on UVM drivers and monitors. Monitors are your friends. Use them wisely.

Synopsys’ Helene Thibieroz interviews one of her colleagues, Frank Lee, about FinFETs. Lee clearly has a very good grasp of this technology and what it means to SoC design.

Cadence’s Yuri Tsoglin offers some tips on writing macros in e. If you’re using the e language, this is the place to go.

By Ed Sperling
Cadence added in-circuit acceleration for the Incisive verification and Palladium emulation portions of its System Development Suite. This will reduce the time it takes to run tests on complex SoCs—for both hardware and software—allowing more time to make sure the chip actually works. Cadence also extended its Verification IP catalog for acceleration and emulation. The company also introduced an NVM Express subsystem with pre-integrated and tested IP.

Mentor Graphics won two deals. The first was from U.K.-based Professional Circuit Design, which standardized on Mentor’s PCB design through manufacturing technologies and consulting services.  The second involved Vestel Electronics, a set-top box manufacturer in Europe, which is using Mentor’s Inflexion user interface technology.

Synopsys won a deal with AMD, which will use Synopsys’ Discovery VIP involving everything from USB 3.0, ARM’s AXI, SATA 3.0, PCI Express 3 and Synopsys’ Protocol Analyzer. What makes this especially interesting is AMD’s play in the enterprise space.

MIPS rolled out a new generation of processor cores called Aptiv, with an emphasis on performance and energy efficiency. The cores are targeted at high-end mobile devices and smart home entertainment, squaring off against ARM’s big.LITTLE with what it claims is a much simpler power management scheme.

By Ed Sperling
Cavium’s Brian Hunter, writing for Synopsys’ Verification Martial Arts, resorts to a rather creative, if unusual, way of describing namespaces—a video of a chicken processing facility. This is the very free-range explanation.

Cadence’s Frank Schirrmeister offers a crash course on in-circuit acceleration. Get familiar with this concept because more and more will happen in-circuit at future process nodes.

Mentor’s Travis Mikjaniec questions why California law requires smokers to stand at least 25 feet away from doors and windows. How exactly did they arrive at that number? And which way was the wind blowing at the time?

IHS iSuppli’s Robert Braverman crosses concepts—value chains and supply chains—and explains why they’re so intertwined.

Synopsys’ Navraj Nandra expounds on how to test embedded IP—a serious problem when you’re using multiple IPs with different test access strategies, interfaces and descriptions.

Cadence’s Peter Heller looks into the role of verification IP in SoC verification and why it’s becoming so critical—not to mention why IP vendors are finally able to get paid for this stuff.

Mentor’s Nazita Saye has created a top-10 list of things she learned from engineers. You’ll like No. 4: Engineers are nice people. Funny, they never say that about writers.

DeepChip’s John Cooley goes searching for Samsung in the foundry rankings and finds them…well…all over the map. So much for consistency in math.

Synopsys’ Eric Huang questions the future of Thunderbolt vs. USB 3.0—while wearing a safari hat. That may not seem weird, unless you consider he was indoors.

And in case you missed the most recent Low-Power Engineering newsletter, here are some blogs worth noting:

—Synopsys’ Cary Chin tests the power efficiency of 4G and 3G phones and discovers, rather unexpectedly, the hidden cost of streaming data.

—Mentor Graphics’ Barry Pangrle digs under the covers of Intel’s new Tri-Gate processors and finds the real story is all about energy efficiency and reduced area.

—Cadence’s Luke Lang examines why there are different commands in CPF and UPF and how to navigate the macro models.

—Mimasic’s Bhanu Kapoor concludes that using all the features built into hardware will require some advances in software.

—Apache Design’s Aveek Sarkar looks at what’s needed to meet power, performance and price goals for stacked die and sub-20nm designs.

—Tensilica’s Chris Rowen cooks up the perfect SoC recipe with some advanced culinary techniques.

—Atrenta’s Kiran Vital charts the gap between a standard format for describing memory behavior and reducing dynamic power.

—And Docea Power’s Ghislain Kaiser points to a key problem in solving thermal problems. Blame it on a lack of training.

By Ed Sperling
A subtle but important shift is under way inside of EDA. While vendors are still focused on solving some thorny issues at the front end of Moore’s Law, much of the R&D effort lately has been targeted toward better and earlier integration of new or enhanced tools and toward combining IP blocks into subsystems.

To some extent this is simply good housekeeping—roughly EDA’s equivalent of making software backward compatible. Ensuring that that tools work with each other in a flow that now has to be concerned with hardware, software, power, electromigration, standards—and all the while making this work across a globally disaggregated supply chain—is an incredibly complex management challenge. But there is also at least an early indication, and one that apparently warrants big investments on the part of EDA vendors, hat at 28nm and beyond many of their customers’ in-house tools are running out of steam. Even better for EDA, there is far less money being appropriated to develop new internal tools.

This explains the rising clamor by customers for more standards. Chipmakers certainly don’t want to pay top dollar for EDA tools, and standards make it easier to chop costs—or at least to negotiate a deal. That’s partly what’s behind the increasing amount of noise about existing standards such as the dueling power formats, CPF and UPF/1801. It also explains why there is more collaboration under way between chipmakers and EDA vendors to develop complex solutions, because while chipmakers may experience a limited number of problems, EDA vendors deal with a much greater universe of the same or related issues and draw from a larger pool of chipmakers to offer advice.

All of the big EDA vendors recognize these changes, and their recent product releases clearly reflect it. Witness Cadence’s announcement today of tighter integration between its System Development Suite, with in-circuit acceleration, and its VIP catalog, which now has hooks for both acceleration and emulation. What that means, in a nutshell, is that simulation and emulation teams now can share a verification environment, and the VIP catalog is now compatible with the Accellera Co-Emulation and Modeling Interface (SCE-MI) standard.

“The goal is to push use models from NRE to automation,” said Michal Siwinski, group director for product marketing for Cadence’s System and Software Realization Group. “There are two elements to this. One is in-circuit acceleration to the System Development Suite. The second is a VIP catalog that has been expanded for acceleration and emulation.”

Both Mentor Graphics and Synopsys have been taking similar steps for their respective environments. Mentor, for instance, has been active in bridging a variety of its embedded software tools into a standard flow, and in making emulation far more attractive for software developers by adding a desktop virtualization layer. The company also has been working heavily on making it easier for chipmakers to develop and incorporate embedded software into their designs.

Synopsys has been integrating a number of pieces in other areas, most recently in the 2.5D/3D IC world where it has begun integrating test, IP, parasitic extraction, simulation, DFM and thermo-mechanical stress analysis into the same flow. It also has been working hard to integrate hardware and software.

“The interaction of components is much more important,” said Alan Gibbons, principal engineer at Synopsys. “A lot of this is not being modeled today, and if it is it’s happening on a spreadsheet. We need more intelligent algorithms to make this work.”

Along the same lines, but in different market, Cadence has launched an NVM Express memory subsystem for enterprise computing environments. “This will dramatically reduce the time it takes to integrate and optimize,” said Neil Hand, group production marketing director for Cadence’s SoC Realization Group. “NVMe was built on PCI Express. This is a natural move to a subsystem and it leverages a lot of expertise in storage and high-performance interfaces.”

This follows on the heels of similar moves by Synopsys in the audio subsystem arena (as well as its NVM Express VIP), and by companies such as Tensilica in the audio and video subsystem world.

Simon Butler, CEO of Methodics, said the move from IP to subsystems eliminates a lot of the “grunt work” by bundling in firmware and development tools.

“There’s a lot of history behind using the appropriate infrastructure with functional blocks,” said Butler. “The challenge is in trying to accommodate both of those. Generally speaking, the larger the block the more you need to remove the complexity, and the way you do that is to give it to the IP vendors and let them do it.”

Butler said that characterizing subsystems rather than just IP blocks is a big step forward. “The fact that programming and interacting can be done at a higher level means the use model is easier. How perfectly it behaves electrically is driven by the application. But if you see enough traffic going through a subsystem, you bring more to the table and are able to solve more problems. So basically your integration work as a customer is going down because the vendor is supplying the abstraction layer.”

With all of the big three EDA vendors on board, this focus on integration will likely establish the theme for the upcoming Design Automation Conference in San Francisco early next month. The big questions now are what else will be integrated, and by whom.