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More space for satellites and a roadmap for data protection

Monday, February 12th, 2018

Blog Review – Monday, February 12, 2018
This week’s selection includes 100G Ethernet for data centers; Satellites will vie for space; A roadmap for data protection, and more from the blogsphere

The rise of data centers and increase in cloud-based computing has prompted Lance Looper, Silicon Labs, to examine how wireless networks are changing to meet the demands for performance and low latency and implementing 100G Ethernet.

https://www.silabs.com/community/blog.entry.html/2018/02/05/ethernet_s_role_inh-pTeJ

Marveling at how connectivity has ‘shrunk’ the world, Paolo Colombo, ANSYS, looks skywards to consider the growth of connected devices. He looks at the role of space satellites and how small satellites will have their day for critical applications and introduces ‘pseudo sats’ which are vying for space in space.

An article about medical device design and manufacturing challenges has prompted Roger Mazzella, QT, to address each and provide a response to reassure developers. Naturally, QT’s products play a role in allaying many fears, but it is an interesting insight into the medical design arena.

An interesting case study is recorded by Hellen Norman, Arm, featuring Scratchy the robot. She asks German embedded systems developer, Sebastian Förster how he used a Cortex-M4, some motors, Lego bricks and cable ties to create a four-legged robot, programmed to walk using artificial intelligence (AI).

It’s not unusual to feel bewildered at a technology conference, so we can sympathise with Thomas Hackett, Cadence, who has a twist on the usual philosophical question of “What am I here for?” A walk through DesignCon caused a lightbulb moment, illuminating the real world interplay of IP, SoC and packaging.

With the IoT there are no secrets, and Robert Vamosi, Synopsys examines how data sharing may not be as innocuous as companies would have us believe, if it is not configured flawlessly. The Strava heatmap which reveals secret military locations has thrown up some serious issues which, we are assured, are being addressed, and which Vamosi sees as a model for other IoT and wearable device manufacturers.

Tackling software-defined networking (SDN) head-on, Jean-Marie Brunet, Mentor Graphics, presents a clear and strong case for accelerating verification using virtual emulation. Of course he advocates Veloce VirtuaLAB PCIe for the task, but backs up his recommendation with some sound reasoning and guidance.

By Caroline Hayes, Senior Editor

Driving To the Shops with Graphics and Bluetooth

Monday, January 29th, 2018

The car’s the star this week, as bloggers look to upgrade models, examine the safety systems, and look at how to use graphics. Other posts concentrate on retail therapy and how Bluetooth can help warehouses manage stock and processes

There’s only 330 days shopping days until Christmas, and Intel’s Ryan Parker’s blog could change how those days pan out as retail is redefined with IoT, artificial intelligence (AI), and digital signage combined with video to make the shopping experience to not only meet customer demands, but changing supply chains too.

Examining the backbone of automotive safety systems, Sandeep Taneja, Synopsys, presents an informed and well-illustrated post on what is needed and for what purpose in safety conscious vehicles.

Graphics double data rate (GDDR) memory has evolved to exceed the realm of gamers and is now used in vehicles. A blog by Rambus charts the changes and benefits of graphics technology for both inside and outside the car, and how it can be used in other markets.

The spread of the industrial IoT brings opportunities for warehouses of the future, writes Torbjørn Øvrebekk, Nordic Semiconductor. He looks at what the Bluetooth Mesh standard will mean and the benefits it will bring for networks and energy useage.

Corrie Callenbach, Cadence, has identified a great video hosted by Nick Heaton, distinguished engineer, Cadence, describing the verification challenges for SoCs when integrating CCIX (Cache Coherent Chip-to-Chip Protocol) IP.

Aligning CAD to a car leads an anonymous blogger at Altium to reminisce about old cars owned, cared for, restored, driven and abandoned when adulthood beckoned and manages to make a comparison with upgrading to the 64-bit world where PCB designers now live and work. Nostalgia mixes with practical tips on scaling up.

Caroline Hayes, Senior Editor

Blog Review – Tuesday, January 16, 2018

Tuesday, January 16th, 2018

A review from CES, and looking ahead to 2018; How the IoT will develop in industry and prototyping; Autonomous driving research; the value of HBM

Research commissioned by Arm around the road to autonomous vehicles is detailed in a blog by Andy Moore. He provides a link to a white paper that touches on the state of ADAS today and what the industry is doing to develop robotaxis and autonomous driving.

After a weather and travel round-up, Paul McLellan, Cadence, highlights some of the news from CES 2018. He alights on automotive and the car designed by Dream Chip and Globalfoundries in the company’s suite and highlights from vehicle manufacturers and semiconductor companies. He also takes in a 5G keynote, TVs, augmented reality, holographs, drones, 3D printing and welcomes robots.

There are many ideas for the IoT, and how to prototype them, with dwindling ranks of hardware and software developers, is perplexing Pär Håkansson, Nordic Semiconductor. He proposes a web-based platform to ‘plug the gaps’ and the company’s own Thingy:52 and nRF Cloud to configure IoT prototypes.

For centuries, people have wanted to know what the future holds. Some mystics have attempted to predict what is to come, some with more success than others. IHS Markit limits itself to identifying transformative technologies for this year. The checklist is analysed in a white paper that can be loaded free of charge.

Another soothsayer is Chet Hellum, Intel, who is not exactly sticking his neck when he says the IoT is going to be big in 2018. His blog looks at how the IoT will drive manufacturing trends in 2018 and the benefits investments can bring to a smart factory.

The role of memory in high bandwith graphics, high performance computing and artificial intelligence will present verification challenges. Shaily Khare, Synopsys examines the structure and strengths of High Bandwith Memory (HBM), the enhancements of HBM2 and how to exploit its properties.

By Caroline Hayes, Senior Editor

Blog Review – Monday, December 11, 2017

Sunday, December 10th, 2017

Looking through the blogshphere, we find packaging issues ahead of the holidays; Life on the IoT edge; billions of connected devices – what does it even mean? and taking nature’s lead in 3D printing

According to Paul McLellan, Cadence, Moore’s Law is running out of steam. He spoke to John Park about advanced packaging and heterogeneous integration.

Living life on the edge, Jeff Miller, Mentor Graphics, sets out a step program for IoT design and advocates a standardized directory structure.

Anticipating one trillion smart, connected devices, Christine Young, Maxim Integrated, looks to the future and what the predicted scale of connectivity will mean for intelligence gathering and sharing, and their role in emerging technologies, such as blockchain.

Taking a cue from nature’s own materials, Scott Goodrich, Fortify guest blogs for ANSYS to explain how magnetic fields were used in 3D printing to align fibers for high strength-to-weight ratio printed parts.

Consumer trends that signal the end of wired audio connections has set Mark Melvin, ON Semiconductor, thinking about hearing aids and adding intelligence via wireless connectivity with smartphones.

Trends for the semiconductor chip market are discussed by John Blyler and Jim Feldan, Semico Research. The complexity is increasing which could impact the number of design starts. One trend is IP reuse and this informative report looks into the facts and figures in great detail to provide an understanding of the industry direction.

By Caroline Hayes, Senior Editor

Blog Review – Monday, October 23, 2017

Monday, October 23rd, 2017

This week blogs are focused on health and AI, from remote care for the elderly to asthma inhalers using machine learning; plus sewer cleaning and multimedia SoCs

The autonomous car can reduce hospital visits by visiting patients – but won’t that put more cars on the road? David P Ryan, Intel advocates a delivery service for the next generation of healthcare.

Taking an engineer’s view on every object, Peter Ferguson, Arm, looks at the asthma inhaler and takes a deep breath at the Amiko ‘smart’ inhaler which uses an Arm Cortex-M processor.

Former Cadence employee, Vishal Kapoor, presented Preparing for the Cognitive Era, at San Jose State University. Paul McLellan, Cadence reports on why Kapoor is worried about the amount of data companies are collecting.

The importance of video content, used in augmented reality devices and 4K UHD TV, relies on efficient multimedia SoCs. Richard Pugh, Mentor, looks at some of the ways and means to verify the data and cites an interesting example of a customer developing a drone.

No wonder it’s called Solo – who would want to join RedZone Robotics’ autonomous sewer-inspection robot (called Solo)? Steve Leibson, Xilinx, uncovers the clean workings of the robot that crawls and records where others refuse to go, and explains how it uses Spartan FPGA for image processing and for AI. (There’s a video too – but it’s not a mucky one!)

Enough about the IoT, says Jim Harrison, Lincoln Technology Communications, guest blogging for Maxim Integrated. What about how to connect millions of sensors and actuators? He lays out a comprehensive ‘shopping list’ of long range wireless comms and connection options to help speed up the IoT conversation.

Coming full circle, Marc Horner, ANSYS, relates the case study of computational modeling for insulin delivery systems.

Caroline Hayes, Senior Editor

Blog Review – Monday, September 25, 2017

Monday, September 25th, 2017

This week, there are some prophecies: What does the future hold for the IoT and for vehicle design? Why is 3D facial recognition a sound idea and why the world should be divided into 3x3mm pieces.

A trillion devices in the IoT – and counting. Frank Schirrmeisster, Cadence, is worried about security, safety, design and verification and system architectures for the expanding IoT. Will next month’s Arm TechCon be able to allay some of this fears?

Calling for a holistic approach to DVFS, Don Dingee, Sonics, looks at what could be standing in the way of designers and what it might mean for IP sub-systems.

The reality of self-driving cars and the role of the connected car to achieve autonomous vehicles, is addressed by Randall Wollschlager, Maxim Integrated, in a Q&A with Christine Young.

Aiming to unite the world, Colin Walls, Mentor, calls for a universal GPS format that divides the world in to 3x3mm squares for pinpoint precision.

Channeling 007, CircuitStudio author, Altium, looks at the iPhone X and its 3D facial recognition technology, and examines how it’s done and for what ends.

Fresh from a trip to Asia, Sean Safarpour, Synopsys, is full of praise for formal verification and how it has been embraced by companies there.

Better than ‘dad dancing’ the robot dance is celebrated by Bob Rogers, Intel, who reviews the ‘Intel Day at Berkeley’. The event at UC Berkeley highlighted areas of research for AI, IoT, autonomous vehicles and surgeon robots.

Caroline Hayes, Senior Editor

Blog Review – Monday, August 14, 2017

Monday, August 14th, 2017

This week, the blogsphere reveals how FPGAs adopt a MeerKAT stance; OML brings life to Industry 4.0; Wearable pairing boosts charging and rigid-flex PCB design tips

A keen advocate of rigid-flex PCB design, Alexsander Tamari, Altium, offers sound design advice for the routing challenges that it may present. There is a link to an informative white paper too.

We love wearables but charging devices wirelessly can present problems, but luckily Susan Coleman, ANYS, is able to describe the company’s recent collaboration with RF2ANTENNA. She describes with tips for efficiency improvements using its tools.

Another classic challenge is taken on by Arthur Schaldenbrand, Cadence. He continues his analog design series and looks at process variation, and countering die costs, power dissipation, with reference to the use of Monte Carlo analysis.

Chip Design’s John Blyler talks to Mentor’s Director of Product Management, Warren Kurisu, about a biometrics game and increased productivity using the Cloud.

Discovering new galaxies is exciting but is demanding on processing power and memory speeds. Steve Leibson, Xilinx, reflects on what the MeerKAR radio telescope has achieved and how FPGAs have played a part.

Ruminating on this year’s SMT Hybrid Packaging event, Danit Atar, Mentor Graphics, reviews what she claims is the world’s first IoT live public demonstration of a manufacturing line, and how Open Manufacturing Language (OML) bring Industry 4.0 to life.

Software integrity is never far from an engineer’s mind, and David Benas, Synopsys, presents a compelling argument for implementing security measures into the software development life cycle (SDLC) from start to finish.

By Caroline Hayes, Senior Editor

Blog Review Monday, May 8, 2017

Monday, May 8th, 2017

This week, there is some N7 news, and the beginning of an HPC renaissance; ARM survives a mountain-top ordeal and Intel has a strategy for IoT; Odd place for sunburn

https://community.cadence.com/cadence_blogs_8/b/breakfast-bytes/archive/2017/05/05/tsmc-n7

TSMC’s 7nm process is detailed by Paul McLellan, Cadence, from a visit to CDNLive Silicon Valley. His report is well illustrated and informative.

Predicting a second renaissance in high-performance computing (HPC), Prasad Alavilli, ANSYS, explains the role of CFD and the state-of-play for HPC and what that means for chip design.

Likening Internet security to the American ‘wild west’, Alan Grau, Icon Labs, fears for security measures and corrective actions. He looks at some recent attacks and cures and advocates a strong stance on security.

I suspect Scott Salzwedel, Mentor Graphics, is rather excited about the New Horizons spacecraft, which is due to emerge from its hibernation. His enthusiasm is infectious, and his well-illustrated blog puts the reader as in thrall to the project – and the role of the company’s own Nucleus RTOS – as he clearly is.

The three phases of the IoT revolution are set out by Aaron Tersteeg, Intel. He sets out a clear plan to nuture big ideas and how technology can support the evolution.

PVT (process, voltage and temperature) sensor systems are exciting Rupert Baines, UltraSoC. He considers the company’s co-operation with Moortec Semiconductor, and what this means for SoC monitoring.

Life is not looking too rosy for ARM engineer Matt Du Puy and fellow climbers, at the moment. They are stuck on Mt Kanchenjunga in Nepal, without the drone copter that was confiscated by customs officials. True the team has a toolbox of ARM-powered devices, like the Suunto Ambit smartwatch, satellite beacon, Outernet networking device, Google Pixel smartphone, Go Pro and Ricoh Theta 360-degree camera, reports Brian Fuller, ARM, but there is also sunburn – inside the nostrils (eughhh!).

Caroline Hayes, Senior Editor

Cadence Launches New Verification Solutions

Tuesday, March 14th, 2017

Gabe Moretti, Senior Editor

During this year’s DVCon U.S. Cadence introduced two new verification solutions: the Xcelium Parallel Simulator and the Protium S1 FPGA-Based Prototyping Platform, which incorporates innovative implementation algorithms to boost engineering productivity.

Xcelium Parallel Simulator

.The new simulation engine is based on innovative multi-core parallel computing technology, enabling systems-on-chip (SoCs) to get to market faster. On average, customers can achieve 2X improved single-core performance and more than 5X improved multi-core performance versus previous generation Cadence simulators. The Xcelium simulator is production proven, having been deployed to early adopters across mobile, graphics, server, consumer, internet of things (IoT) and automotive projects.

The Xcelium simulator offers the following benefits aimed at accelerating system development:

  • Multi-core simulation improves runtime while also reducing project schedules: The third generation Xcelium simulator is built on the technology acquired from Rocketick. It speeds runtime by an average of 3X for register-transfer level (RTL) design simulation, 5X for gate-level simulation and 10X for parallel design for test (DFT) simulation, potentially saving weeks to months on project schedules.
  • Broad applicability: The simulator supports modern design styles and IEEE standards, enabling engineers to realize performance gains without recoding.
  • Easy to use: The simulator’s compilation and elaboration flow assigns the design and verification testbench code to the ideal engines and automatically selects the optimal number of cores for fast execution speed.
  • Incorporates several new patent-pending technologies to improve productivity: New features that speed overall SoC verification time include SystemVerilog testbench coverage for faster verification closure and parallel multi-core build.

“Verification is often the primary cost and schedule challenge associated with getting new, high-quality products to market,” said Dr. Anirudh Devgan, senior vice president and general manager of the Digital & Signoff Group and the System & Verification Group at Cadence. “The Xcelium simulator combined with JasperGold Apps, the Palladium Z1 Enterprise Emulation Platform and the Protium S1 FPGA-Based Prototyping Platform offer customers the strongest verification suite on the market”

The new Xcelium simulator further extends the innovation within the Cadence Verification Suite and supports the company’s System Design Enablement (SDE) strategy, which enables system and semiconductor companies to create complete, differentiated end products more efficiently. The Verification Suite is comprised of best-in-class core engines, verification fabric technologies and solutions that increase design quality and throughput, fulfilling verification requirements for a wide variety of applications and vertical segments.

Protium S1

The Protium S1 platform provides front-end congruency with the Cadence Palladium Z1 Enterprise Emulation Platform. BY using Xilinx Virtex UltraScale FPGA technology, the new Cadence platform features 6X higher design capacity and an average 2X performance improvement over the previous generation platform. The Protium S1 platform has already been deployed by early adopters in the networking, consumer and storage markets.

Protium S1 is fully compatible with the Palladium Z1 emulator

To increase designer productivity, the Protium S1 platform offers the following benefits:

  • Ultra-fast prototype bring-up: The platform’s advanced memory modeling and implementation capabilities allow designers to reduce prototype bring-up from months to days, thus enabling them to start firmware development much earlier.
  • Ease of use and adoption: The platform shares a common compile flow with the Palladium Z1 platform, which enables up to 80 percent re-use of the existing verification environment and provides front-end congruency between the two platforms.
  • Innovative software debug capabilities: The platform offers firmware and software productivity-enhancing features including memory backdoor access, waveforms across partitions, force and release, and runtime clock control.

“The rising need for early software development with reduced overall project schedules has been the key driver for the delivery of more advanced emulation and FPGA-based prototyping platforms,” said Dr. Anirudh Devgan, senior vice president and general manager of the Digital & Signoff Group and the System & Verification Group at Cadence. “The Protium S1 platform offers software development teams the required hardware and software components, a fully integrated implementation flow with fast bring-up and advanced debug capabilities so they can deliver the most compelling end products, months earlier.”

The Protium S1 platform further extends the innovation within the Cadence Verification Suite and supports the company’s System Design Enablement (SDE) strategy, which enables system and semiconductor companies to create complete, differentiated end products more efficiently. The Verification Suite is comprised of best-in-class core engines, verification fabric technologies and solutions that increase design quality and throughput, fulfilling verification requirements for a wide variety of applications and vertical segments.

Behold the Intrinsic Value of IP

Monday, March 13th, 2017

By Grant Pierce, CEO

Sonics, Inc.

Editor’s Note [this article was written in response to questions about IP licensing practices.  A follow-up article will be published in the next 24 hours with the title :” Determining a Fair Royalty Value for IP”].

figure

Understanding the intrinsic value of Intellectual Property is like beauty, it is in the eye of the beholder.  The beholder of IP Value is ultimately the user/consumer of that IP – the buyers. Buyers tend to value IP based upon their ability to utilize that IP to create competitive advantage, and therefore higher value for their end product. The IP Value figure above was created to capture this concept.

To be clear, this view is NOT about relative bargaining power between buyer and the supplier of IP – the seller –  that is built on the basis of patents. Mounds of court cases and text books exist that explore the question of patent strength. What I am positing is that viewing IP value as a matter of a buyer’s perception is a useful way to think of the intrinsic value of IP.

Position A on the value chart is a classification of IP that allows little differentiation by the buyer, but is addressing a more elastic market opportunity. This would likely be a Standard IP type that would implement an open standard. IP in this category would likely have multiple sources and therefore competitive pricing.  Although compliance with the standard would be valued by the buyer, the price of the IP itself would be likely lower reflecting its commodity nature. Here, the value might be equated to the cost of internally creating equivalent IP. Since few, if any, buyers in this category would see advantage for making this IP themselves and because there are likely many sellers, the intrinsic value of this IP is determined on a “buy vs buy” basis.  Buyers are going to buy this IP regardless, so they’ll look for the seller with the proposition most favorable to the buyer – which often is just about price.

Position B on the value chart is a classification of IP that allows for differentiation by the buyer, but addresses a more elastic market. IP in this category might be less constrained by standards requirements. It is likely that buyers would implement unique instantiations of this IP type and as a result command some end competitive advantage. Buyers in this category could make this IP themselves, but because there are commercial alternatives, the intrinsic value is determined by applying a “make vs buy” analysis. The value proposition of the sellers of this type of IP often include some important, but soft value propositions (e.g., ease of re-use, time-to-market, esoteric features), the make vs buy determination is highly variable and often buyer-specific. This in part explains the variability of pricing for this type of IP.

Position C on the value chart is a classification of IP that serves a less elastic market and empowers buyers to differentiate through their unique implementations of that IP. This classification of IP supports license fees and larger, more consistent, royalty rates. IP in this category becomes the competitive differentiation that sways large market share to the winning products incorporating that IP. This category supports some of the larger IP companies in the marketplace today. Buyers in this category are not going to make the IP themselves because the cost of development of the product and its ecosystem is too prohibitive and risky. The intrinsic value really comes down to what the seller charges.

This is a “buy vs not make” decision – meaning one either buys the IP or it doesn’t bother to make the product. A unique hallmark of IP in this position is that so long as the seller applies pricing consistently, then all buyers know at the very least that they are not disadvantaged relative to the competition and will continue to buy. Sellers will often give some technology away to encourage long-term lock in. For these reasons, pricing of IP in this space tends to be quite stable. That pricing level must subjectively be below the level that customers begin to perform unnatural acts and explore unusual alternatives.  So long as it does, the price charged probably represents accurately the intrinsic value.

Position D on the value chart is a classification of IP that requires adherence to a standard. Like category A, adherence to the standard does not necessarily allow differentiation to the buyer. The buyer of this category of IP might be required to use this IP in order to gain access to the market itself. Though the lack of end-product differentiation available to the buyer might suggest a lower license fee and/or lower to zero royalty rate, we see a significantly less elastic market for this IP type.

This IP category tends to comprise products adhering to closed and/or proprietary standards. IP products built on such closed and/or proprietary standards have given rise to several significant IP business franchises in the marketplace today. The IP in position D is in part characterized by the need to spend significant time and money to develop, market and maintain (defend) their position, in addition to spending on IP development. For this reason, teasing out the intrinsic value of this IP is not as straightforward as “make vs buy.” Pricing is really viewed more as a tax. So the intrinsic value determination is based on a “Fair Tax” basis. If buyers think the tax is no longer “fair,” for any reason, they will make the move to a different technology.

Examples:

Position A:  USB, PCI, memory interfaces (Synopsys)

Position B:  Configurable Processors, Analog IP cores (Synopsys, Cadence)

Position C:  General Purpose Processors, Graphics, DSP, NoC, EPU (ARM, Imagination, CEVA, Sonics)

Position D: CDMA, Noise Reduction, DDR (Qualcomm, Dolby, Rambus)

Why Customer Success is Paramount

Sonics is an IP supplier whose products tend to reside in the Type C category. Sonics sets its semiconductor IP pricing as a function of the value of the SoC design/chip that uses the IP. There is a spectrum of value functions for the Sonics IP depending upon the type of chip, complexity of design, target power/performance, expected volume, and other factors. Defining the upper and lower bounds of the value spectrum depends upon an approximation of these factors for each particular chip design and customer.

Royalties are one component of the price of IP and are a way of risk sharing to allow customers to bring their products to market without having to pay the full value of the incorporated IP up front. The benefit being that the creator and supplier of the IP is essentially investing in the overall success of the user’s product by accepting the deferred royalty payment. Sonics views the royalty component of its IP pricing as “customer success fees.”

With its recently introduced EPU technology, Sonics has adopted an IP business model based upon an annual technology access fee and a per power grain usage fee due at chip tapeout. Under this model, customers have unlimited use of the technology to explore power control for as many designs as they want, but only pay for their actual IP usage in a completed design. The tape out fee is calculated based on the number of power grains used in the design on a sliding scale. The more power grains customers use, the more energy saved, and the lower the cost per grain. Using more power grains drives lower energy consumption by the chip – buyers increase the market value of their chips using Sonics’ EPU technology. The bottom line is that Sonics’ IP business model depends on customers successfully completing their designs using Sonics IP.

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