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Blog Review Monday, May 8, 2017

Monday, May 8th, 2017

This week, there is some N7 news, and the beginning of an HPC renaissance; ARM survives a mountain-top ordeal and Intel has a strategy for IoT; Odd place for sunburn

https://community.cadence.com/cadence_blogs_8/b/breakfast-bytes/archive/2017/05/05/tsmc-n7

TSMC’s 7nm process is detailed by Paul McLellan, Cadence, from a visit to CDNLive Silicon Valley. His report is well illustrated and informative.

Predicting a second renaissance in high-performance computing (HPC), Prasad Alavilli, ANSYS, explains the role of CFD and the state-of-play for HPC and what that means for chip design.

Likening Internet security to the American ‘wild west’, Alan Grau, Icon Labs, fears for security measures and corrective actions. He looks at some recent attacks and cures and advocates a strong stance on security.

I suspect Scott Salzwedel, Mentor Graphics, is rather excited about the New Horizons spacecraft, which is due to emerge from its hibernation. His enthusiasm is infectious, and his well-illustrated blog puts the reader as in thrall to the project – and the role of the company’s own Nucleus RTOS – as he clearly is.

The three phases of the IoT revolution are set out by Aaron Tersteeg, Intel. He sets out a clear plan to nuture big ideas and how technology can support the evolution.

PVT (process, voltage and temperature) sensor systems are exciting Rupert Baines, UltraSoC. He considers the company’s co-operation with Moortec Semiconductor, and what this means for SoC monitoring.

Life is not looking too rosy for ARM engineer Matt Du Puy and fellow climbers, at the moment. They are stuck on Mt Kanchenjunga in Nepal, without the drone copter that was confiscated by customs officials. True the team has a toolbox of ARM-powered devices, like the Suunto Ambit smartwatch, satellite beacon, Outernet networking device, Google Pixel smartphone, Go Pro and Ricoh Theta 360-degree camera, reports Brian Fuller, ARM, but there is also sunburn – inside the nostrils (eughhh!).

Caroline Hayes, Senior Editor

Cadence Launches New Verification Solutions

Tuesday, March 14th, 2017

Gabe Moretti, Senior Editor

During this year’s DVCon U.S. Cadence introduced two new verification solutions: the Xcelium Parallel Simulator and the Protium S1 FPGA-Based Prototyping Platform, which incorporates innovative implementation algorithms to boost engineering productivity.

Xcelium Parallel Simulator

.The new simulation engine is based on innovative multi-core parallel computing technology, enabling systems-on-chip (SoCs) to get to market faster. On average, customers can achieve 2X improved single-core performance and more than 5X improved multi-core performance versus previous generation Cadence simulators. The Xcelium simulator is production proven, having been deployed to early adopters across mobile, graphics, server, consumer, internet of things (IoT) and automotive projects.

The Xcelium simulator offers the following benefits aimed at accelerating system development:

  • Multi-core simulation improves runtime while also reducing project schedules: The third generation Xcelium simulator is built on the technology acquired from Rocketick. It speeds runtime by an average of 3X for register-transfer level (RTL) design simulation, 5X for gate-level simulation and 10X for parallel design for test (DFT) simulation, potentially saving weeks to months on project schedules.
  • Broad applicability: The simulator supports modern design styles and IEEE standards, enabling engineers to realize performance gains without recoding.
  • Easy to use: The simulator’s compilation and elaboration flow assigns the design and verification testbench code to the ideal engines and automatically selects the optimal number of cores for fast execution speed.
  • Incorporates several new patent-pending technologies to improve productivity: New features that speed overall SoC verification time include SystemVerilog testbench coverage for faster verification closure and parallel multi-core build.

“Verification is often the primary cost and schedule challenge associated with getting new, high-quality products to market,” said Dr. Anirudh Devgan, senior vice president and general manager of the Digital & Signoff Group and the System & Verification Group at Cadence. “The Xcelium simulator combined with JasperGold Apps, the Palladium Z1 Enterprise Emulation Platform and the Protium S1 FPGA-Based Prototyping Platform offer customers the strongest verification suite on the market”

The new Xcelium simulator further extends the innovation within the Cadence Verification Suite and supports the company’s System Design Enablement (SDE) strategy, which enables system and semiconductor companies to create complete, differentiated end products more efficiently. The Verification Suite is comprised of best-in-class core engines, verification fabric technologies and solutions that increase design quality and throughput, fulfilling verification requirements for a wide variety of applications and vertical segments.

Protium S1

The Protium S1 platform provides front-end congruency with the Cadence Palladium Z1 Enterprise Emulation Platform. BY using Xilinx Virtex UltraScale FPGA technology, the new Cadence platform features 6X higher design capacity and an average 2X performance improvement over the previous generation platform. The Protium S1 platform has already been deployed by early adopters in the networking, consumer and storage markets.

Protium S1 is fully compatible with the Palladium Z1 emulator

To increase designer productivity, the Protium S1 platform offers the following benefits:

  • Ultra-fast prototype bring-up: The platform’s advanced memory modeling and implementation capabilities allow designers to reduce prototype bring-up from months to days, thus enabling them to start firmware development much earlier.
  • Ease of use and adoption: The platform shares a common compile flow with the Palladium Z1 platform, which enables up to 80 percent re-use of the existing verification environment and provides front-end congruency between the two platforms.
  • Innovative software debug capabilities: The platform offers firmware and software productivity-enhancing features including memory backdoor access, waveforms across partitions, force and release, and runtime clock control.

“The rising need for early software development with reduced overall project schedules has been the key driver for the delivery of more advanced emulation and FPGA-based prototyping platforms,” said Dr. Anirudh Devgan, senior vice president and general manager of the Digital & Signoff Group and the System & Verification Group at Cadence. “The Protium S1 platform offers software development teams the required hardware and software components, a fully integrated implementation flow with fast bring-up and advanced debug capabilities so they can deliver the most compelling end products, months earlier.”

The Protium S1 platform further extends the innovation within the Cadence Verification Suite and supports the company’s System Design Enablement (SDE) strategy, which enables system and semiconductor companies to create complete, differentiated end products more efficiently. The Verification Suite is comprised of best-in-class core engines, verification fabric technologies and solutions that increase design quality and throughput, fulfilling verification requirements for a wide variety of applications and vertical segments.

Behold the Intrinsic Value of IP

Monday, March 13th, 2017

By Grant Pierce, CEO

Sonics, Inc.

Editor’s Note [this article was written in response to questions about IP licensing practices.  A follow-up article will be published in the next 24 hours with the title :” Determining a Fair Royalty Value for IP”].

figure

Understanding the intrinsic value of Intellectual Property is like beauty, it is in the eye of the beholder.  The beholder of IP Value is ultimately the user/consumer of that IP – the buyers. Buyers tend to value IP based upon their ability to utilize that IP to create competitive advantage, and therefore higher value for their end product. The IP Value figure above was created to capture this concept.

To be clear, this view is NOT about relative bargaining power between buyer and the supplier of IP – the seller –  that is built on the basis of patents. Mounds of court cases and text books exist that explore the question of patent strength. What I am positing is that viewing IP value as a matter of a buyer’s perception is a useful way to think of the intrinsic value of IP.

Position A on the value chart is a classification of IP that allows little differentiation by the buyer, but is addressing a more elastic market opportunity. This would likely be a Standard IP type that would implement an open standard. IP in this category would likely have multiple sources and therefore competitive pricing.  Although compliance with the standard would be valued by the buyer, the price of the IP itself would be likely lower reflecting its commodity nature. Here, the value might be equated to the cost of internally creating equivalent IP. Since few, if any, buyers in this category would see advantage for making this IP themselves and because there are likely many sellers, the intrinsic value of this IP is determined on a “buy vs buy” basis.  Buyers are going to buy this IP regardless, so they’ll look for the seller with the proposition most favorable to the buyer – which often is just about price.

Position B on the value chart is a classification of IP that allows for differentiation by the buyer, but addresses a more elastic market. IP in this category might be less constrained by standards requirements. It is likely that buyers would implement unique instantiations of this IP type and as a result command some end competitive advantage. Buyers in this category could make this IP themselves, but because there are commercial alternatives, the intrinsic value is determined by applying a “make vs buy” analysis. The value proposition of the sellers of this type of IP often include some important, but soft value propositions (e.g., ease of re-use, time-to-market, esoteric features), the make vs buy determination is highly variable and often buyer-specific. This in part explains the variability of pricing for this type of IP.

Position C on the value chart is a classification of IP that serves a less elastic market and empowers buyers to differentiate through their unique implementations of that IP. This classification of IP supports license fees and larger, more consistent, royalty rates. IP in this category becomes the competitive differentiation that sways large market share to the winning products incorporating that IP. This category supports some of the larger IP companies in the marketplace today. Buyers in this category are not going to make the IP themselves because the cost of development of the product and its ecosystem is too prohibitive and risky. The intrinsic value really comes down to what the seller charges.

This is a “buy vs not make” decision – meaning one either buys the IP or it doesn’t bother to make the product. A unique hallmark of IP in this position is that so long as the seller applies pricing consistently, then all buyers know at the very least that they are not disadvantaged relative to the competition and will continue to buy. Sellers will often give some technology away to encourage long-term lock in. For these reasons, pricing of IP in this space tends to be quite stable. That pricing level must subjectively be below the level that customers begin to perform unnatural acts and explore unusual alternatives.  So long as it does, the price charged probably represents accurately the intrinsic value.

Position D on the value chart is a classification of IP that requires adherence to a standard. Like category A, adherence to the standard does not necessarily allow differentiation to the buyer. The buyer of this category of IP might be required to use this IP in order to gain access to the market itself. Though the lack of end-product differentiation available to the buyer might suggest a lower license fee and/or lower to zero royalty rate, we see a significantly less elastic market for this IP type.

This IP category tends to comprise products adhering to closed and/or proprietary standards. IP products built on such closed and/or proprietary standards have given rise to several significant IP business franchises in the marketplace today. The IP in position D is in part characterized by the need to spend significant time and money to develop, market and maintain (defend) their position, in addition to spending on IP development. For this reason, teasing out the intrinsic value of this IP is not as straightforward as “make vs buy.” Pricing is really viewed more as a tax. So the intrinsic value determination is based on a “Fair Tax” basis. If buyers think the tax is no longer “fair,” for any reason, they will make the move to a different technology.

Examples:

Position A:  USB, PCI, memory interfaces (Synopsys)

Position B:  Configurable Processors, Analog IP cores (Synopsys, Cadence)

Position C:  General Purpose Processors, Graphics, DSP, NoC, EPU (ARM, Imagination, CEVA, Sonics)

Position D: CDMA, Noise Reduction, DDR (Qualcomm, Dolby, Rambus)

Why Customer Success is Paramount

Sonics is an IP supplier whose products tend to reside in the Type C category. Sonics sets its semiconductor IP pricing as a function of the value of the SoC design/chip that uses the IP. There is a spectrum of value functions for the Sonics IP depending upon the type of chip, complexity of design, target power/performance, expected volume, and other factors. Defining the upper and lower bounds of the value spectrum depends upon an approximation of these factors for each particular chip design and customer.

Royalties are one component of the price of IP and are a way of risk sharing to allow customers to bring their products to market without having to pay the full value of the incorporated IP up front. The benefit being that the creator and supplier of the IP is essentially investing in the overall success of the user’s product by accepting the deferred royalty payment. Sonics views the royalty component of its IP pricing as “customer success fees.”

With its recently introduced EPU technology, Sonics has adopted an IP business model based upon an annual technology access fee and a per power grain usage fee due at chip tapeout. Under this model, customers have unlimited use of the technology to explore power control for as many designs as they want, but only pay for their actual IP usage in a completed design. The tape out fee is calculated based on the number of power grains used in the design on a sliding scale. The more power grains customers use, the more energy saved, and the lower the cost per grain. Using more power grains drives lower energy consumption by the chip – buyers increase the market value of their chips using Sonics’ EPU technology. The bottom line is that Sonics’ IP business model depends on customers successfully completing their designs using Sonics IP.

Blog Review – Monday, August 15 2016

Monday, August 15th, 2016

In this collection, we define the IoT, investigate IP fingerprinting, and break into vehicles in the name of crypto-research. There is also prophesizing about 5G and disruption technology for technology, and relationship advice for computing and data.

Empathizing with anyone who has ever struggled with CMSIS RTOS API, Liviu Ionescu, ARM, offers a helping hand, catalogues the issues that can be encountered and reassures designers they are not alone and, more importantly, offers practical help.

Putting IP fingerprints to work may sound like the brief for an episode of CSI, but it is Warren Savage’s, (IP-extreme) recipe for successful SoC tapeout. He does do some CSI-style digging to thoroughly explain how to delve into a chip’s IP to limit the risks associated with IP reuse.

Listening intently at the Linley Mobile Conference, Paul McLellan, Cadence, sees the advent of 5G as good news for high-capacity, high-speed, low-latency wireless networks and linked with all things IoT.

Famous couplings, love and marriage, horse and carriage, could be joined by computing and data. Rob Crooke, Intel, believes that an increase in data and increased computing will transform cloud computing, but that memory storage has to keep up to realize smart cities to autonomous vehicles, industrial automation, medicine, immersive gaming to name a few. His post covers 3D XPoint and 3D NAND technology.

On security detail this week, Gabe Moretti, Chip Design magazine, finds a white paper from Intrinsic-ID that he recommends on the topic of embedded authentication which is vital to the secure operation of the IoT.

At the end of this year, the last Volkswagen Camper, (or kombi) van, will roll off the assembly line in Brazil. Robert Vamosi, Synopsys, includes the iconic vehicle in his post about a hack related in a paper authored by researchers at the University of Birmingham to clone a VW remote entry systems. The paper was presented at the Usenix cybersecurity conference in Austin, Texas, with reassurances that the group is in ‘constructive’ talks with VW.

For a vintage automobile to the latest, EV and PHEVs, Andrew Macleod, Mentor Graphics, looks at disruption they may bring to the automotive industry. Referring to account technology manager Paul Johnston’s presentation at 2016 IESF, he touches on the electrical engineering and embedded software challenges as well as the predicted scale of the EV industry.

Still looking at a market rather than the technology, Alex Voica, Imagination Technologies, looks at the IoT. He has some interesting graphs and statistics and asks some interesting questions around definitions, from what is the IoT and what defines a device.

Caroline Hayes, Senior Editor

Blog Review – Monday, June 13, 2016

Monday, June 13th, 2016

DAC 2016 highlights; Medical technology and IoT; Autonomous car market races ahead; Remote controlled beer; Secure connectivity

Distinguishing between Big Data and Business Intelligence, ScientistBob, Intel, identifies a ‘watershed’ moment for Big Data and Intel’s steps with Intel Xeon processors to deliver the next step in data analytics.

In response to FCC regulations, the prpl Foundation addresses next-generation security for connected devices. Alexandru Voica, Imagination Techologies, has collected some useful information (demo, white paper, devices, kits and links) to show the progress made.

A fascinating medical application is detailed in Steve Leibso, Xilinx, as he describes how the Xynq-7000 SoC in an eye-tracking computer interface. The video is a little ‘salesy’ and could have benefitted from some more examples of use rather than talking heads but has some practical engineering information about how the processing moves to the SoC.

Continuing the medical theme, Thierry Marchal, ANSYS, tantalizes readers ahead of a medical IoT webinar (June 22) by Cambridge Consultants. He has some interesting statistics to put the topic into context, some graphics and an exploration of the communications protocols involved.

The 53 rd DAC saw ARM launch ARM Artisan physical IP, including POP IP, targeting mainstream mobile designs. Brian Fuller, ARM, adds some meat to the bones with comment from Will Abbey, general manager, ARM’s Physical Design Group.

Automotive design at DAC captured the interest of Christine Young, Cadence, who reports on the keynote by Lars Reger, CTO Automotive Business Unit, NXP Semiconductors. She looks at the security issues for vehicles from the family car to trucks.

Beer that comes to you takes the slog out of summer al fresco dining, doesn’t it? The Atmel team details the use of an ATmefa8 MCU for a remote controlled beer crate, with a link to the build recipe list.

Here in the UK, we are knee-deep in discussions about how to get on with our neighbours as an EU membership referendum looms. A model for happy international relations is here in the blog by Devi Keller, Semiconductor Industry Association, which records the 20 years of the World Semiconductor Council (WSC).

A trip to Detroit for Robert Bates, Mentor Graphics, for its IESF conference, was a source of great material for all things related to autonomous cars. Keynotes and networking led him to consider safety and neural network questions around the technology.

Putting it all into practise, the first Self Racing Cars track event is gleefully reported by Danny Shapiro, Nvidia. There are some great images capturing the spirit of a ground-breaking event. Last weekend a momentous event in the motorsports and automotive world took place. Of course, the company’s technology is used and there is a handy list of what was used and where.

Caroline Hayes, Senior Editor

Blog Review – Monday, February 15, 2016

Monday, February 15th, 2016

Research converts contact lens to computer screens; What to see at Embedded World 2016; Remembering Professor Marvin Minsky; How fast is fast and will the IoT protect us?

The possibilities for wearable technology, where a polymer film coating can turn a contact lens into a computer screen are covered by Andrew Spence Nanontechnology University of South Australia’s Future Industries Institute. The lens can be used as a sensor to measure blood glucose levels to a pair of glasses acting as a computer screen.

If you are preparing your Embedded World 2016, Nuremberg, schedule, Philippe Bressy, ARM offers an overview of what will be at his favourite event. He covers the company’s offerings for IoT and connectivity, single board computing, software productivity, automotive and from ARM’s partners to be seen on the ARM booth (Hall 5, stand 338), as well as some of the technical conference’s sessions and classes.

Other temptations can be found at the Xilinx booth at Embedded World (Hall 1, stand 205). Steve Leibson, Xilinx explains how visitors can win a Digilent ARTY Dev Kit based on an Artix-7 A35T -1LI FPGA, with Xilinx Vivado HLx Design Edition.

Showing more of what can be done with the mbed IoT Device Platform, Liam Dillon, ARM, writes about the reference system for SoC design for IoT endpoints, and its latest proof-of-concept platform, Beetle.

How fast is fast, muses Richard Mitchell, Ansys. He focuses on the Ansys 17.0 and its increased speeds for structural analysis simulations and flags up a webinar about Ansys Mechanical using HPC on March 3.

If the IoT is going to be omnipresent, proposes Valerie C, Dassault, can we be sure that it can protect us and asks, what lies ahead.

A pioneer of artificial intelligence, Professor Marvin Minsky as died at the age of 88. Rambus fellow, Dr David G Stork, remembers the man, his career and his legacy on this field of technology.

I do enjoy Whiteboard Wednesdays, and Corrie Callenback, Cadence, has picked a great topic for this one – Sachin Dhingra’s look at automotive Ethernet.

Another thing I particularly enjoy is a party, and Hélène Thibiéroz, Synopsys reminds us that it is 35 years since HSPICE was introduced. (Note to other party-goers: fireworks to celebrate are nice, but cake is better!)

Caroline Hayes, European Editor

Blog Review – Monday, January 25 2016

Monday, January 25th, 2016

In this week’s review, there is a Star Wars analogy, IoT security plans, a 30th anniversary and an unusual way of serving whisky

The dormant nature of some devices in the IoT are likened to the reawakening of Star Wars’ R2-D2 by Joe Hupcey III, Mentor Graphics. In an equally honorable and daring quest, he looks for the wisdom of ultra-low power design and verification for SoCs used in devices that wait a long time for reactivation.

FPGA with a dash of splash or on the rocks? Steve Leibson, Xilinx, explains how a bottle of fine whisky (scotch) ended up in a PC. It’s all in a good cause.

Three trends for embedded systems are identified by Amber Thousand, Critical Link. She explains how we should all be paying attention to user interfaces, the rise of complexity and integration, and a focus on core competencies.

This year marks 30 years since MIPS Computer Systems introduced the MIPS R2000 microprocessor chipset. Alexandru Voica, Imagination Technologies, considers the rise of RISC and where it has led.

Silicon is the best place to secure security features for the IoT, argues Matthew Rosenquist, Intel. He outlines the role Trusted Execution Environments (TEEs) play in the cyber future.

Clearly not a man that travels light, Navrai Nandra, Synopsys, concluded that if storage space is limited, instead of trying to close a bulging suitcase, think about moving up. His wait at the airport inspired an interesting blog on 3D stack technology to triple NAND capacity.

Looking at what the IoT design wins means for design at advanced nodes, Vassilios Gerousis, Cadence, considers the design rules for 10nm.

Caroline Hayes, Senior Editor

Blog Review – Monday, July 27 2015

Monday, July 27th, 2015

IoT for ADAS; ESC 2015 focuses on security; untangling neural networks; what drives new tools; consolidation conundrum; IoT growth forecast; three ages of FPGA

Likening a business collaboration to a road trip may be stretching a metaphor that would make Jack Kerouac blush, but David McKinney, Intel, presses on as he explains Intel and QNX’s ADAS solution, based on Intel IoT for automobiles. He includes some interesting links and a video to inform the reader.

A review of ESC 2015 shows that Chris Ciufo is not only ahead of the curve, advocating embedded security, but also not one to pass by a freebie at a show. He relates some of the highlights from the first day of the Santa Clara event.

Neural network processors hold promise for computer vision, believes Jeff Bier, BDTI. His blog explains what work is needed for the scale of computation the industry expects.

Posing an interesting question, Carey Robertson, Mentor Graphics, asks what prompts the development of new tools. He blends this with helpful information about the newly launched Calibre xACT extraction tool, without too much “hard sell”.

“It works!” is the triumphant message of the blog co-authored by Jacek Duda and Steve Brown, Cadence. Reporting from this month’s workshop where Type-C USB was put through its paces.

What to do with wireless IP is asked and answered by Navari Nandra, Synopsys. He explains what can be done and how it can contribute to the IoT.

The SoC market is consolidating fast, says Rupert Baines, UltraSoC, on an IP Exteme blog. This poses two challenges that he believes licensed IP can simplify.

A common proposition is to move from Intel to ARM, and Rich Nass, ARM presents a well-rounded blog on how to make the transition, with some input from WinSystems hardware and software experts.

Forget consumer, the future of the IoT growth is in enterprise, reports Brian Fuller, ARM, observing analyst IDC’s webinar on which parts of the IoT will be lucrative and why.

Recalling the talk by Xilinx Fellow, Dr. Steve Trimberger, Steve Leibson, explains the three ages of the FPGA, with a link to a video on the history of the technology.

Caroline Hayes, Senior Editor

Blog Review – Monday, June 22 2015

Monday, June 22nd, 2015

Yonsei Uni team up for 5G; Hold that thought; now catch it; ARM and UNICEF; Industry and Education breathe life into EDA; Connected driving clears the road ahead

Researchers at Yonsei University have demonstrated a real-time, full-duplex LTE radio system at IEEE Globecom in Austin, Texas, using a novel antenna approach and working with National Instruments SDR platforms and LabVIEW graphical programming environment, reports Steve Leibson, Xilinx.

“Hold that thought” takes a new turn, as an anonymous blogger at Atmel describes the MYLE TAP, a wearable ‘thought catcher’. The touch-activate and voice-powered device automatically converts thoughts into actions. An interesting prototype or a recipe for disaster if it falls into the wrong hands?

Charity doesn’t always begin at home, sometimes it’s a warehouse in Copenhagen, Denmark. Dominic Vergine, ARM, visited the UNICEF global procurement hub and considers what wearable technology can provide, building on the low-tech, wearable technology of the MUAC band to test for malnutrition.

Building on a presentation at DAC 2015, Richard Goering, Cadence, considers how to academia and industry can work together to revitalize EDA.

The road ahead is smooth for the connected car, reports John Day, Mentor Graphics, if you are driving a Jaguar Land Rover (JLR), anyway. He examines the connected car technology that can identify and share data on potholes, broken manholes and other hazards.

Sloth is a deadly sin, especially in IP software development, warns Tom De Schutter, Synopsys, as he examines how laze in automotive testing can be absolved with virtual prototypes as an alternative to hardware, making earlier, broader, more automated software testing available.

Caroline Hayes, Senior Editor

Blog Review – Monday, June 08, 2015

Monday, June 8th, 2015

DAC duo announce DDA; Book a date for DAC with ARM, Ansys, Cadence; Synopsys and Xilinx; True FPGA-based verification

Announcing a partnership with Cadence Design Systems at DAC 2015, Dennis Brophy, Mentor Graphics teases with some details of Deug Data API (DDA). Full details will be unveiled at a joint presentation at the Verification Academy Booth (2408) on Tuesday at 5pm.

Amongst demonstrations of an IoT sub-system for Cortex-M processors, ARM will show a new IP tooling suite and the ARM Cordio radio core IP. There will be over a dozen partners, reports Brenda Westcott, ARM, in the Connected Community Pavillion and the ARM Scavenger Hunt. (DAC June 7 – 11, ARM booth 2428).

As if justifying its place at DAC 2015, Ravi Ravikumar, Ansys, explains how the show has evolved beyond EDA for SoCs. The company will host videos on automotive, IoT and mobile, and presentations from foundry partners. (DAC June 7 – 11, Anysys booth 1232).

If you are interested in the continuum of verification engines, DAC is the place to be this week. Frank Schirrmeister, Cadence, summarizes the company’s offerings to date, with a helpful link to a COVE (Continuum of Verification Engines) article, and provides an overview of some of the key verification sessions at the Moscone Center. (DAC June 7 – 11, Cadence booth 3515).

Back with FPGA prototyping system, HAPS, Michael Posner, Synopsys, invites visitors to DAC to come see the Xilinx UltraScale VU440-based HAPs. As well as proudly previewing the hardware software development support, he also touches on the difficulties of mapping ASICs to FPGAS.

More Xilinx-DAC news, as Doug Amos’s guest blog at Aldec, announces the era of true FPGA-based verification. He believes the end of big-box emulation is nigh, following the adoption of Xilinx’s Virtex UltraScale devices in its HES-7 (Hardware Emulation Solution, seventh generation) technology.

Caroline Hayes, Senior Editor

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