Part of the  

Chip Design Magazine

  Network

About  |  Contact

Posts Tagged ‘Cadence’

Next Page »

Blog Review – Nov. 25

Monday, November 25th, 2013

By Caroline Hayes, Senior Editor

A tech museum archive is discovered; Grab a beer and watch an integrity video; In the car, connectivity is the star; Managing efficient communications & Traveler’s tales from Europe

John Day, Mentor Graphics considers the extended relationship between car buyers and car makers as connectivity means a gear change for the industry with software updates to improve performance and the range and quality of in-vehicle entertainment offered.

Can you have too much integrity? This is not a political blog, but one where Team Allegro at Cadence looks at PCB design and the type, quality and quantity of decoupling capacitors, or decaps. Any blog that encourages the reader to grab a cold, frosty beverage and watch a video– about Sigrity OptimizePI is on to a winner – even if you can guess the ending.

An interesting project is covered in the Dassault Systèmes blog by the author known only as Eric
telling how it helped Fujitsu Network Communications streamline its processes for efficiencies and to meet multi-sourcing challenges. As well as photos, a video interview gives an insight into how the company, whose customers include Verizon, eliminated inefficiencies.

ChipDesign’s John Byler reviews highlights from the International Electronics Forum (Dublin) and the Imec Technology Forum.

Hamilton Carter goes treasure hunting in half a century’s worth of the Hewett-Packard journal. Stopping to admire the sartorial elegance of engineers in ties, he unearths a nostalgia tech museum.

Investments In EDA Stocks Offer Good Returns

Wednesday, November 20th, 2013

Gabe Moretti

I have heard multiple times that once an EDA company goes public almost always the new investors do not experience the growth in the share price that other companies in the electronics industry can offer.  At least this is what one hears from publicly traded EDA companies.  I wanted to see how true the opinion is.  I looked at the last twelve months stock market performance of Cadence, Mentor, and Synopsys and compared it to a few other electronics companies’ market performance.

The EDA Companies

On October 23rd Cadence reported third quarter 2013 revenue of $367 million, compared to revenue of $339 million reported for the same period in 2012. For the last complete financial year Cadence reported revenues of $1.33 billion, an increase of 15% over 2011 results.  During the last twelve months its stock price ranged from $13.51 to $12.71 reaching a peak price of $15.77 on July 19th.  The company today has a little over 287 million shares outstanding and a EPS (earning per share) of 1.53.  it is interesting to note that almost all the publicly traded shares are owned by institutional investors.

Mentor will release its 3rd quarter 2014 soon.  For the first six months of its 2014 fiscal year Mentor reported revenue of almost $480 million.  Its last completed year of operation resulted in revenue of $1.089 billion.  Its latest EPS is 0.95.  In the last twelve months he stock reached a highest closing price of $23.62 on October 1st and the lowest price of $14.22 on November 19, 2012.  The company is in currently executing a share buyback program and plans to purchase up to $20 million worth of shares.  Also in the Mentor case almost all of the outstanding stock is in the hands of institutional investors.  It is interesting to note that of the three companies I looked at, only Mentor is currently paying a dividend to its investors.  The quarterly dividend is $0.05 per share.

For the third quarter of fiscal year 2013, Synopsys reported revenue of $482.9 million, compared to $443.7 million for the third quarter of fiscal year 2012, an increase of 8.8%.  The company reported revenue for the last complete fiscal year of $1.756 billion.  Revenue for the quarter ended July 31, 2013 were almost $483 million.  Stock price ranged from a low of 31.42 on January 7th to a high of $38.40 on October 22nd.  Its EPS is 1.41.  Of the three EDA companies Synopsys is the company with the largest percentage of shares in the hands of small investors.

Other Electronics Companies

For comparison I picked ARM that considers itself an IP company, Applied Materials a provider of semiconductors fabrication equipment, and TSMC, a foundry.

ARM is the largest pure play IP company.  For its 3rd quarter 2013 it reported revenue of $286.7 million.  For its 2012 fiscal year it reported revenue of $650 million.  ARM pays dividends to its stockholders, a practice very popular with European companies.  At the beginning of September it increased the amount of its dividend from $0.12 to $0.167 per share.  Its stock price ranged from a low of $34.46 on November 20, 2012 to a high of $51.78 on October 21st.  Its EPS is 0.53 and only about 28% of its shares are held by institutional investors, making the stock more volatile due to a higher volume of daily trades by small investors.

Applied Materials stock price ranged from a low of $10.36 on November 19, 2012 to a high of $18.07 on October 22.  The company has just reported its fiscal 2013 results.  It had revenue of $8.719 billion and it pays a $0.10 quarterly dividend.  The EPS is a negative 0.36 and the stock is approximately 86% owned by institutional investors.

Finally TSMC’s stock ranged from a low of $15.75 on August 21st to a high of $20.21 on May 8th.  Its EPS is 1.19.  For fiscal 2012 the company reported revenue of over $17.2 billion.  For the 3rd quarter of 2013 revenue were a little over $5.5 billion.  The company is in a competitive market that also requires very high capital expenditures to stay competitive.

Conclusion

few data points show that there is really no substantial difference in the performance of the stock of an EDA company versus that of other companies in the electronics industry.  Certainly both Applied Materials and TSMC have much larger revenue, but their business model is quite different from that of EDA vendors.  Revenue size is not a good indicator of stock performance anyway.  Profits are, as well as expected performance in the short term (one or tow years).  Stock market behavior no longer reflects long term expectations as investors are focused on immediate returns.  Actually judging by earnings per shares, EDA companies are above average in the ability to generate revenue from their capitalization.  The fact that institutional investors own a very large percentage of stocks of EDA companies shows that they are seen as reliable conservative investments.  In the last twelve months Mentor stock in fact performed as a growth stock.  If you had purchased it at its low price of $14.22 and sold at $23.62 you would have realized a 66% return on your investment.  Only a similar investment in Applied Materials would have returned a higher percentage.

Network on Chip Solution Is Gaining Market Shares

Thursday, November 14th, 2013

by Gabe Moretti, Contributing Editor

It is important to notice how much network on chip (NoC) architectures have established themselves as the preferred method of connectivity among IP blocks.  What I found lacking are tools and methods that help architects explore the chip topology in order to minimize the use of interconnect structures and to evaluate bus versus network tradeoffs.

Busses

Of course there are busses for SoC designs, most of which have been used in designs for years.  The most popular one is the AMBA bus first introduced in 1996.  Up to today there are five versions of the AMBA bus.  The last one introduced this year is the AMBA 5 CHI (Coherent Hub Interface) that offers a new high-speed transport layer and features aimed at reducing congestion.

Accellera offers the OCP bus developed by OCP-IP before it merged with Accellera.  It is an openly licensed protocol that allows the definition of cores ready for system integration that can be reused together with their respective test benches without rework.

The OpenCores open source hardware community offers the Wishbone bus.  I found it very difficult to find much information about Wishbone on the OpenCores.org website, with the exception of three references to implementations using this protocol.  Wishbone is not a complete bus definition, since it has no physical definitions.  It is a logic protocol described in terms of signals and their states and clock cycles.

Other bus definitions are proprietary.  Among them designers can find Quick Path from Intel, Hyper Transport from AMD, and IPBus from IDT.

IBM has defined and supports the Core Connect bus that is used in its Power Architecture products and is also used with Xilinx’s MicroBlaze cores.

Finally Altera uses its own Avalon bus for its Nios II products line.

Clearly the use of busses is still quite pervasive.  With the exception of proprietary busses, designers have the ability to choose both physical and protocol characteristics that are best suited for their design.

Network on Chip

There are two major vendors of NoC solutions: Arteris and Sonics.  Arteris is a ten year old company headquartered in Sunnyvale but with engineering center near Paris, France.  its technology is derived from the computer networking solutions that are modified to the requirements of SoC realizations.  Its products deal both with on-chip as well as with die-to-die and multi-chip connectivity.

Sonics was founded in 1996.  In addition to network on chip products it also offers memory subsystems, and tools for performance analysis and development tools for SoC realizations.  It offers six products in the NoC market covering many degrees of sophistication depending on designers’ requirements.  SonicsGN is its most sophisticated product.  It offers a high-performance network for the transportation of packetized data, utilizing routers as the fundamental switching elements.  On the other hand SonicsExpress can be used as a bridge between two clock domains with optional voltage domain isolation.  It supports AXI and OCP protocols and thus can be integrated in those bus environments.

After the panel discussion on IP Blocks Connectivity that covers mostly NoC topics, I spoke with Avi Behar, Product Marketing Director at Cadence.  Cadence had wanted to participate to the discussion but their request had come too late to include them in the panel.  But, information is important, and scheduling matters should not become an obstacle.  So I decided to publish their contribution in this article.

The first question I asked was: on chip connectivity uses area and power and also generates noise.  Have we addressed these issues sufficiently?

Avi:A common tendency among on-chip network designer is to over design. While it’s better to be on the safe side – under–designing will lead to the starvation of bandwidth hungry IPs and failure of latency critical IPs – over–designing has a cost in gate count and as a result in power consumption. In order to make the right design decisions, it is crucial that design engineer run cycle-accurate performance analysis simulations (by performance I primarily mean data bandwidth and transaction latency) with various configurations applied to their network. By changing settings like outstanding transactions, buffer depth, bus width, QoS settings and the switching architecture of the network and running the same, realistic traffic scenarios, designers can get to the configuration that would meet the performance requirements defined by the architects without resorting to over-design. This iterative process is time consuming and error prone, and this is where the just launched Cadence Interconnect Workbench (IWB) steps in. By combining the ability to generate a correct-by-construction test bench tuned for performance benchmarking (the RTL for the network is usually generated by tools provided by the network IP provider) with a powerful performance analysis GUI that allows side-by-side analysis of different RTL configurations, IWB greatly speeds this iterative process while mitigating the risks associated with manual creation of the required test benches.

What type of work do we need to do to be ready to have a common, if not standard, verification method for a network type of connectivity?

Avi: There are two aspects to the verification of networks-on-a-chip: functional verification and ‘performance verification’. Functional verification of these networks needs to be addressed at two levels: first make sure that all the ports connected to the network are compliant with the protocol (say AMBA3 AXI or AMBA4 ACE) that they are implementing, and secondly, verifying that the network correctly channels data between all the master and slave nodes connected to the network. As for performance verification, while the EDA industry has been focusing on serving the SoC architect community with virtual prototyping tools that utilize SoC models for early stage architectural exploration, building cycle accurate models of the on-chip network, capturing all the configuration options mentioned above is impractical. As the RTL for the connectivity network is usually available before the rest of the IP blocks, it is the best vehicle for performing cycle-accurate performance analysis. Cadence’s IWB, which as described in the previous answer, can generate a test bench tuned for running realistic traffic scenarios and capturing performance metrics. IWB can also generate a functional verification testbench which addresses the two aspects I mentioned earlier – protocol compliance at the port level and connectivity across the on-chip network.

What do you think should be the next step?

Avi: Many of our big SoC designing customers have dedicated network-on-a-chip verification teams who are struggling to get not only the functionality right, but ever more importantly, get the best performance while removing unnecessary logic. We expect this trend to intensify, and we at Cadence are looking forward to serving this market with the right methodologies and tools.

The contribution from Cadence reinforced the point of views expressed by the panelists.  It is clear that there are many options available to engineers to enable communication among IP blocks and among chips and dies.  What was not mentioned by anyone was the need to explore the topology of a die in view of developing the best possible interconnect architecture in terms of speed, reliability, and cost.

What Powers the IoT?

Wednesday, October 16th, 2013

By Stephan Ohr, Gartner

Powering the Internet of Things (IoT) is a special challenge, says Gartner analyst Stephan Ohr, especially for the wireless sensor nodes (WSNs) that must collect and report data on their environmental states (temperature, pressure, humidity, vibration and the like). While the majority of WSNs will harness nearby power sources and batteries, there will be as many as 10% of the sensor nodes that must be entirely self-powering. Often located in places where it is difficult or impossible to replace batteries, these remote sensor nodes must continue to function for 20 years or more.

Two research and development efforts focus on self-powering remote sensor nodes: One effort looks at energy harvesting devices, which gather power from ambient sources. The major types of energy harvesting devices include specialized solar cells, vibration and motion energy harvesters, and devices that take advantage of thermal gradients warm and cool surfaces. Research and development concentrated on reducing the size and cost of these devices, and making their energy gathering more efficient. But even in their current state of development, these devices could add up to a half-billion in revenues per year within the next five years.

The other R&D effort concentrates on low-power analog semiconductors which will elevate the milli-volt outputs of energy harvesting devices to the levels necessary for powering sensors, microcontrollers, and wireless transceivers. These devices include DC-DC boost converters, sensor signal conditioning amplifiers, and, in some cases, data converter ICs which transform the analog sensor signals to digital patterns the microcontroller can utilize. Broadline analog suppliers like Linear Technology Corp. and Analog Devices have added low-power ICs to their product portfolios. In addition to boosting low-level signals, they use very little power themselves. LTC’s low-power parts, for example, have a quiescent current rating of 1.3 micro-amps. Other companies liked Advanced Linear Devices (ALD) have been working on low-threshold electronics for years, and Texas Instruments has a lineup of specialized power management devices for WSN applications.

Ohr’s projections on energy harvesting will be part of his talk on “Powering the Internet of Things” at the Sainte Claire Hotel, San Jose, CA on October 24, 2013. (Admission is free, but advance registration is required The Internet of Things – A Disruption and an Evolution)

Source: Gartner Research (Oct 2013)

Stephan (“Steve”) Ohr is the Research Director for Analog ICs, Sensors and Power Management devices at Gartner, Inc., and focuses on markets that promise semiconductor revenue growth. His recent reports have explored custom power management ICs for smart phones and tablets, the impact of Apple’s choices on the MEMs sensor industry, and a competitive landscape for MEMs sensor suppliers.

Ohr’s engineering degree, a BS in Industrial Engineering, comes from the New Jersey Institute of Technology (the Newark College of Engineering) and his graduate degree, an MA in sociology, comes from Rutgers.

Mixed Signal and Microcontrollers Enable IoT

Wednesday, October 16th, 2013

By John Blyler

The Internet of Things (IoT) has become such a hot topic that many business and technical experts see it as a key enabler for the fourth industrial revolution – following the steam engine, the conveyor belt and the first phase of IT automation technology (McKinsey Report). Still, for all the hype, the IoT concept seems hard to define.

From a technical standpoint, the IoT refers to the information system that uses smart sensors and embedded systems that connect wired or wirelessly via Internet protocols. ARM defines IoT as, “a collection of smart, sensor-enabled physical objects, and the networks, servers and services that interact with them. It is a trend and not a single sector or market.” How do these interpretations relate to the real world?

“There are two ways in which the “things” in the IoT interact with the physical world around us,” explains Diya Soubra, CPU Product Manager for ARM’s Processor Division. “First they convert physical (analog) data into information and second they act in the physical world based on information. An example of the first way is a temperature sensor that reports temperature while an example of the second way is a door lock opens upon receiving a text message.”

For many in the chip design and embedded space, IoT seems like the latest iteration of the computer-communication convergence heralded from the last decade. But this time, a new element has been added to the mix, namely, sensor systems. This addition means that the role of analog and mixed signal system must now extend beyond RF and wireless devices to include smart sensors. This combination of analog mixed signal, RF-wireless and digital microcontrollers has increase the complexity and confusion among chip, board, package and end product semiconductor developers.

“Microcontrollers (MCUs) targeting IoT applications are becoming analog-intensive due to sensors, AD converters, RF, Power Management and other analog interfaces and modules that they integrate in addition to digital processor and memory,” says Mladen Nizic, Engineering Director for Mixed Signal Solutions at Cadence Design Systems. “Therefore, challenges and methodology are determined not by the processor, but by what is being integrated around it. This makes it difficult for digital designers to integrate such large amounts of analog. Often, analog or mixed-signal skills need to be in charge of SoC integration, or the digital and analog designer must work very closely to realize the system in silicon.”

The connected devices that make up the IoT must be able to communicate via the Internet. This means the addition of wired or wireless analog functionality to the sensors and devices. But a microcontroller is needed to convert the analog signal to digital and to run the Internet Protocol software stacks. This is why IoT requires a mix of digital (Internet) and analog (physical world) integration.

Team Players?

Just how difficult is it for designers – especially digital – to incorporate analog and mix signal functionality into their SoCs? Soubra puts it this way (see Figure 1): “In the market, these are two distinct disciplines. Analogue is much harder to design and has its set of custom tools. Digital is easier since it is simpler to design, and it has its own tools. In the past (prior to the emergence of IoT devices), Team A designed the digital part of the system while Team B designed the analog part separately. Then, these two distinct subsystems where combined and tested to see which one failed. Upon failure, both teams adjusted their designs and the process was repeated until the system worked as a whole. These different groups using different tools resulted in a lengthy, time consuming process.”

Contrast that approach with the current design cycle where the entire mixed signal designers (Teams A and B) work together from the start as one project using one tool and one team. All tool vendors have offerings to do this today. New tools allow viewing the digital and analog parts at various levels and allow mixed simulations. Every year, the tools become more sophisticated to handle ever more complex designs.

Figure 1: Concurrent, OA-based mixed-signal implementations. (Courtesy of Cadence)

Simulation and IP

Today, all of the major chip- and board-level EDA and IP tool vendors have modeling and simulation tools that support mixed signal designs directly (see Figure 2).

Figure 2: Block diagram of pressures-temperature control and simulation system. (Courtesy Cadence)

Verification of the growing analog mixed-signal portion of SoCs is leading to better behavioral models, which abstract the analog upward to the register transfer level (RTL). This improvement provides a more consistent handoff between the analog and digital boundaries. Another improvement is the use of real number models (RNMs), which enable the discrete time transformations needed for pure digital solver simulation of analog mixed-signal verification. This approach enables faster simulation speeds for event-driven real-time models – a benefit over behavioral models like Verilog-A.

AMS simulations are also using assertion techniques to improve verification – especially in interface testing. Another important trend is the use of statistical analysis to handle both the analog nature of mixed signals and the increasing number of operational modes. (See, “Moore’s Cycle, Fifth Horseman, Mixed Signals, and IP Stress”).

Figure: Cadence’s Mladen Nizic (background right) talk about mixed-signal technology with John Blyler. (Photo courtesy of Lani Wong)

For digital designers, there is a lot to learn in the integration of analog systems. However, the availability of ready-to-use analog IP does make it much easier than in the past. That’s one reason why the analog IP market has grown considerable in the last several years and will continue that trend. As reported earlier this year, the wireless chip market will be the leading growth segment for the semiconductor industry in 2013, predicts IHS iSuppli Semiconductor (“Semiconductor Growth Turns Wireless”).

The report states that original-equipment-manufacturer (OEM) spending on semiconductors for wireless applications will rise by 13.5% this year to reach a value of $69.6 billion – up from $62.3 billion in 2012.

The design and development of wireless and cellular chips – part of the IoT connectivity equation – reflects a continuing need for related semiconductor IP. All wireless devices and cell phones rely on RF and analog mixed-signal (AMS) integrated circuits to convert radio signals into digital data, which can be passed to a baseband processor for data processing. That’s why a “wireless” search on the Chipestimate.com website reveals list after list of IP companies providing MIPI controllers, ADCs, DACs, PHY and MAC cores, LNAs, PAs, mixers, PLLs, VCOs, audio/video codecs, Viterbi encoders/decoders, and more.

Real-World Examples

“Many traditional analog parts are adding more intelligence to the design and some of them use microcontrollers to do so,” observes Joseph Yiu, Embedded Technology Specialist at ARM. “One example is an SoC from Analog Device (ADuCM360) that contains a 24-bit data acquisition system with multichannel analog-to-digital converters (ADCs), an 32-bit ARM Cortex-M3 processor, and Flash/EE memory. Direct interfacing is provided to external sensors in both wired and battery-powered applications.”

But, as Soubra mentioned earlier, the second way in which the IoT interacts with the physical world is to act on information – in other words, through the use of digital-to-analog converters (DACs). An example of a chip that converts digital signals back to the physical analog world is SmartBond DA14580. This System-on-Chip (SoC) is used to connect keyboards, mice and remote controls wirelessly to tablets, laptops and smart TVs. It consists of Bluetooth subsystem, a 32 -bit ARM Cortex M0 microcontroller, antenna connection and GPIO interfaces.

Challenges Ahead

In addition to tools that simulated both analog, mixed signal and digital designs, perhaps the next most critical challenge in IoT hardware and software development is the lack of standards.

“The industry needs to converge on the standard(s) on communications for IoT applications to enable information flow among different type of devices,” stressed Wang, software will be the key to the flourish of IoT applications, as demonstrated by ARM’s recent acquisition of Sensinode.” A Finnish software company, Sensinode builds a variation of the Internet Protocols (IP) designed for IoT device connection. Specifically, the company develops to the 6LoWPAN standard, a compression format for IPv6 that is designed for low-power, low-bandwidth wireless links.

If IoT devices are to receive widespread adoption by consumers, then security of the data collected and acted upon by these devices must be robust. (Security will be covered in future articles).

Analog and digital integration, interface and communication standards, and system-level security have always been challenges faced by leading edge designers. The only thing that changes is the increasing complexity of the designs. With the dawning of the IoT, that complexity will spread from every physical world sensor node to every cloud-based server receiving data from or transmitting to that node. Perhaps this complexity spreading will ultimately be the biggest challenge faced by today’s intrepid designers.

WEEK IN REVIEW: October 10 2013

Friday, October 11th, 2013

Imagination Technologies and Rightware collaborate; Applied Materials’ tax affairs; Cadence prepare for next-gen comms with IP; AWR at European Microwave Week and Tensilica’s DSP for in-car sound.

Imagination Technologies and Rightware have signed a multi-year agreement whereby the companies will collaborate to develop next-generation mobile benchmarks. It hopes to deliver “visually stunning” user experiences through the software company’s Kanzi-based user interfaces on Imaginations PowerVR GPUs (graphics processing units) and MIPS CPUs (central processing units).

Tetsuro Higashi, Chairman, President and CEO of Tokyo Electron and Gary Dickerson, President and CEO of Applied Materials

Applied Materials is still in the headlines following its merger with Tokyo Electron, but for a different reason – tax. By reincorporating the company in the Netherlands, its tax bill could be reduced from 22% to 17%,
saving the company $100million a year.

Cadence Design Systems has introduced a suite of fast, low power analog IP (intellectual property) that delivers as much as x10 faster conversion rate than anything else available, it claims, ready for the next-generation of high speed, wired and wireless communications. The Data Converter IP, ADC (analog to digital conversion) IP and DAC (digital to analog conversion) IP can be integrated into 28nm process nodes and in readiness for WiGig (802.11ad) LTE (long term evolution) and LTE Advanced protocols.

Breaking new ground, Cadence announced that it is the first IP core supplier to offer DTS Neutral Surround support to the next generation of car audio processors with the Tensilica HiFi Audio/Voice DSP.

Nuremberg – European Microwave saw AWR announce AWR Connected for AMPSA, a synthesis through simulation flow for amplifier design. High-frequency circuit designers can leverage the AMPSA synthesis tool, using Impedance-Matching Wizard (IMW) and Amplifier Design Wizard (ADW) environments.

Blog Review October 10 2013

Thursday, October 10th, 2013

By Caroline Hayes

At the TSMC Open Innovation Platform (TSMC OIP) Ecosystem Forum, Richard Goering hears that 16mm FinFET design and 3D ICs are moving closer to volume production. Dr Cliff Hou, vice president, R&D, TSMC warned that although EDA tools and flows have been qualified, foundation IP has been validated, and interface IP is under development, one tool does not guarantee success, calling for a “more rigorous validation methodology”.

Steve Favre was also at TSMC OIP, discussing 450nm wafers. He wondered why EUV (extreme ultra violet) patterning has become a gating item for the move to 450nm, and how are these two related? Money, as usual, is the answer, It would cost billions of dollars to build a 450nm wafer fab and billions to move to EUV – why pay twice?

Lakshmi Mandyam from ARM’s smart connected community reflects on her journey from the power-hungry, boot-up slow laptop to a touch-sensor, multi-screen tablet. She ends by marking the anniversary of her laptop-free life. Maybe she should start an LA (Laptop Anonymous) support group?

Chip Design’s John Byler cringes with embarrassment while following up a nanotechtechnology lead at IEF in Dublin, Ireland. The lapse of government funding is proclaimed on the National Institute of Standards and Technology, accounting for the website’s and its affiliated websites’ closure. He turns to the French for further research, over a croissant – naturellement.

Pity Brian Fuller, caught off-guard by the usually genial  analyst Gary Smith in an interview for Unhinged.  Smith urged EDA vendors to be bolder, pooh-poohed the idea of industry consolidation, held forth on the power of the press and then complimented John Cooley. What is the world coming to?

Michael Posner sounds the alarm that “My RTL is an alien”, neatly timed to coincide with a white paper by Synopsys which details ways to accelerate FPGA (field programmable gate array)-based prototyping. With over 70% of today’s ASICs and systems-on-chips (SoCs) being prototyped in an FPGA, designers are looking for ways to ease the creation of FPGA-based prototypes directly from the ASIC design source files.

Gabe Moretti is feeling nostalgic in preparation for the Back to the Future Dinner organized by the EDA Consortium at the Computer Museum, Mountain View, California, this month.

In this blog he remembers the early days of EDA, when it was called CAD (computer aided design) and ruylith cut by hand. Those were the days!

ESL Market Potential

Wednesday, October 9th, 2013

By Gabe Moretti

In preparing for my first panel discussion on ESL (see http://bit.ly/1f65L8x) I spoke with Gary Smith to get his views on this segment of the EDA market.  As usual Gary was very helpful, so if I misunderstood it is completely my fault.  First the bad news: there are still no standards systems architects can rely upon.  This means that during product implementation the characteristics of the architectural design are derived in a subjective manner.  Designers implement what they understand, not necessarily what is intended.

This lack of standards could also be good news, since our industry has been quite attentive to such requirements, and certainly has the proven expertise to develop effective standards.  The experience gained by architects and designers can be used by standards developers.  We now not only understand what is required but have a better idea of what might work and what does not work.

Of course Accellera has developed standards that are useful in system level development, SystemVerilog, VMM, UVM, and IP-XACT.  But, and this is Gary’s point, they address development and verification, not architectural design.  Although there have been attempts to develop an architecture description language, those initiatives are still by en large academic exercises.

On the positive note, ESL is growing, may be not as aggressively as once thought from a financial point of view, but its methods are based on solid and proven grounds and offer much room for expansion.  The revenue hockey stick phenomenon predicted a couple of years ago did not materialize.  But revenue from ESL tools is steadily growing and shows a definite positive trend.  Platform based design, according to Gary is now an established methodology and it has made possible the implementation of very complex systems while cutting development costs, some time up to 44%.  Platform based design requires both certified IP blocks and verified firmware.  Accellera is dedicating significant energy to IP issues and its work is well accepted by IP vendors.

During the discussion on ESL the panelists were very focused on the software side of the problem when it comes to verification.  Virtual prototyping and system emulation offer significant growth opportunities in EDA.  Jon MacDonald of Mentor observed that “there is a strong need for each tool to have the ability to interact with representations from other design spaces.  Engineering disciplines have been compartmentalized for a long time to address significant issues in system complexity.  Each discipline needs development tools focused on reducing the complexity of that domain.”

Gary Smith also reinforced the observation made by Frank Schrrmeister of Cadence:

“Fact is that the core customers of EDA – the semiconductor houses – have taken on over the last two decades huge amounts of additional expertise as part of their developments. Where a set of drivers and a partnership with operating system vendors may have been enough 15 years ago, today the same vendors have to provide chips with reference ports of Android, Linux, Chrome OS and Windows Mobile just to win the socket. We all have to learn and deal with the aspects of those adjacent markets as they increasingly simply become a “must Deal with” for existing EDA customers.”

Gary pointed out that the role of the semiconductors companies has changed.  The foundries have taken on an increasing role in providing IP products constituting entire subsystems that include both hardware and software components.  This change is not an overt decision on the part of foundries to change their business model.  It is, instead, the natural result of process requirements.  Processes below 45 nm require cells that are very foundry specific and have indigenous software drivers, often to address power consumption requirements.

What came out of the panel is that the electronics part of a large heterogeneous system still plays the most important role.  The electronics subsystem is fundamental to the construction of the internet of things, certainly the most promising architecture of the near and more distant future.  The strategic item in designing a heterogeneous system is the communication of information from the non-electronic subsystem to the computational part.  This is the area that offers significant growth potential for EDA companies, together with the expansion in embedded software development and verification.

During the panel discussion Bill Neifert of Carbon observed that “like it or not, software can have a significant impact on the behavior of the system. Far too often, hardware decisions are made with no real data from the software team and software teams are forced to live with decisions the hardware team made without their input.”

And Brett Cline, of Forte added: “Integrating non-electronic components could help more accurately model the system prior to construction with obvious benefits. There are plenty of tools and technologies available to help model the non-electronic portions of a system. At some point, the tool flow becomes extremely complex and modeling the entire system becomes prohibitively expensive or difficult. Should EDA companies choose to tackle this problem, the getting the tool flow and integration will be paramount to being successful.”

Virtual prototyping needs to expand its role.  From an almost exclusively software verification tool it must grow to properly support “what-if” analysis to efficiently allow architects to trade-off hardware/software combinations in order to identify the optimum architecture.  This is particularly important when dealing with power consumption issues.

Of course, without cost and time constrints, architects could experiment with a number of different architectural solutions using present tools.  But such scenario is not practical even in the academic world, let alone in the commercial one.  The creation of algorithms and computational architectures that allow modeling of complex systems in a practical manner is a challenge as well as an opportunity for EDA.

Electronics companies have been developing embedded software, called firmware, at least since the introduction of the programmable calculator in 1970.  As the IP blocks have grown to become real subsystems, they incorporate firmware.  Thus companies like ARM and NVIDIA are selling IP products that contains significant amount of firmware.  The certification of these subsystems for each process node from the various foundries is becoming a necessary part of their commercialization.

Finally we must realize that expanding the role of ESL tools within a design will be critical in lowering the cost of backend work.  Optimization of the layout of a chip can be simplified by a clean architectural design that avoids many of the problems inherent with an inefficient and crowed layout.

WEEK IN REVIEW: October 3 2013

Friday, October 4th, 2013

Caroline Hayes

Fujifilm and imec have developed photoresist technology for organic semiconductors that enables submicron patterning on large substrates, without damage to the organic materials. It could prove to be a cost-effective alternative to current methods, i.e. shadow masking and inkjet printing, which have not proved suitable for high resolution patterns on large substrates. Photolithography is successfully used in patterning silicon semiconductors, but the photoresist dissolves the organic semiconductor material during processing. OPDs (organic photo detectors) were produced at sizes down to 200µm x 200µm without degradation. OLED (organic light emitting diodes) were also produced, at a pitch of 20µm and were found to emit uniform light.

Synopsys released a new TLM (transaction level model) subsystem flow and eclipse IDE (integrated development environment) integration speed Virtualizer Development Kit. The Virtualizer 13.06 enables and disables components of the design to allow users to optimize simulation performance during software debug.

Celebration for Cadence Design Systems as it accepted not one but three Partner of the Year awards from TSMC at this month’s Open Innovation Platform forum. They were for the Analog/Mixed-Signal IP, the 16nm FinFET Design Infrastructure, and Joint Delivery of 3D-IC Design Solution categories.

NAND flash devices are looking beyond conventional semiconductor manufacturing techniques, reports IHS. Nearly two thirds (65.2%) of all NAND memory chips shipped worldwide by 2017, will be produced using 3D processes, according to a Flash Dynamics brief. At present, it is less than 1%. Time is running out for planar semiconductor technology capacity, leaving 3D manufacturing the answer to building higher densities NAND products.

Results from the RF and Analog/Mixed-Signal (AMS) IC Survey

Wednesday, October 2nd, 2013

A summary of the results of a survey for developers of products in RF and analog/mixed-signal (AMS) ICs.

This summary details the results of a survey for developers of products in RF and analog/mixed-signal (AMS) ICs. A total of 129 designers responded to this survey. Survey questions focused on job area, company information, end-user application markets, product development types, programming languages, tool vendors, foundries, processes and other areas.

Key Findings

  • More respondents are using Cadence’s EDA tools for RFIC designs. In order, respondents also listed Agilent EESof, Mentor, Ansys/Ansoft, Rhode & Schwartz and Synopsys.
  • More respondents are using Cadence’s EDA tool for AMS IC design. Agilent EESof, Mentor, Aniritsu, Synopsys and Ansys/Ansoft were behind Cadence.
  • Respondents had the most expertise with C/C++. Regarding expertise with programming languages, C/C++ had the highest rating, followed in order by Verilog, Matlab-RF, Matlab-Simulink, Verilog-AMS, VHDL, SystemVerilog, VHDL-AMS and SystemC.
  • For RF design-simulation-verification tools, more respondents in order listed that they use Spice, Verilog, Verilog-AMS, VHDL and Matlab/RF-Simulink. For planned projects, more respondents in order listed SystemC, VHDL-AMS, SystemVerilog, C/C++ and Matlab/RF-Simulink.
  • Regarding the foundries used for RF and/or MMICs, most respondents in order listed TSMC, IBM, TowerJazz, GlobalFoundries, RFMD and UMC.
  • Silicon-based technology is predominately used for current RF/AMS designs. GaAs and SiGe are also widely used. But for future designs, GaAs will lose ground; GaN will see wider adoption.
  • RF and analog/mixed-signal ICs still use fewer transistors than their digital counterparts. Some 30% of respondents are developing designs of less than 1,000 transistors. Only 11% are doing designs of more than 1 million transistors.
  • Digital pre-distortion is still the favorite technique to improve the efficiency of a discrete power amp. Envelope tracking has received a lot of attention in the media. But surprisingly, envelope tracking ranks low in terms of priorities for power amp development.

Implications

  • Cadence continues to dominate the RFIC/AMS EDA environment. Virtuoso remains a favorite among designers. RF/AMS designers will continue to have other EDA tool choices as well.
  • The large foundries, namely TSMC and IBM, will continue to have a solid position in RF/AMS. But the specialty foundries will continue to make inroads. Altis, Dongbu, Magnachip, TowerJazz, Vanguard and others are expanding in various RF/AMS fronts.
  • There is room for new foundry players in RF/AMS. GlobalFoundries and Altis are finding new customers in RF, RF SOI and RF CMOS.
  • The traditional GaAs foundries—TriQuint, RFMD, Win Semi and others—are under pressure in certain segments. The power amp will remain a GaAs-based device, but other RF components are moving to RF SOI, SiGe and other processes.

Detailed Summary

  • Job Function Area-Part 1: A large percentage of respondents are involved in the development of RF and/or AMS ICs. More respondents are currently involved in the development of RF and/or AMS ICs (55%). A smaller percentage said they were involved in the last two years (13%). A significant portion are not are involved in the development of RF or AMS ICs (32%).
  • Job Function Area-Part 2: Respondents listed one or a combination of functions. More respondents listed analog/digital designer (30%), followed in order by engineering management (22%), corporate management (12%) and system architect (10%). The remaining respondents listed analog/digital verification, FPGA designer/verification, software, test, student, RF engineer, among others.
  • Company Information: Respondents listed one or a combination of industries. More respondents listed a university (23%), followed in order by systems integrator (18%), design services (14%), fabless semiconductor (13%) and semiconductor manufacturer (10%). The category “other” represented a significant group (13%). The remaining respondents work for companies involved in ASICs, ASSPs, FPGAs, software and IP.
  • Company Revenue (Annual): More respondents listed less than $25 million (27%), followed in order by $100 million to $999 million (24%) and $1 billion and above (22%). Others listed $25 million to $99 million (8%). Some 19% of respondents did not know.
  • Location: More respondents listed North America (60%), followed in order by Europe (21%) and Asia-Pacific (10%). Other respondents listed Africa, China, Japan, Middle East and South America.
  • Primary End-User Application for Respondent’s ASIC/ASSP/SoC design: More respondents listed communications (67%), followed in order by industrial (28%), consumer/multimedia (24%), computer (21%), medical (15%) and automotive (12%).
  • Primary End Market for Respondent’s Design. For wired communications, more respondents listed networking (80%), followed by backhaul (20%). For wireless communications, more respondents listed handsets (32%) and basestations (32%), followed in order by networking, backhaul, metro area networks and telephony/VoIP.
  • Primary End Market If Design Is Targeted for Consumer Segment. More respondents listed smartphones (34%), followed in order by tablets (24%), displays (18%), video (13%) and audio (11%).

Programming Languages Used With RF/AMS Design Tools:

  • Respondents had the most expertise with C and C++. Regarding expertise with programming languages, C/C++ had an overall rating of 2.47 in the survey, followed by in order by Verilog (2.32), Matlab-RF (2.27), Matlab-Simulink (2.17), Verilog-AMS (2.03), VHDL (1.99), SystemVerilog (1.84), VHDL-AMS (1.70) and SystemC (1.68).
  • Respondents said they had “professional expertise” (19%) with C/C++. Respondents were “competent” (27%) or were “somewhat experienced” (37%) with C/C++. Some 17% said they had “no experience” with C/C++.
  • Respondents said they had “professional expertise” with Verilog-AMS. (13%). Respondents were “competent” (15%) and “somewhat experienced” (35%) with Verilog-AMS. Some 38% said they had “no experience” with Verilog-AMS.
  • Respondents said they had “professional expertise” with Verilog (12%), or were “competent” (30%) or were “somewhat experienced” (36%). Some 22% said they had “no experience” with Verilog.
  • Respondents said they had “professional expertise” with Matlab-RF (10%), or were “competent” (27%) or “somewhat experienced” (42%). Some 21% said they had “no experience” with the technology.
  • Respondents also had “professional experience” with VHDL (10%), SystemVerilog (9%), SystemC (7%), Matlab-Simulink (6%) and VHDL-AMS (3%).
  • Respondents had ‘’no experience” with SystemC (55%), VHDL-AMS (51%), SystemVerilog (49%), Verilog-AMS (38%), VHDL (36%), Matlab-Simulink (26%), Verilog (22%), Matlab-RF (21%) and C/C++ (17%).

Types of Programming Languages and RF Design-Simulation-Verification Tools Used

  • For current projects, more respondents listed Spice (85%), Verilog (85%), Verilog-AMS (79%), VHDL (76%), Matlab/RF-Simulink (71%), C/C++ (64%), SystemVerilog (56%), VHDL-AMS (44%) and SystemC (21%).
  • For planned projects, more respondents listed SystemC (79%), VHDL-AMS (56%), SystemVerilog (44%), C/C++ (36%), Matlab/RF-Simulink (29%), VHDL (24%), Verilog-AMS (21%), Verilog (15%) and Spice (15%).

Which Tool Vendors Are Used in RFIC Development

  • More respondents listed Cadence (60), followed in order by Agilent EESof (43), Mentor (38), Ansys/Ansoft (29), Rhode & Schwartz (26) and Synopsys (25). Others listed were Aniritsu, AWR, Berkeley Design, CST, Dolphin, EMSS, Helic, Hittite, Remcon, Silvaco, Sonnet and Tanner.
  • The respondents for Cadence primarily use the company’s tools for RF design (68%), simulation (73%), layout (67%) and verification (43%). The company’s tools were also used for EM analysis (27%) and test (22%).
  • The respondents for Agilent EESof primarily use the company’s tools for RF design (54%) and simulation (65%). The company’s tools were also used for EM analysis, layout, verification and test.
  • The respondents for Mentor Graphics primarily use the company’s tools for verification (55%), layout (37%) and design (34%). Meanwhile, the respondents for Rhode & Schwartz primarily use the company’s tools for test (69%). The respondents for Synopsys primarily use the company’s tools for design (40%), simulation (60%) and verification (48%).

Which Tool Vendors Are Used in AMS IC Development

  • More respondents listed Cadence (48), followed in order by Agilent EESof (26), Mentor (22), Aniritsu (19), Synopsys (18) and Ansys/Ansoft (15). Others listed were AWR, Berkeley Design, CST, Dolphin, EMSS, Helic, Hittite, Remcon, Rohde & Schwarz, Silvaco, Sonnet and Tanner.
  • The respondents for Cadence primarily use the company’s tools for AMS design (79%), simulation (71%), layout (71%) and verification (48%). The company’s tools were also used for EM analysis and test.
  • The respondents for Agilent EESof primarily use the company’s tools for design (42%), simulation (69%) and EM analysis (54%).
  • The respondents for Mentor Graphics primarily use the company’s tools for design (50%), simulation (46%) and verification (55%). The respondents for Aniritsu primarily use the company’s tools for test (47%). The respondents for Synopsys primarily use the company’s tools for design (61%) and simulation (67%).

Areas of Improvement for Verification and Methodologies

  • Respondents had a mix of comments.

Foundry and Processes

  • Foundry Used for RFICs and/or MMICs: More respondents listed TSMC (32), followed in order by IBM (27), TowerJazz (19), GlobalFoundries (17), RFMD (13) and UMC (13). The next group was Win Semi (12), ST (11), TriQuint (11) and GCS (10). Other respondents listed Altis, Cree, IHP, LFoundry, OMMIC, SMIC, UMS and XFab.
  • Of the respondents for TSMC, 87% use TSMC for RF foundry work and 55% for MMICs. Of the respondents for IBM, 81% use IBM for RF foundry work and 41% for MMICs. Of the respondents for TowerJazz, 84% use TowerJazz for RF foundry work and 42% for MMICs. Of the respondents for GlobalFoundries, 76% use GF for RF foundry work and 41% for MMICs.
  • Complexity of Respondent’s Designs (Transistor Count): More respondents listed less than 1,000 transistors (30%), followed in order by 10,000-99,000 transistors (14%) and 100,000-999,000 transistors (14%). Respondents also listed 1,000-4,900 transistors (11%), greater than 1 million transistors (11%) and 5,000-9,900 transistors (10%).
  • Process Technology Types: For current designs, more respondents listed silicon (66%), followed in order by GaAs (32%), SiGe (27%), GaN (23%) and InP (10%). For future designs, more respondents listed silicon (66%), followed in order by SiGe (31%), GaN (28%), GaAs (16%) and InP (13%).

Technology Selections:

  • Which Baseband Processor Does Design Interface With: More respondents listed TI (35%), ADI (22%) and Tensilica/Cadence (18%). Respondents also list other (26%).
  • Technique Used To Improve Discrete Power Amplifier Efficiency: In terms of priorities, more respondents listed digital pre-distortion (38%), followed in order by linearization (27%), envelop tracking (14%) and crest factor reduction (10%). In terms of priorities, the technique that showed the lowest ranking was envelop tracking (37%), crest factor reduction (21%) and linearization (14%).

Test and Measurement

  • Importance of Test and Measurement: More respondents listed very important (34%), followed in order by important (24%), extremely important (20%), somewhat important (19%) and unimportant (3%).

lapedus_markMark LaPedus has covered the semiconductor industry since 1986, including five years in Asia when he was based in Taiwan. He has held senior editorial positions at Electronic News, EBN and Silicon Strategies. In Asia, he was a contributing writer for Byte Magazine. Most recently, he worked as the semiconductor editor at EE Times.

Next Page »