By Caroline Hayes
Today, lament many designers, there is no more bolting together blocks of pre-verified analog or digital circuitry mixed-signal SoC testing. As process nodes reduce, the level of chip integration grows, involving more analog circuitry and larger blocks of mixed-signal IP.
As analog IP (Intellectual Property) not only grows more complex but contains more digital control logic, the balancing act of SoC (System on Chip) and system level verification is being pursued via different routes, all with the objective of reducing development time and costs.
The increase in size and complexity means that the ‘old’ and trusted method of bolting on black boxes of what was presumed (hoped) to be pre-verified analog and digital blocks is no longer seen as good practice.
It has been estimated that around 60% of all SoC respins at 45nm and below are due to mixed-signal errors; most commonly inverter or disconnected signals. Each re-spin is at a cost of millions of dollars and adds a minimum of eight weeks to the development time. Considering that the main drivers of mixed-signal SoCs are semiconductor designs used in consumer-orientated mobile devices or automotive applications, both of these cost and time penalties are unacceptably high.
At the International Test Conference (ITC) 2013, both Synopsys and Cadence Design Systems showcased technologies to increase the speed of large SoC test.
Cadence identified Giga-gate SoC challenges at advanced technology nodes and also showcased safety requirements for automotive in particular, with logic Built-In Self Test (BIST) and test coverage augmentation techniques. It also showcased advances in distributed Automatic Test Pattern Generation (ATPG) and core level test pattern migration for large SoCs. Synopsys also introduced two test systems, both claimed to reduce SoC test times.
Bassilios Petrakis, product marketing director, Cadence Design, explained that the turn of this century has seen a focus on test compression. “The 2000 – 2010 time frame was when test compression began to dramatically reduce the time and data volume associated with logic testing as well as the rise of automation for reducing switching power during test,” he said. Most recently, there have been increasing levels of compression and core-based hierarchical testing, he noted. Hierarchical verification is becoming essential to support the different levels of abstraction, different simulation engines and different modelling languages, used in complex SoCs.
Petrakis sees hierarchical test as becoming more important in the mixed-signal design landscape. “Hierarchical test is important to reduce the size of circuit ATPG needs to process and, possibly, to improve test compression results,” he said. This will continue as more chip design include multiple copies of cores, such as central processor unit (CPU), graphics processing unit (GPU) and input/output (I/O). “We expect to see an increasing use of partially bad chips, with one or two bad cores that can still be sold for reduced functionality”. He points out that this is similar to the model used today for Random Access Memory (RAM) “but now, with IEEE 1500-based core isolation and multiple, identical cores, we can begin to see this done for logic as well”.
For Petrakis, one strategy for mixed-signal SoC test, where there are often very few pins available through which to test logic, is to combine reduced pin testing and compression techniques, allowing devices to be tested using very few pins.
Mentor Graphics first proposed a mixture of stimulus and analysis by proprietary and third party IP blocks as well as Automatic Test Equipment (ATE) in a digital infrastructure in 2011, at the European Test Symposium. According to Steve Pateras, marketing director, Mentor Graphics, the approach builds on P1687 and include P1687-like serial paths for sampled analog signals that provide almost unlimited voltage and time resolution at an unlimited number of circuit nodes. Building on this, at this year’s symposium, the company described a new approach to analog defect simulation, important for verifying a mixed-signal test’s quality, and to determine if a new test or BIST could replace a more costly, silicon-proven test.
One of the main challenges is to maintain test efficiency as design size and complexity grow. Pateras says this calls for a “divide and conquer approach”, with techniques such as wrapping cores with dedicated scan chains for isolation; generating patterns for each core in isolation, and the ability to merge and retarget core level patterns to the top level pins, to keep test costs in check.
With the increase in test pattern volumes, so the number of defect types that need to be addressed, increases. He argues that increasing compression levels is one direct way to keep test pattern volumes, and test time, manageable. There are several techniques being developed to improve compression levels. One, singled out by Pateras is Scan Bandwidth Management. “[This] involves techniques for improving the bandwidth between the ATE and the scan resources of the various blocks within a design,” he explained.
He also agrees that BIST is a useful tool to meet the new challenges of mixed-signal SoC test. “Adding test resources directly on chip enables greater test efficiency through increased test application bandwidth and test parallelization,” he said. “BIST adoption is evolving beyond being just for embedded memories to other major parts of SoC, including logic and mixed-signal blocks.”
Sandeep Kaushik, senior marketing manager, embedded test and repair, Synopsys summed up the challenges faced by today’s engineers who rely on both internally developed and third party IP core. “Traditional, ad hoc methods for adding the design for test logic and generating test patterns for each block and then combining and sequencing all these patterns at the SoC level are time consuming and error-prone. A more automated approach is need for SoC test integration that accommodates a wider variety of cores, more cores per design and fewer test pins per core.”
Customers expect IP to contain BIST for running analog loopback tests in standard, mixed signal interfaces, such as PCIe, USB 3.0, HDMI (High Definition Multimedia Interface) and other SERDES (serializer/deserializer) interfaces. Viewing analog waveforms as part of the overall test program enables the analog output to be trimmed, based on the waveforms.
At ITC 2013, the company launched the DesignWare Star Hierarchical System to leverage IP and ore level test to test the entire SoC, claimed to reduce test integration time to a matter of days, and to reduce design and test costs. It interfaces to the standard mixed-signal interfaces using the IEEE 1500 standard and co-ordinates the IP test, and also allows the engineer to trim waveforms via on-chip fuses.
Kaushik explained its role in custom mixed-signal blocks, where designers traditionally create the test program: “[It] makes use of IEEE 1500 interfaces and infrastructure to control and observe the digital signals of the blocks. Designers than have direct access to the digital signals and can focus primarily on stimulating and observing the analog signals, saving test integration time and effort.”
The company’s theme for ITC 2013 was “Higher quality, lower cost, faster” and its second launch at ITC was DFTMAX Ultra, which uses synthesis-based technology for higher scan compress and faster test frequencies, using fewer test pins.
Today, the mixed-signal blocks used in designs are on the scale of entire chips in previous generations, so visibility into all signals is vital and it is not adequate to assume that blocks are pre-verified, even though this adds to the development period.
Finally a warning was sounded by Chris Allsup, marketing manager, high-level synthesis and test products, Synopsys. He fears that potentially higher DPPM (defective parts per million) and slower yield ramp will occur, due to subtle defects associated with advanced manufacturing processes. “At 20nm and below,” he said “not only are defect densities higher, there are also significant on-chip process variations that affect transistor sizes, transistor threshold voltages and wire resistances.”
The balancing act has to be that as the shrinking of process technologies; the increased use of complex chips in cost and time sensitive applications continues – seemingly unabated – it is matched by EDA companies countering with cost and time efficient methods and technologies.