By Ed Sperling
Mentor’s Mike Jensen compares muscle memory—the human kind—to mechatronic system modeling and simulation. Gatorade anyone?

Synopsys’ Eric Huang examines one way to speed up gaming platforms—don’t compress the video. But you need bigger pipes and faster I/O to make that work, which is why USB 3.0 is showing up in the newest consoles.

Cadence’s Richard Goering interviews colleague Anirudh Devgan about the company’s new signoff strategy. Signoff is the point at which you have sufficient confidence in a design to release it to the market, staking your team’s reputation on it. You’d better have the right tools to get there.

Real Intent’s Shiva Borzin digs deep into Verilog’s parameter statement and how that can be redefined as a defparam statement. If you work in this segment, grab a knife and fork.

Semico Research’s Rich Wawrzyniak looks at the maturation of the IP market and what implications that has. It doesn’t mean a slowdown in innovation, but there will be fewer players, presumably with better business practices because they’re the survivors.

Mentor’s Brad Dixon digs down into software behavior in a design to improve performance—and subsequently energy efficiency. These kinds of tools are long overdue.

Synopsys’ Karen Bartleson talks with San Francisco residents about what’s needed to actually work in the technology field. The answer may vary by process node.

Cadence’s Jack Erickson is promoting an unusual discussion format at DAC—one in which Cadence and Forte are presenting together on deploying SystemC high-level synthesis. Consider this a team of rivals. This may be the only DAC presentation with a metal detector at the door.

IHS iSuppli’s Sweta Dash questions whether ultra-high definition TVs can avoid the fate of 3D TVs. Answer: Maybe, but don’t hold your breath for UHD content.

Synopsys’ Mick Posner digs into the ROI equation for FPGA boards that are commercially purchased or ones that are re-used from one project to the next.

Cadence’s Team Specman has some useful hints if you work with this tool, this one involving enhancements to simplify multi-instance modeling.

Mentor Graphics teamed up with Tezzaron Semiconductor to automate the verification of die-to-die interfaces in 2.5D and 3D stacked die. The companies also plan to extend that collaboration into the silicon photonics market. Interest in stacked die is growing, in part because of the continued delays in EUV lithography and the cost implications of multi-patterning.

Interest in silicon photonics is growing, as well, due to the RC effects of shrinking wires and interconnects. Mentor teamed up with OpSIS Foundries and Lumerical Solutions on PDK development for a silicon photonics process.

Cadence rolled out a timing signoff solution that updates and dramatically improves the performance as well as the competitiveness of the company’s offering in this area. The new technology is now parsed so it can take advantage of massively parallel hardware configurations using hundreds of processors. It also includes a new path-based analysis engine that significantly reduces pessimism in design—one of the major causes of extra margin—and it adds multi-corner, multi-mode analysis and physically aware timing closure. Signoff is becoming a huge problem in complex SoCs these days. Expect to see more announcements in this area. In a related move, TSMC certified Cadence’s new signoff solution for 20nm designs.

On the earnings side, Cadence uncorked its Q1 financial results with a toast. The company reported revenue of $354 million, compared with $316 million in 2012. Net income was $79 million, compared with $31 million in the same period in 2012. Cadence completed its acquisition of Tensilica. The net cost was about $326 million. The Tensilica team will report to Martin Lund, senior vice president of R&D for Cadence’s SoC Realization Group.

Celebrations continued at Synopsys, as well, which posted strong financial results for its fiscal Q2. Revenue increased 15% to $499.3 million, compared with $432.6 million in the same period in 2012. Net income was $68.7 million, compared with $21.0 million in 2012. Design complexity is proving to be very good for EDA vendors, and Synopsys remains the largest of the Big Three.

Real Intent also showed off some strong growth numbers. The company’s revenue grew more than 70% in the first half of fiscal 2013 compared with the previous six months, and is on track to achieve more than 100% growth by the end of this year. Real Intent also grew its customer list by more than 20%.

Falling commodity prices have changed the tenor of negotiations with suppliers, according to IHS iSuppli, and knowledge of the trend has given negotiators the upper hand. It probably won’t show up in end device pricing, but it will show up in their margins.

Jasper Design Automation introduced a power-aware version of its formal verification tool, adding optimization for multiple voltage and power-management domains. The tool now can create an internal power-aware formal model based upon power partitioning specs.

Real Intent teamed up with DeFacTo Technologies to deliver an RTL signoff flow for both clock-domain crossing and design for test, which the companies say speeds up the signoff process. There has been a lot of attention focused on the growing signoff problem over the past few months.

Achronix taped out a finFET-based FPGA using Synopsys’ physical design and verification. FinFETs should greatly improve the power/performance characteristics of FPGAs, which is why there has been a big rush by FPGA vendors to the latest node.

South Korea’s MagnaChip adopted Mentor Graphics’ process design kit automation process and custom IC platform. MagnaChip makes AMS semiconductor platforms. The company also won a deal with CNH, which makes agricultural and construction equipment for its wiring and harness design software tools, which are becoming more popular as off-road vehicles add more sophisticated electronics.

Yamaha was able to reduce power consumption for its mobile consumer chips by 10% using Cadence’s characterization tools. The improvements are the result of automating the functional descriptions of cells and the specification of worst-case conditions.

Open-Silicon celebrated its 10th anniversary. The company has shipped more than 78 million chips over that period.

People may be overweight, but at least they’re putting their money where their mouths are—so to speak. Shipments of sports and fitness monitors will total 250 million units between 2013 and 2017, according to IHS iSuppli.

Android and iOS accounted for 92.3% of all smartphone OSes shipped in Q1, according to IDC, and Android’s share accounted for 75% compared with iOS’s 17.3%. Moreover, while shipments of iOS increased from Q1 2012 to the same period in 2013, its market share dropped nearly 6%. Android’s shot up nearly 17%.

By Ed Sperling
Mentor’s Colin Walls looks around at where engineers can learn about embedded software. It seems none of the education is complete enough, so they have to cobble it together from a variety of sources. Sounds like good job security for those with a bank of expertise.

Cadence’s Richard Goering interviews a dual power-format user from Maxim about the convergence of CPF with the new IEEE 1801/UPF standard. There’s still room for improvement, but the new standard is a long-awaited giant step in the right direction.

Mentor’s Robin Bornoff questions the value of heatsinks as a magical way of cooling electronics. Bottom line: The heat still has to go somewhere—even after it’s dispersed by the heatsink.

Real Intent’s Prakash Narain kicks off a staff-written blog about what went on at DVcon ’13 and what trends they spotted. There’s a long list here, so pour a large cup of coffee.

IHS iSuppli’s Richard Dixon sees a bright future—or in his words, an exhilarating ride—for MEMS in the automotive market. Of particular note are the various architectures for this market.

Cadence’s Jack Erickson sees the Internet of Things as the next big driver of design—and high-level synthesis. Considering the emphasis will be on time-to-market rather than complex tradeoffs at the most advanced process nodes, there is a good case for HLS everywhere.

Synopsys’ Eric Huang takes a look at where USB 3.0 is showing up—new products, existing products, but not in smart phones. You have to wonder about that one.

Mentor’s Andrew Patterson looks at how embedded OSes are chosen by auto makers and why the current approach raises all sorts of questions about security and safety. Does anyone buy screwdrivers anymore?

Cadence’s Stacy Whiteman digs into delta markers in ViVA, Cadence’s waveform viewer. This kind of insight into tools is valuable for users of these tools.

Synopsys’ Mick Posner is wondering when the Pac-Man video game was launched. Unless this is a trick question, the answer is 1980. It was developed by the Nakamura AmusementMachine Manufacturing Co., or NAMCO, and distributed in the U.S. market by Midway.

And in case you missed the most recent issue of Low-Power/High-Performance Engineering, here are some standout blogs:

—Synopsys’ Cary Chin looks for logical answers on why his phone’s battery mysteriously drains while it’s asleep.

—Cadence’s Adam Sherer takes a lesson from Mario—Nintendo’s resourceful plumber.

—Mentor’s Steve Pateras shows off the latest development in built-in self-test—a new low-power version—and what it means for design.

—Atrenta’s Mike Gianfagna believes this may be the biggest and best DAC yet, even if it is in Austin.

—Apache Design’s Aveek Sarkar rolls out part two of his epic on challenges in IC and electronic systems verification.

—Calypto’s Ghulam Nurie says that just adding more clock gating isn’t enough. It has to be efficient clock gating.

—Nvidia’s Barry Pangrle questions whether power or performance is more important, and concludes that’s the wrong question to ask.

—And Chris Rowen of Tensilica/Cadence looks at why technology made such a big difference in the Boston Marathon bombing.

By Ed Sperling
Cadence rolled out an enterprise simulator that it claims improves low-power verification productivity by 30%. The focus is on advanced modeling and debug. It also includes the broadest support yet by Cadence for IEEE 1801/UPF, effectively putting to rest longstanding customer complaints about dueling power formats.

Cadence also announced its intent to buy the IP business from Poland-based Evatronix, which specializes in standard interface IP such as USB 2.0/3.0, MIPI and storage controllers. Cadence has been ramping up its IP business since last year year, but this acquisition would position it more directly against Synopsys than previous buys, as well as provide some critical pieces for building subsystems. The purchase price was not made public.

Synopsys rolled out a new release of its physical verification tool, improving speed at all nodes with concurrent clock and data optimization and support for finFET processes. The tool also addresses last-minute engineering change orders, providing ECO guidance for minimal physical impact.  Synopsys also announced that HiSilicon has taped out a 50 million-instance SoC based on ARM’s new Cortex-A15 using its physical verification tool.

In a decidedly different twist on supply chain software, Mentor Graphics rolled out a new addition to its wire harness tool suite, this one for generating data about manufacturing and cost data for each harness design so rapid quotes can be generated. The automotive industry was known for very long lead times on products, but things are becoming much more competitive—which is very good news for chip suppliers.

Atrenta expanded its R&D facility in Noida, India, just outside of New Delhi. The company already had facilities here.

Dassault Systemes acquired SIMPOE, which develops plastic injection molding simulation. Dassault has been building up its suite of 3D modeling tools. The company did not comment on the purchase price.

GlobalFoundries is working with Infineon on development and production of 40nm embedded flash for automotive and security microcontrollers. Security is expected to become a huge market as the automotive industry moves more functionality under the control of semiconductors.

Security is a hot topic in Eastern Europe, too. The market for Russian and Eastern European surveillance equipment will double between 2012 and 2017, according to IHS iSuppli. One of the big drivers is terrorism at high-profile events.

Intel introduced a new low-power, high-performance architecture called Silvermont based on its 22nm tri-gate/finFET process. The company claims up to 3X increase in performance at 5X lower power compared with its Atom processor. Considering power has been one of the big stumbling blocks for Intel in the smartphone market, as well as one of ARM‘s big advantages, this should certainly start some fireworks.

By Ed Sperling
Mentor’s Michael Ford trashes what’s supposed to be intelligent advertising, namely tracking searches and blasting users with targeted ads. In the age of the Internet, “better late than never” doesn’t apply.

Synopsys’ Mick Posner may have discovered a new opportunity for electronics—a lane warning departure from the vehicle that’s about to be hit. Nice dent dude.

Cadence’s Adam Sherer digs under the covers of low-power verification and why it’s becoming so difficult. It’s beyond the point of even counting the problems. There are too many.

Real Intent’s Graham Bell examines X management—unknowns—and their relationship to reset analysis. He’s right: Unknowns are becoming a huge problem in design.

Dassault’s Mehdi Tayoubi looks at the resurgence of artistic GIFs from a couple decades ago, and how they’ve changed. Check out the video. It’s amazing.

IHS iSuppli’s Jeremie Bouchard looks at the MEMS business and why Apple is so important to their business. The answer lies in the microphones.

Mentor’s Colin Walls offers praise for truly developing hardware and software in sync—and why it’s so hard to do.

Synopsys’ Eric Huang examines WiFi routers and why some of them with USB 3.0 are faster than others. He also times the consumption of a box of donuts, raising important questions about why some people eat donuts faster than others. And what’s with that knife?

Cadence’s Richard Goering recounts a lively conversation between Joe Costello and Jim Hogan about compelling company stories. This is like the preface to, “Follow the money.” It’s called, “How to get the money.”

Mentor’s Mike Jensen compares EDA to Windows 8. His point is cool user interfaces, but Microsoft is getting ready to overhaul the operating system because of an eruption of complaints.

By Ed Sperling
ARM licensed 138 Sonics patents, including those affecting on-chip interconnects and agreed to support Sonics’ forthcoming power management technologies. The deal goes a long way toward reducing legal liability for SoC makers using ARM processors and microcontrollers, as well as propelling network-on-chip technology forward.

Synopsys rolled out a virtual development kit for Freescale’s Qorivva microcontrollers that speeds software development, integration and test.

Cadence teamed up with GlobalFoundries to improve DFM signoff for the 20nm and 14nm process nodes, adding pattern classification and matching. GlobalFoundries will use it for a pattern-matching based lithography signoff flow called DRC+, which is used to classify thousands of problems into pattern libraries.

Intel named a fab expert, Brian Krzanich, as its new CEO, raising speculation across the industry about what the company will try to accomplish during his tenure. Opinions range from a greater push into mobile to a bigger play in the foundry market, but the reality is likely to be all of the above and more. Case in point: The selection of Renee James as president. Her background ranges from hardware to software and services.

By Ed Sperling
Mentor’s Anil Khanna looks at zero configuration networking, one of the technologies at the root of the Internet of Things and machine-to-machine communications. And this is just the beginning. Wait until machines start marketing to other machines.

Cadence’s Jason Andrews shines a spotlight on virtual platforms, including who creates the models for them and what should be included in those models. Check out the photo of his whiteboard, too. This is a good diagram of how an engineer’s mind works.

Synopsys’ Mick Posner sheds light on the fine art of merging onto a freeway and the perpetual need to notice what’s in your blind spot—which in this case also happens to include an FPGA prototyping platform.

Dassault’s Aurelien Blaha interviews industrial designer Geoffrey Cooper about rolling tree-planting robots to replant forests and restore deserts. Nifty idea. There’s a cool video to go with it, too.

IHS iSuppli’s Peter Lin notes that China became the leading PC market in 2012. There are four shifts under way in that market, ranging from preferred form factor to the OS that runs on it. What’s really intriguing, though, is the huge bump in sales in rural areas, which is an enormous opportunity.

Independent blogger Guarav Jalan makes a strong case for combining constrained random verification with coverage driven verification—and what’s needed to make it happen. He claims that, done right, it’s a competitive game changer.

Mentor’s Mark Laing poses a question that has nagged auto aficionados for years: How many ratios do you need in your car’s gearbox? The answer may surprise you.

Cadence’s Richard Goering reports on a presentation given by Oracle’s Tom Dillinger about the challenges of parasitic extraction in finFETs. There’s been a lot of talk about this subject lately, but there’s no simple solution—at least not yet.  Goering also tracked a presentation by GlobalFoundries’ Jongwook Kye about the need for design technology co-optimization, particularly at 10nm. This is a new wrinkle for DFM.

Synopsys’ Eric Huang offers some tips about sushi and USB. Bottom line: Never buy IP where you are the only customer.

Mentor’s Dennis Brophy talks about low-power design and verification, and why the new IEEE low-power standard for the Unified Power Format is so critical. There are even power-aware verification course modules.

Synopsys’ Helen Thibieroz talks with Paul Chapman about regressions, which in any other industry would mean something entirely different. In this case, it’s a very good thing.

And in case you missed the most recent issue of the System-Level Design newsletter, here are some noteworthy blogs:

Synopsys’ Tom De Schutter looks at the real value of virtual prototypes. How long are you willing to wait?

Cadence’s Frank Schirrmeister takes a skeptical dive into subsystems and reuse and emerges optimistic.

Mentor’s Jon McDonald says that modeling complex computations can have a big effect on reducing the overall design costs. Raising the level of abstraction is usually the best way to find problems, providing you do it correctly.

Arteris’ Kurt Shuler uses a series of meetings with analysts to draw conclusions about cost, names and IP.

Real Intent’s Graham Bell digs into how to manage unknowns in simulation, which is a growing concern in signoff.

And Sonics’ Frank Ferro buys a new smart phone, only to find out the battery life is actually shorter than his old phone. The question is what it will take to really improve power management. He has some ideas.

By Ed Sperling
Mentor Graphics uncorked an extension to its embedded software development platform that for the first time will allow software engineers to write more energy-efficient code without having to use additional tools. The new virtual edition of the tool adds capabilities in the native environment rather than forcing software engineers to learn new techniques, and it allows hardware engineers to virtually see what the software engineers are developing and where problems show up during debugging. This is an intriguing development, and it represents a completely different approach to hardware-software co-design.

Synopsys rolled out an integrated tool suite to accelerate application-specific instruction-set processor design—the highly specific processors that can greatly boost performance using the least amount of energy—by combining a process design tool with its FPGA-based prototyping system. Using custom processors in an SoC is a significantly more efficient approach than trying to run everything on general-purpose processors, and they will be critical for subsystems, which are expected to become far more popular over the next few years.

Cadence’s fiscal Q1 revenue increased 12% to $354 million, compared to the same period in 2012. Net income increased to $79 million from $31 million in 2012, due in part to a $34 million tax benefit. Excluding the tax benefit, net income rose 45%, which is still healthy, a reflection of increases in both emulation and IP, according to the company.

Dassault Systemes acquired Germany’s FE-DESIGN Group, which optimizes early-stage product development. FE-DESIGN focuses on structural and fluids-based system design. Dassault also reported its Q1 financial results. Revenue grew 5% to 485.3 million Euros. Earnings per share were 0.58 Euros, flat from the same period in 2012, but the company also proposed an 0.80 Euro annual cash dividend per share.

More smart phones were shipped than “feature phones” in Q1, according to IDC. Out of a total 418.6 million mobile phones shipped—up from 402.4 million in the same period in 2012—smart phones accounted for 51.6% of the total. That may explain why PC sales are down, particularly in emerging markets.

IHS iSuppli projects sales of smart glasses—think Google Glass, which is the main player in this category—could hit 6.6 million units in 2016. But the analyst firm also cautions that success hinges on the apps developed for this platform. If compelling applications don’t materialize, sales will be significantly lower. It takes a well-tested commercial infrastructure to develop and manufacture the platform, but it takes a global ecosystem to drive sales.

By Ed Sperling
As the Internet of Things bridges the gap between the mobile and big data worlds, EDA and IP vendors increasingly are looking well beyond their usual boundaries.

How successful they are at moving upward into a market that is far less price-sensitive remains to be seen. But from a technology standpoint, at least, the issues encountered by data centers and cloud providers are remarkably familiar. They’re the same ones that engineering teams already wrestle with in the mobile SoC world—performance, power and area.

When it comes to big data, each of these factors can be measured in real dollars rather than hours on a battery. Improving performance means fewer servers are needed within the data center, and it frequently translates into less energy per computation. Fewer servers also are more efficient because they require less energy to power and cool a data center, which is one of the biggest costs faced by CIOs.

While data center consolidation of servers has been under way for the past decade, there are two areas that are only now beginning to be addressed. One involves software, where applications, operating systems and middleware can be made significantly more efficient. Those kinds of improvements have rarely been even considered in the data center, where the key attributes of successful software are performance and accuracy.

A second area involves storage. The amount of data being stored is exploding, and being able to access it efficiently and within a reasonable amount of time is the next big challenge. It’s also where chipmakers, IP vendors and EDA companies see a big opening—and one that will only grow in importance as the Internet of Things begins to take root.

But all of this requires thinking about a system-level design from the standpoint of an entire data center, where the kinds of tradeoffs made in one area can have big impacts on another.

Software
At least part of the challenge, as well as one of the largest opportunities, is the ability to bridge hardware and software—and to make each more efficient. The two worlds have existed as silos at the enterprise level since the invention of the mainframe, when product cycles were as long as a decade.

“We have server-based customers using virtual prototypes to model the power and launch software, but it’s surprising just how little interest there is within the software community to deal with power,” said Glenn Perry, general manager of the embedded software division at Mentor Graphics. “It’s frustrating because one or two lines of code can add 10% in terms of power.”

Perry said that Mentor has been trying to push more efficient software programming since the 1990s, but the only ones who have shown real interest in improving the efficiency of software are hardware engineers. The solution, and one the company has just begun to promote, is using the same software development tools with some rather innocuous additions that check on power efficiency.

“Until now, when you when a software engineer hit a break point, they’d blame the hardware and the hardware guy would blame the software. What we’ve been able to do is collect data in the correct database so the hardware engineer sees the same data as the software engineer. It’s almost like they’re providing a second view of the same process, and it allows the software developers to connect to the emulator.”

Commercial IP
Another opportunity involves IP. While the amount of commercially developed IP content is growing on the SoC level, it is crossing over into the data center world through PCI Express and the protocols that ride on top of that—Nonvolatile Memory Express (NVMe) and Small Computer System Interface Express (SCSIe).

“We’re seeing three initiatives in the data center,” said Ron DiGiuseppe, strategic marketing manager for IP at Synopsys. “The first is on the compute side, where lower-power SoCs and compute operations are becoming critical. The second is in networking, with software-defined networking on how to manage data on the data plane, which is where PCIe is standard. The third is on the storage side where there is a lot of activity around things like buffering and packaging.”

With storage, the key is protocol conversion above PCIe until a single de facto standard emerges, similar to what happened with Blu-ray and HD-DVD in the high-definition DVD space. “We’re seeing customers implementing one or both (NVMe and SCSIe),” he said. “They’re also using a range or storage solutions ranging from RAM to external drives to cache acceleration. We’re also seeing demand for a whole range of IP, whether that’s PCIe generation 1, 2 or 3. It’s critical for the data center that the software provided to ISAs is synchronized.”

PCIe is particularly important in this world because it’s almost ubiquitous, from networking to PCs and add-in cards. It’s also in the storage IP, which is why Cadence and Synopsys are both battling for a piece of this market—both with IP and verification IP. Cadence rolled out a full subsystem in this space last year, as well, including a controller, PHY, firmware and VIP.

“Any time there is a convergence of standard protocols there are opportunities to look at subsystems,” said Susan Peterson, group director of VIP marketing in Cadence’s SoC Realization Group. “We’re anticipating more subsystems, coupled with EDA tools such as emulation or acceleration to verify an SoC or system, and other tools for layout.”

She noted that the big opportunity—if it materializes—is for full data center analysis, particularly involving power. “We’re also going to see more and more standards like SATA, NVMe and IDE, which makes connections to standards easier.”

Hurdles ahead
While these opportunities sound straightforward enough, there also are some giant hurdles.

“One of the biggest issues we see is differentiation,” said Naveed Sherwani, president and CEO of Open-Silicon. “Software is the biggest play to differentiation, but everyone has their own proprietary hardware, I/Os, and technology for transferring data between switches and routers. You can’t buy generic solutions here. On top of that, the tools will remain ASIC-centric for at least a few years.”

He noted the big picture problem to solve isn’t latency on a chip it’s latency across a data center. That has to be accomplished using less energy to achieve better performance everywhere, and it’s where software will become particularly important.

This is not simple stuff, and it compounds the problems that many companies have encountered in the ASIC world. While the problems are similar, it doesn’t necessarily follow that the approaches for solving the problems are exactly the same.

“With the Internet of Things we’re going to see arrays of sensors loosely connected to help people make intelligent decisions,” said Drew Wingard, CTO at Sonics. “So we’re going to need SoC design techniques to attach to the server, but they will have to be fully cache coherent, highly reliable, with performance analysis. This is not where most of the SoC design work has been. The big iron guys also will have to learn about higher levels of integration and the ASIC guys will have to develop different techniques. The current ASIC flow only works because they’ve made the assumption that they can fix problems with guard-banding. They don’t error-check everything.”

This is a big shift for SoC developers, and it remains to be seen just how well these two worlds meet, Wingard said. While the SoC developers have a better sense of use models and power management, they clearly don’t have all the pieces. But neither does anyone else.

And that has left everyone thinking seriously about where the new opportunities might be. “Every EDA supplier is thinking about this, because for the first time in the past 20 years it means a new customer base,” said Mike Gianfagna, vice president of corporate marketing at Atrenta. “ The number of design starts is shrinking even though they’re getting more complicated. That leaves two new opportunities. One is in 3D-IC, which we believe will be real whether it’s in one year, two years or four years. The second opportunity is in the data center.”

With legacy hardware interfaces and well-established operating systems and applications, the real opportunities appear to point to IP and software—particularly embedded software. “If you can add a layer that deals with clock frequencies and that turns things on an off, that can be a big win,” Gianfagna said.