It must be time to solve those pesky I/O issues no one got around to fixing last year. Mentor Graphics introduced a hardware-assisted solution for USB 2.0 verification called iSolve, which works with a variety of emulators. Cut the wait time wherever you can.

And Synopsys uncorked a couple new products for USB 3.0. One is a DesignWare protocol analyzer for verifying USB 3.0-based designs. It also introduced USB 3.0 models for TLM 2.0.

Virage Logic set up an R&D center of excellence in the Netherlands. This builds on the rather complex deal Virage inked with NXP last year. Note the analog business unit, which plays heavily into Virage’s ARC acquisition.

GlobalFoundries completed its acquisition of Chartered Semiconductor. It now owns two 300mm fabs and is building a third in New York State. The bottom line: It’s now down to the Common Platform (GlobalFoundries included) vs. TSMC at advanced nodes in the merchant foundry business. Watch out for falling shrapnel.

Speaking of TSMC, the foundry is developing its 28nm process technology with Qualcomm. Most process folks think 28nm is an evolution, but 20nm starts getting really tricky. This may be a good time to start reading up on FinFETs, air gap insulation, self-assembling components and new substrate materials like graphene. They’ll be filed in the science fiction section.

Intel seems to be doing okay these days. Its fourth-quarter income jumped 875%. No, that is not a typo. Revenue was up 28% year over year. And while the computer market pull-through isn’t what it used to be for electronics companies, it certainly can’t hurt.

By Ed Sperling

Virage Logic wasted no time in putting its ARC acquisition to work. As soon as the ink dried for the deal, Virage opened fire on ARM. Virage’s new 32-bit processor core, aka the ARC 601, is aimed squarely at ARM’s Cortex M0 microcontroller. With the lines already blurred between microprocessors and microcontrollers this should prove to be an interesting slugfest. What’s especially interesting about this new ARC core is that it’s the same size as an 8-bit microcontroller.

At least ARM is getting a reprieve from Intel’s laser-like focus. With the Federal Trade Commission hammering Intel, this time for including graphics on its processors, the company is facing battles on all fronts—Europe, Korea, Japan and now the United States, it has to be a major distraction. How many other big markets are there? Intel did take the unusual step of responding to the FTC with a statement. It said the FTC jumped the gun and filed before it knew the facts.

Meanwhile, the other half of the dynamic duo, Microsoft, settled its dispute with the EU. Microsoft will now offer multiple browsers to customers. Does anyone still care about which browser gets used? A more pertinent question is whether they can take advantage of more than one core for searches and video playback.

Mentor Graphics achieved IPv6 phase II compliance for its Nucleus operating system. IPv4 is predicted to run out of address space in 2010, which happily was never mentioned in the Mayan calendar. Still, this is a good move for Mentor. We’re taking odds on whether there will be some hiccups in the transition of the Internet, though.

X-Fab, a major analog/mixed signal foundry in Germany, is backing Synopsys’ Galaxy custom installation solution. Analog and mixed signal continues to be a slow and tedious process, in part because analog engineers don’t put a lot of trust in automated tools. Anyone trying to push tools into this market needs a lot of patience and staying power.

TSMC introduced process technology for LED driver devices. This stuff goes all the way back to .6 micron, which is 600nm and as far forward as 180nm. Guess they found a good use for all that fully depreciated equipment.

Chartered Semi, meanwhile, won two investor relations awards in Asia. This is interesting because Chartered has been dead silent since early September, when Abu Dhabi’s ATIC offered to buy the company.

By Ed Sperling

As the semiconductor industry digs out from one of the worst downturns in decades, the business of semiconductor design and engineering is changing. While the architecture and features are still being developed by chip companies, the actual work of developing the chip increasingly is being done by third parties.

Outsourcing is hardly new concept in business. In the early part of the 20th century, most automobile makers recognized that it was far more efficient to design a car than produce the parts needed to run it. Outsourcing the design itself, however, has never proven successful because otherwise there would be no differentiation from one manufacturer to the next.

Even within this outsourcing there is specialization and stratification.

IDMs as foundries

Over the past decade, almost all the major integrated device manufacturers have offered foundry services to customers to help offset these costs, usually within the bounds of very restrictive designs. IBM, AMD, Toshiba and now Intel have all taken this approach, and so far none has been particularly successful. Others, such as Texas Instruments, have handed their manufacturing over to major foundries and given up trying to keep pace with rising costs for digital or advanced mixed signal chips.

The latest player to put a stake in this market is Globalfoundries, the AMD joint venture with Advanced Technology Investment Company (ATIC), the investment arm of the Abu Dhabi government that recently announced its intention to buy Chartered Semiconductor. Globalfoundries’ approach is to become a virtual IDM, creating design kits, IP, processes, and even transistor tuning and metal stacks. It does not do the place and route, however, which some of the other IDM foundries have done in the past.

“What we’re doing differently is providing feedback to customers,” said Subramani Kengeri, vice president of design solutions at Globalfoundries. “The disaggregated supply chain model was broken. We’re able to provide very early access, certification for IP—that’s product grade qualification—and we can emulate an SoC so the building blocks are verified at almost the SoC level. We also have a ‘gate first’ approach, while Intel has a ‘gate last’ approach. That gives us more than two times the gate density, and we offer SOI for super high performance.”

This is no ordinary foundry play, and Intel’s approach is to focus on a menu of possible services ranging from power and memory choices to the number of layers and transistor strategy. (See Figure 1) Paul Otellini, Intel president and CEO, said at the Intel Developer Forum last month that he expects SoCs to surpass processors as the company’s revenue stream over the next decade.

Figure 1: Intel's SoC offering.

IBM, meanwhile, has been offering what it calls end-to-end integration from design to manufacturing to characterization and test, and Toshiba has been providing complete design services for the past several years.

How successful these ventures are is unknown. None of these companies break out their revenues for these operations.

Foundries as design houses

While the IDMs seek to recoup their development costs with design and manufacturing services, pure-play foundries aren’t looking so pure-play anymore, either.

The problem with the pure-play model is that majority of designs are being manufactured at older process nodes, which is not where foundries can generate the highest profit. It’s also not where they gain the money to develop new processors or the experience on those new processes to mature them, thereby simplifying the move to the most advanced nodes and amortizing the whole investment.

This explains why TSMC took a 49% stake in Global Unichip Corp. six years ago (it has since reduced that investment), and why the big names on the GUC board of directors are the same ones on TSMC’s board. In fact, looking at the two boards it’s hard to differentiate the companies.

Rival UMC, meanwhile, struck a design services agreement with Bangalore-based Wipro Technologies for the entire design cycle for ASICs and SoCs.

Until recently, when ATIC made a bid for Chartered, it was Chartered that was claiming it was the last major pure-play foundry because of these outside relationships.

Design houses as advanced chip engineers

The last piece to change in the supply chain is the one that was predicted first—but differently. As designs become more complicated and time-to-market pressures mount for companies, many thought they would outsource some of their older designs to companies that could churn them out relatively cheaply while focusing design work on the bleeding edge of Moore’s Law.

What’s happened, however, is quite different from the predictions. Companies like eSilicon and OpenSilicon are now developing much more complex designs than anyone would have guessed. In fact, eSilicon now views 40nm as mainstream, according to Prasad Subramaniam, the company’s vice president of design technology.

Subramaniam notes that complexity is becoming so great that it’s difficult for many companies to turn out a chip or two every year. Engineers don’t have enough experience with some of the tools and difficult techniques such as multiple power islands and complex verification to work at these nodes.

Open-Silicon has reached the same conclusion after initially pitching its design services for older process nodes.

“The downturn convinced people to outsource,” said Naveed Sherwani, Open-Silicon’s president and CEO. “Three years ago our customers were startups. Now they’re large companies. We’re finding that our real competition now is the internal teams within these companies. The VP of engineering services now sees us as competition. We’re writing RTL for them.”

By Ed Sperling
The Common Platform is starting to attach ratings to intellectual property, a move intended to take the guesswork out of whether third-party IP will work as planned at various process nodes and whether it can be manufactured.

The effort is a reflection of just how difficult it is to get chips out the door at future process nodes, and how regulated designs rules will be adhered to in order to keep fabs churning out complex semiconductors. “This is the next step past silicon-proven,” said Kevin Meyer, vice president of industry marketing and platform alliances at Chartered. “It’s now manufacturability-proven.”

The Common Platform triumvirate—IBM, Samsung and Chartered Semiconductor—began the effort over the past year to ensure that all IP meets design for manufacturability criteria and issuing a score based upon lithography simulation and the manufacturing checking deck (MCD).

“We’ve been working with various IP providers to do this in the past,” said Walter Ng, vice president of design enablement services at Chartered. “Now they have to pick up their fair share of this.”

In the past, when the Common Platform rolled out sponsored versions of its foundation IP, including standard cells, memory compilers, USB and SERDES, it was already tested for litho simulation and MCD. The only thing that was not included was critical error testing, and while still considered important it is not part of the rating system.

“IP will be rated for MCD from zero to 100,” said Ng. “We will enforce 90 as a minimum score. We want IP providers to do this kind of testing as part of their design because it’s too disruptive otherwise.”

TSMC has been working on a IP rating similar scheme for the past several years called TSMC 9000, a reference to the ISO 9000 manufacturing standards.

The Common Platform also has standardized on Mentor’s DFM tools as it moves forward into computational scaling to define shapes at 22nm and beyond. “We evaluated multiple vendors’ tools and made our choice for what is golden and best in class,” Ng said.

By Ed Sperling

It was a good week for those companies—and countries—with cash.

The Abu Dhabi government’s $5.6 billion bid for Chartered Semiconductor took top billing this week as the deal to watch. The Advanced Technology Investment Company made the bid, but the company is entirely owned by the government. This is the same group that set up a joint venture with AMD to create Globalfoundries.

Synopsys also announced that it would repurchase $500 million in stock, which is what companies do when they want to boost the price of their shares. It’s simple math. The fewer shares, the more they’re worth. IBM has been doing this for years.

Meanwhile, back at the foundries, Cadence announced a broad multi-year technology agreement with Globalfoundries for design, verification and manufacturing. Well, at least we know there’s plenty of money to pay for the tools.

There’s also more money in the works for Magma. The company’s offer to exchange outstanding convertible notes was greeted positively by the majority of bondholders. To paraphrase Mark Twain, news of this company’s death are greatly exaggerated.

So with all this positive activity going on, why did TSMC’s sales drop last month? The top foundry’s numbers show sales in August 2009 were $887 million (U.S.), versus $922 million in August 2008. Sales were down year over year for the first eight months, as well. Aren’t all signs supposed to be pointing to the end of a protracted downturn?

Synopsys introduced DDR3 PHY and digital controller IP with support for the newest 2133 Mbps data rates from JECEC and the anticipated new low-power 1.35 volt standard (compared with the existing 1.5 volts). The company is the first to get there—even ahead of the new standards—but it certainly won’t be the only one.

Also on the IP front, Cypress licensed a broad array of ARM’s intellectual property for its programmable line. Expect to see a lot more in the programmable space in coming months as business concerns begin infiltrating what formerly were technology-only decisions.

By Ed Sperling

Virage Logic sent a large ripple through the IP community, stating its intention to buy ARC International—one of the few IP processor companies left—and intensifying the race to consolidate that began in earnest when ARM bought Artisan. For an estimated $41 million, Virage now has inroads alongside both Intel for its Atom processor and ARM for its own Cortex line—not to mention the possibility to challenge both someday if can amass enough market share.

Synopsys sailed through its quarter firmly in the black, posting revenue of $345.2 million for the third fiscal quarter ended July 31, up from $344.1 million for the same period last year. Net income was $68.3 million, or 47 cents a share on a non-GAAP basis, or 32 cents a share on a GAAP basis. The company expects to post revenue of between $1.357 billion and $1.365 billion for the full fiscal year, with GAAP earnings per share of between $1.16 and $1.23. Somebody break out the champagne—please.

Synopsys also rolled out its HDMI IP for 90nm to 40nm process technologies, which is about as far as anyone using HDMI has even thought of going.

Mentor Graphics snuck by in the black last quarter, if you use Non-GAAP numbers, but the real news is the strength of its bookings. Revenue for the quarter was $182.6 million, up about $200,000 over the same period in 2008. Non-GAAP income was 2 cents a share, compared with a loss of 2 cents a share for the same period in 2008. On a GAAP basis, the company lost 22 cents a share. In a statement, CEO Wally Rhines said Mentor continues to build strength in ESL and low-power product offerings.

Mentor’s bid for LogicVision also was approved by LogicVision’s stockholders, making it a done deal. The bid had been announced in May. The combination gives Mentor built-in self test technology, complementing its own automated test pattern generation technology.

Things must be going relatively well on the chip manufacturing side these days, too. TSMC’s board of directors appropriated $1.12 billion to expand the 45nm process capacity and install some 32nm process capacity, and it approved a $50 million appropriation for “solar-related areas.” That could prove very interesting.

Chartered Semiconductor, meanwhile, said its 32nm process using high k/metal gate is ready, and it is working on 28nm.

By Ed Sperling

Power is shifting across the design industry in multiple ways and sometimes across multiple continents, driven by complexity and cost pressures and entirely new forms of competition.

On one side of the equation, foundries are dictating more of what goes on up front in the design cycle. Design for manufacturing is a prerequisite at 45nm and below, and they’re the ones dictating the rules. Moreover, those rules are becoming far more stringent at 32/28nm because the lasers used to etch chips aren’t thin enough at 193nm—even with immersion technology—to etch all the polygons as irregularly as in the past.

On the other side, ESL modeling is removing much of the control for designs from individual design engineers used to working with RTL or various levels above that. Interfaces are entirely too complex to map out by hand, IP is bought by the block with the real challenge moving to the integration and testing of those blocks, and verification continues to become more unwieldy as tradeoffs between performance, area and power—and power in multiple states and islands—become orders of magnitude more complex.

The foundry shift

With new fabs costing $4 billion to $5 billion for the most advanced process nodes, it’s no wonder that most companies no longer can afford them. Even IBM has partners for developing new processes, and it continues to expand its ecosystem for new technologies to include companies like Sony, Infineon and AMD. And the mighty Intel, until recently the one holdout in the integrated-device manufacturing model, has shifted manufacturing for its Atom chip to TSMC.

But that shift also has concentrated an increasing amount of power in the hands of a few foundries, most notably TSMC, UMC and the Common Platform triumvirate of IBM, Samsung and Chartered Semiconductor. With cost pressures rising on them, they’re in a position to both dictate what gets built, how it gets built, and what gets used in a design.

Already, the foundries are dictating what IP gets validated. Tom Quan, TSMC deputy director, said the foundry has a portfolio of IP companies as a necessary part of getting designs into production.

“We’ve got to understand who’s doing what, who’s got the star IP,” said Quan. “We have to know all the pieces and pick the right players. We also have to look at the emerging players and choose which ones we think are the most promising. We’re betting on them.”

This becomes particularly important at future nodes. Currently, about two-thirds of TSMC’s revenue comes from the 65nm and 90nm process nodes. In the first half of 2010, the foundry estimates that half its revenue will come from 28nm chips.

That also means more restrictive design rules, because if the designs don’t head into production then the foundries don’t make money.

“Restrictive rules increase productivity,” said Quan. “At 40nm, we had some rules. At 28nm, there will be more. And at 22nm, there will be even more.”

Driving those rules are layout-dependent effects caused by everything from diffusion to stress engineering. Those effects can be theorized, but reality isn’t always the same. And that means the layout designer will have far less freedom than in the past.

That’s no surprise to some long-time industry investors. Startup Tela Innovations—notably funded by Cadence, Qualcomm and Intel, among others—is focused on developing more regular layouts to make them easier to print. Neil Carney, VP of marketing at Tela, said the company’s focus is on front-end rules, including ways to break designs into to parts using double patterning.

One source, who spoke on condition that he not be named, said the new design rules put designers back 20 years. “What you’re giving up is shape-based technology where you tune with wires and vias,” he said. “At 22nm, you’re back on the grid. Wrong-way wires will disappear.”

That opinion was echoed by Giuseppe Forniciari, senior design manager at ST Microelectronics: “At 40nm and below, wiring dominates gates and margins add too much power.” He said the need for concurrent multi-corner, multi-mode throughput on the flow is now essential.

Raising the abstraction level

While EDA executives jab at the growing control of the foundries whenever the opportunity arises, individual designers are taking shots at the growing control of the large EDA vendors. ESL modeling removes much of the control in a design from their hands and raises it to a level that makes them more reliant on tools than ever before.

This is, in part, why analog engineers have so strongly resisted using EDA tools. It’s also why modeling has experienced relatively slow growth in the digital world. But with complexity now beyond the comprehension of the human brain—particularly within the time constraints of most chipmakers—raising up the level of abstraction and keeping track of all these different levels, power states and voltage islands makes modeling a necessity.

Modeling plays neatly into the hands of the big EDA vendors, which are working on everything from simulation to validation and software prototyping. Tadahiko Yamamoto, chief specialist in Toshiba’s design methodology development group, said that with Synopsys’ IC Validation Design rule checker it was able to reduce the number of steps to three from what was previously six. In addition, total time spent was reduced to a few hours instead of more than a day.

Intel is even starting to measure progress in “time to model.” Daniel Pace, senior software engineer at Intel, said the goal is quick turnaround for adjusting the model and mixed levels of abstraction.

Conclusion

Complexity, technology limitations in areas such as lithography, time-to-market pressures and the rising cost of getting chips out the door will change fundamental power relationships within the semiconductor design industry. Systems on chip require different skill sets than simple IC designs, but SoCs built at 22nm will require different skills, tools, packaging and possibly even different substrates and materials than those built at 28nm. So far, no one is even sure what the half node beyond 22nm will be or what that will entail.

Chipmakers are coping with all of this by outsourcing designs altogether to companies like eSilicon or Open Silicon, skipping nodes, or hanging back a node or two on some products to save development time and cost because manufacturing processes are more mature there. It’s even too expensive to continue developing their own point tools at the leading edge of design, which used to be a differentiator for many IDMs—back when there were IDMs—and putting more resources into software development.

But if these kinds of changes in the industry’s power structure are happening over the course of a couple of process nodes, what will happen at the next couple of nodes beyond 22nm?