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Blog Review – Mon April 14 2014

Monday, April 14th, 2014

Static warning about keyword variables in C language; wearable electronics; more power to the user interface; IP sales – where and when to shop around; EDA consolidation concerns. By Caroline Hayes, Senior Editor

Defining the static keyword in the C language can cause mayhem and confusion, but Jacob Beningo, ARM, has helpful advice in his blog about when and where to declare.

With an eye on the aesthetics of wearable electronics, Ansys’s Sudhir Sharma writes about cool, wearable electronics design, with some interesting examples and practical news for a related webinar using Synapse for engineering services.

As a follow up to his web seminar, called Create Compelling User Interfaces for Embedded with Qt Framework, Phil Brumby sits in the guest blogger seat at Mentor Graphics. He uses it as a platform to complete unfinished business, posting and answering questions not covered in the seminar and to help assess the processor power required for a particular project.

When and what to buy and if to buy at all, is the focus of a well constructed blog by Neha Mittal , Arrow Devices. It defines the four IP development models, and lists the advantages and disadvantages of each.

John Blyler looks at the EDA market’s recent activity for mergers and considers the future, with a Consolidation Curve and the effect consolidation has on the industry and its innovation.

EDA in the Age of the System

Monday, July 31st, 2017

Learn from other industries to gain a system’s perspective was the reoccurring theme of Garysmith EDA analyst Laurie Balch’s pre-DAC address.

By John Blyler, Editor-in-Chief, ESDE

Once again, the system took center stage at the recent Design Automation Conference (DAC), an event focused on the software tools required to developed semiconductor system-on-chip (SOC) devices. These software tools typically fall under the heading of electronic design automation (EDA).

As per tradition, DAC kicked-off with a Sunday night “state of the industry” address by the analysts at GarySmith EDA (GSEDA). This year’s event was presented by Laurie Balch, Chief Analyst at GSEDA (see Figure 1).

Figure 1: Laurie Balch, Chief Analyst at GSEDA, presents EDA trends at DAC 2017 in Austin, TX.

She began by highlighting the positives with the chip design industry, starting with the diversity of both larger established and smaller start-up companies. Further, EDA is a mature market where litigations among the companies has more or less subsided. Finally, the chip industry is still very dynamic with lots of new product development.

The bad news is that there will be no double-digit growth for the traditional EDA space in the near future, at least not without a few changes, explained Balch (see Figure 2). More on that shortly.

EDA Growth Chart

Figure 2: Double-digit growth is not expected anytime soon for the EDA industry. (Courtesy GSEDA)

Broadening the Core

This begs the question as to the meaning of the traditional EDA landscape. In the past, EDA has provided tools in a number of development abstraction areas, including semiconductor chip gate-level and register transfer level (RTL) design-verification, electronic system level (ESL) design, packaging and interfaces to IC Computer-Aided Design (CAD) and Printed-Circuit Board (PCB) design.

“Since EDA is a maturing market, the industry needs to more beyond the traditional definition,” explained Balch. “In addition to the core EDA space, we have to include the embedded, mechanical and IP markets. These peripheral markets are central to understanding the future growth potential of EDA (see Figure 3).”

EDA Peripheral Markets

Figure 3: Expanded view of EDA markets and growth potential. (Courtesy of GSEDA)

Engaging with customers on the intersecting markets means that semiconductor companies must think about high-level systems. This is not a new observation. At last year’s DAC-2016, Balch predicted that EDA will see mechanical CAD vendors coming onto tradition semiconductor turf. This was confirmed with the recent acquisition of long-time EDA giant Mentor Graphics by Siemens PLM, a global systems, software and CAD business.

Mechanical CAD is only one of three markets that will help expand revenues to the traditional EDA market. The growth of semiconductor and embedded intellectual property (IP) over the last several years has already improved the revenue outlook. Adding mechanical design and embedded software will lead to further revenues, noted Balch.

Popular Tools

What were purported to be the hot new EDA market spaces at this year’s DAC? Balch provided the following list:

  • Analog/Mixed-Signal/RF
  • Emulation
  • System-Level Tools
  • Intellectual Property (IP)
  • Simulation & Verification
  • Circling the edges of EDA
  • Automotive

This list has changed little from previous DAC events. Perhaps the only difference now has been from the recent flurry of acquisitions which resulted in market share shifts among the three major EDA vendors.

What Does it Mean?

Today’s EDA is a market in transition, one that faces many challenges. Balch listed four main concerns:

  • Disappearance of double digit growth
  • Disruptive change vs. process improvement
  • Shift in vertical industry influences
  • IoT design impact

The disappearance of double-digit growth in traditional EDA markets has already been covered. Balch didn’t see disruptive changes in the market but rather a move toward more efficient methods in the overall chip development process. This was taken as a good move as process improvement is the right mindset for system development, she noted.

A shift to vertical markets could be a good thing for EDA, e.g., consider the rising growth in the automotive sector.

Perhaps the real challenge to EDA tool vendors is the rise of the Internet-of-Things (IOT). Designing for IOT requires changing some ways that EDA designs and offers their own tools, noted Balch. One big different is that most IOT designs don’t required the lowest and most expensive manufacturing nodes. I’ve noted other differences in the IOT design approach in other articles. (See, “Why is Chip Design for IOT so Hard?”)

Path Forward

One way to gain perspective on today’s EDA market is to look at it from another angle. For example, perhaps the mechanical design market will serve as a template for EDA. Balch pointed out the EDA originally grew out of the mechanical CAD space. Another comparison point is that mechanical CAD tools had a slow growth period similar to the one facing EDA. The latter emerged from its doldrums with new strategies that included reaching out to other markets.

Another change of perspective is afforded by the so-called “tall, thin engineer.” In the chip community (referencing Howard Sachs), a tall-thin engineer was a generalist with broad knowledge in many different fields rather than a specialist deeply involved in only areas, say IC design or layout.

Personally, I find this term misleading. A “tall, thin engineer” seems more indicative of a specialist, i.e., someone who has a deep (or tall) understanding in a very narrow (or thin) area of technology – for example, designing digital Silicon chips. In markets outside of EDA, the “tall, thin engineer” is known simply as a systems or systems-of-systems (SOS) engineer. Even this subtle difference in semantics highlights the difficulty that domain and EDA semiconductor engineers will face when expanding into peripheral markets like embedded software and mechanical systems.

Regardless of the semantics, many technical folks touch upon electronics, meaning that they have to deal with electronic issues for which they are not specialists. EDA can help them navigate the technical challenges but only if EDA itself has more generalists that understand the end-users perspective. Thus, the process by which EDA tools are developed would also need to be different. Balch noted that the tool obstacle was confronted by the mechanical community years ago, specifically in Computer-Aided-Engineering (CAE) tools for simulation. The result was new tools that could be used by engineers who were not experts.

Finally, vertical markets are directly influencing the EDA tool market. In the automotive space, Tier 1 companies are forcing their users to use specifically-qualified tools, e.g., ISO-26262. This influence will only continue. (See, “Fit-for-Purpose Tools Needed for ISO 26262 Certification”)

There are encourage signs that the EDA community is embracing other markets. Many presentations at this DAC focused on the new and rising markets of big data, machine learning and artificial intelligences.

EDA Call to Action

In conclusion, Balch listed three activities that would help rejuvenate the EDA community:

  • Recognition of EDA realities
    • Risks of standing still
  • Learn from parallel markets
    • Model for navigating the future
  • Repurposing EDA expertise
    • Creativity in abundance
  • Be fearless!

Foremost on the list was the theme of her presentation, namely, that future EDA strategies must continue to embrace the larger system world. The systems-view will help the community look and learn from other markets, esp. mechanical design.

“We should look at their history and see how they solved similar problems,” emphasized Balch.

The EDA space is well positioned to re-purpose their expertise into new markets, e.g., mechanical design, IP, embedded software and vertical markets like automotive and

Finally, Balch admonished the attendees to be fearless when seeking expanded markets, perhaps by focusing on design data management as well as high level physics-based technologies.

FPGAs for ASIC Prototyping Bridge Global Development

Wednesday, July 20th, 2016
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Hardware-Software Tops Priority List For ASIC Prototypers

Thursday, August 23rd, 2012

By John Blyler
The most important decision facing chip prototyping designers this year (2012) concerned the completeness of the combined hardware and software platform. (See Fig. 1). Cost and boot time followed as the next most importance issues. Close to 200 qualified respondents participated in the annual Chip Design Trends (CDT), “ASIC/ASSP Prototyping with FPGAs” survey.

Fig. 1: Prototyping priorities listed in the 2012 CDT survey.

The concern over a complete hardware-software prototyping solution was in stark contrast to results from previous years, when key concerns revolved around the flexibility and expandability of the system, as well as cost, performance and ease-of-use factors (see chart below).

Another surprising finding in this year’s survey is the importance of system “bring-up-time,” which ranked in the top three concerns for software development-based prototyping systems. The importance of software-related issues was further verified by another survey question that found an overwhelming 65.5% of respondents used a combination of software and hardware execution (i.e. simulation plus FPGA prototyping).

What was the language of choice for these hardware-software co-designers? C/C++ beat out Verilog, VHDL and their derivatives. (see Fig. 2)

Fig. 2: Software languages used in software simulation and hardware (FGPA) based prototyping systems. (Source: 2012 CDT Survey)

Most designers who used a combination of software simulation and hardware FPGA-based prototyping did so to achieve early verification results (42.7%) and to accelerate the (simulation) speed with software processor models (35.4%)

The most common hardware configuration on the FPGA prototyping board consisted of between 4 to 9 clocks with the fastest clock running 50 to 125 MHz.

What interfaces were used to connect the software simulation and FPGA based prototyping/emulation/acceleration platforms? Not surprisingly, ARM-based interfaces were the most popular (56.4%), including ACE, AMBA, AXI, AHB, or APB variations (see Fig. 3). OCP was the choice interface for 17.3% designers. Many software developers just didn’t know what interface was used (36.4%).

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