By Ed Sperling
Japan’s SoC market, which has been a big market for advanced EDA tools, may be headed for a major consolidation. Renesas, Fujitsu and Panasonic are in talks to combine portions of their business in conjunction with the Japanese government’s Innovation Network Corp., according to numerous news reports. One particularly interesting addition to these changes in Japan: GlobalFoundries may buy Elpida Memory’s Hiroshima fab. Whether all of these changes create a larger and much stronger market for tools and services, or whether it actually shrinks, is a big question mark.

Cadence is collaborating with Samsung for 32, 28 and 20nm DFM flows. Key to the deal are pattern classification and search, CMP prediction, and both litho and yield analysis.

Synopsys won a deal with CSR for its Galaxy implementation platform. CSR makes everything from low-energy Bluetooth chips to GPS ICs.

eSilicon expanded its SerDes licensing deal with Avago. Under the terms of the deal, eSilicon will be able to include Avago’s SerDes cores—from 28nm to 90nm—in chips for the communications and storage markets. http://www.esilicon.com/press-releases/195-esilicon-expands-serdes-ip-licensing-agreement-with-avago-technologies-

Methodics rolled out a new release of its IP version-control product, aka Subversion, boosting performance and improving the distributed use model. As IP use and re-use grows, keeping track of IP in complex designs is turning out

By Ed Sperling
Mentor Graphics came under siege from corporate raider Carl Icahn, who claimed the company should be sold. Icahn’s group, which has bought up about 15% of Mentor’s stock, filed a proxy statement with the SEC to vote for its own officers on Mentor’s board. This could well be the most bizarre development in EDA history.

On a kinder and more productive note, Mentor won a deal with VIA Technologies, which makes low-power x86 processors. VIA is adopting the Calibre electrical rule checking product for electrostatic discharge analysis.

Synopsys is collaborating with Varian Semiconductor Equipment on process models for advanced logic and memory using Technology CAD models for cryogenic ion implantation. This is really interesting technology, but it makes it hard to explain at social gatherings what you do for a living.

Synopsys also introduced new technology for optimizing multicore systems. The company’s Platform Architect allows hardware-software partitioning and analysis well before the software is available. And it released a DDR memory controller that it claims has 30% lower latency and up to 15% higher throughput.

Apache Design Solutions rolled out its next-gen Chip Power Model for analyzing and optimizing the chip, the package and the system. This is a big step forward for advanced process nodes.

Tensilica introduced its DSP IP cores for LTE Advanced, which is the de facto 4G standard. Now you’ll be able to actually finish downloading mail before the cops pull you over and put your phone away.

Also in the LTE Advanced space, MIPS won a deal with Altair Semiconductor for its 4G LTE multithreaded processor IP.

A group of companies inside the SOI Consortium have created 20nm Ultra Thin Body Silicon on Insulator using fully depleted SOI. This is a major step forward for reducing current leakage. The wafers were provided by Soitec.

U.K.-based CSR is collaborating with TSMC on 90nm embedded flash process technology, IP and RF processes. Most of this stuff was being done at 180nm, so this is a two-node jump.

By Xiaodan Wang

The new message in China is integration, and that message is being spun and re-spun as companies jockey for position in a converged consumer world.

Case in point: When Frank Liang, Broadcom’s general manager for Greater China, released a 65nm chip that included Bluetooth, FM radio and GPS functionality two months ago, it hardly seemed like a major innovation. Texas Instruments and Cambridge Silicon Radio introduced a similar chip 10 months earlier. But as Liang put it, it’s not the time of releasing but integration quality that counts.  

Integration is Broadcom’s favorite topic these days, and with good reason. According to IDC’s latest statistics, combination chips will account for half of the market by next year. Companies with stronger abilities to integrate technologies and tackle interference issues when those functions are combined will win the market.

Within two years, all mainstream mobile phones will be embedded with GPS, triggering plenty of new opportunities for service providers, media and advertising. It’s no wonder that wireless chip vendors at the upper stream of the industry chain such as TI, CSR, Broadcom, Atheros and NXP are jockeying for position in this market.

The trend for “omnipotent” mobile phones also presents enormous opportunities and challenges for chip providers. Everyone sees the cake but not everyone can eat it. To make sure they’re in line, many companies are accelerating their acquisition plans so they can include more functions on chips more quickly. Despite clear signals that this was where the market was heading, Broadcom didn’t make a significant move in this direction until 2007 when it acquired Global Locate, then the world’s second largest GPS chip provider. Global Locate boasts leading GPS chip IP and powerful network-assisted GPS. Not surprisingly, that technology is in Broadcom’s new chip.

CSR, meanwhile, acquired Sirf Technology Holdings in February for the much the same reason. Interestingly, Sirf posted losses as an independent company, despite the growing popularity of GPS technology.

More integration ahead

Broadcom once claimed that it would release a new chip every two months. The product roadmap displayed by Broadcom when it introduced its new chip in February showed the new selling point will be WLAN connectivity. Questioned about this direction, Liang responded, “It’s good reasoning.”

There is widespread speculation in China that telecom operators will actively deploy “3G+WiFi.” 3G is used for the wireless communication in remote areas and between cities, while WiFi is the wireless Internet model of the highest price/performance within cities. Simultaneously supporting 3G, WiFi, Bluetooth and GPS is already a burgeoning trend. Broadcom, which is second only to Qualcomm as the 3G (WCDMA) solution provider, not to mention supplier for Nokia and Samsung, market watchers don’t expect to be kept waiting very long.

Scott McGregor, president and CEO of Broadcom, said his company is no longer a simple baseband chip provider, but a mobile phone chip provider. The difference is all about integration.

Xioadan Wang is chief editor of EEFocus, the Chinese affiliate of Low-Power Design and System-Level Design.

By Ed Sperling

Santa Clara, Calif.—Feb. 5, 2009—Design for manufacturing was a great buzz phrase for the past five years, but at 45nm and beyond DFM is becoming a necessary approach. As a result, differences between system-level designers and foundries have escalated from hypothetical to tangible.

Joe Sawicki, vice president and general manager of Mentor Graphics’ Design-to-Silicon Division, said during a panel at DesignCon that DFM has moved from the hype phase to the “slope of enlightenment.” He added that at the 45nm and 32nm process nodes it will become a design diagnostic requirement.

That also means DFM needs to be developed and tested like any other suite of tools in chip design. Kimon Michaels, vice president and general manager for DFM at PDF Solutions, said much of the data that DFM tools now provide are “overly conservative.”

“There is a need to provide DFM data that is accurate and practical for both the foundry and fabless companies,” Michaels said. He noted that the quantity of the data has not been a problem. There is plenty of available, but not of the quality necessary to avoid respins and ensure manufacturability of designs.

To a large extent, this depends upon cooperation between the fabless companies and the foundries that manufacture their chips. That cooperation has improved over the past several years, but there is still hesitancy on both sides to cement a partnership.

On the side of the developers, Mark Radford, Cambridge Silicon Radio, said questions remain about the data. “The foundries provide DFM kits and SPICE models and EDA provides tools,” he said. “But does the data statistically capture what we want and the level of detail we need?”

The answer to that question becomes increasingly important at every new process node. “At 32nm and 28nm, variability will be the dominant new challenge,” Radford said. “There will need to be DFM checks on third-party IP. All parties must work much more closely together. Right now there is competition and suspicion. We need to find a collaborative EDA, fabless and foundry working model.”

All of this concern—by EDA companies, foundries and end users—signals a change in how companies are looking at DFM. Walter Ng, senior director of design solutions at Chartered Semiconductor, said that until now there has not been a lot of adoption of DFM by customers.

“The big question now is, ‘Do customers see the value of purchasing additional tools,’” he said. “Through 65nm, we have not seen much impact.”

Ng noted that DFM will be most needed where there is the least amount of silicon—at the leading edge of development—and where variation tends to be greater because there has been limited learning on a new process. He said that variability decreases as volume increases and processes can be refined, but there is a challenge for companies looking to utilize the most advanced process nodes.

Among the problems is the cool air thermal limitation of 100 watts per square centimeter, said Jamil Kawa, group director of Synopsys’ advanced technology group.

“Voltage is not scaling properly anymore,” Kawa said. “There is also an increase in short-channel effects. Silicon trench isolation will be difficult unless we move to SOI (silicon on insulator) or finFETs.  In addition, planarization will become very critical.”