By Ed Sperling
Mentor’s Nazita Saye examines the shrink and pink phenomenon—and why embedded simulation pays for itself. This is like reverse engineering a shopping trip.

Cadence’s Richard Goering interviews Sigrity CEO Jiayuan Fang. Of particular note is the positioning for the PCB and 3D-IC worlds.

Synopsys’ Eric Huang looks at market dynamics for WiFi-AC routers and questions why no one will stand next to him—or even close to him—during a video shoot.

Vista Ventures’ Jim Hogan lays out the custom design market, what’s changing, and who’s doing what. The gang’s all here in a Cutom 2.0 posting on John Cooley’s DeepChip.

Mentor’s Mike Jensen compares engineering expertise to practicing to become a professional musician. The work seems to be steadier for most engineers, though.

Cadence’s Jason Andrews is back with some insights into the Linux kernel message system updates. If this is your area of expertise, take note.

Synopsys’ Mike Thompson questions why people are still using 8-bit processors when they could be using 32-bit processors for the same tasks. It’s like taking your riding mower out on the freeway.

Semico Research’s Jim Feldhan digs into the lack of innovation in the ultrabook market and why there should be lots of upside for this market. For anyone who has tried to seriously create content on a tablet or smart phone, that should be readily apparent—unless you have chicken fingers.

Mentor’s Colin Walls calls himself a professional enthusiast. That’s certainly easier to comprehend than embedded system coding for a non-technical person.

Cadence’s Yuri Tsoglin offers up some tips on using long expressions in e, which can result in coding errors even though they’re supposed to be legal.

Synopsys’ Mick Posner shows off a customer’s HAPS Christmas tree, decorated with fan shrouds. What do you tell them? Cool?

And in case you missed last week’s Low-Power/High-Performance Engineering newsletter, here are some notable blogs:

— Mentor’s Erich Marschner peels back the covers on the next version of UPF.

— Synopsys’ Cary Chin compares politics to engineering, and what it would mean for battery life.

— MIPS’ Rao Gattupalli looks at the role of virtualization in creating secure embedded systems.

— Apache Design’s William Ruby tackles how to debug your design for power.

— Nvidia’s Barry Pangrle observes that predictions about arranging atoms are finally coming true.

— Atrenta’s Mike Gianfagna looks at the end of the road map and what’s next.

— And Docea Power’s Gene Matter digs into power simulation and hardware emulation, and why not both?

By Ed Sperling
Cadence’s Pete Hardee predicts 2013 will be the year of dynamic voltage and frequency scaling. Considering these techniques are sufficiently tested and power budgets are now everyone’s problem, it’s hard to argue otherwise.

Mentor’s Colin Walls asks for and receives some suggestions about how to optimize code. This may be the best argument yet for open-source software.

Synopsys’ Karen Bartleson unveils OpenStand’s fourth principle: availability to everyone. But note: Available doesn’t mean free.

Speaking of standards, Cadence’s Richard Goering heaps much-deserved praise on standards champion Stan Krolikoski. His advice to all participants in future standards effort: Have lots of patience.

VC Jim Hogan, writing for John Cooley’s DeepChip, looks at variation effects in the age of atomic-level design and why a single atom now matters. Remember the good old days when a few extra atoms didn’t matter? So what do you do when you get down to five atoms and you need to cut that number in half?

Mentor’s Kamran Shah is looking for suggestions about what’s needed in debugging tools for embedded systems. Now is your chance to be heard. Operators are standing by.

Synopsys’ Eric Huang slams a WiFi-AC adapter for using USB 2.0, which means it will never be able to achieve advertised speeds. He also wonders why he looks as if he works at Target. Answer: At 1 a.m. on Black Friday, everybody does.

Apple to the rescue. IHS iSuppli’s Vinita Jakhanwal says Apple helped Korean suppliers overcome a weakness in the small display market. Apple undoubtedly was happy to help.

Cadence’s Qi Wang recounts some of the presentations at the Mixed-Signal Technology Summit in Japan and why this field is becoming so important. Answer: It’s profitable.

Synopsys’ Scott Knowlton examines the fine art of testing PCI Express 3.0. The upside is a huge performance boost.

And in case you missed last week’s System-Level Design newsletter, here are some standout blogs:

—Mentor’s Jon McDonald compares TLM modeling and RTL emulation, and why they’re only good for certain things.

—Synopsys’ Nithya Ruff draws analogies between the Sagrada Familia in Barcelona and embedded Linux.

—Cadence’s Frank Schirrmeister looks at how to choose the right engine, and why it’s necessary to define requirements up front.

—And Sonics’ Pascal Chauvet questions whether you can extend the tools that come with IP—and if not, why not?

By Ed Sperling
Mentor’s Colin Walls sings the praises of USB 3.0, but he says one of the problems is backward compatibility with USB 2.0. Time to hire more software engineers—if you can find any.

Cadence’s Richard Goering points to a 20nm test chip experience, replete with design rule changes and what impact they had on place and route, and double patterning. Despite all the all the talk about how double patterning isn’t a problem, it really is.

Synopsys’ Mike Thompson looks at the downside of bigger chips—more power and higher cost. What a difference a few years makes, when the focus was almost entirely on performance. But don’t get too hasty about shortening PPA by a letter.

IHS iSuppli’s Francis Sideco predicts mobile communications equipment—phones plus routers and other equipment—will remain strong, despite a soft global economy. Even if you’re unemployed, you need to talk to someone.

DeepChip’s John Cooley looks at top core frequencies and NoC usage. Of particular note are the reported problems in implementing on-chip networks.

Mentor’s Mark Laing looks at keeping multiple sites in sync for managing process preparation. A single database is one solution, but it also can cause other problems. Think about the recent power outage in New York City.

If you use Cadence’s Incisive simulation, Sumeet Aggarwal has some tips on how to boost performance, and deep links to go with them. Put on another pot of coffee. It’s going to be a long night.

By Ed Sperling
Synopsys’ Karen Bartleson unveils the second principle of OpenStand: Adherence to principles, or more accurately, adherence to fundamentals. It’s a good rule for all standards bodies to follow.

Mentor’s Colin Walls finds advantages in simplicity, like how fast an LED blinks. Didn’t Samuel Morse have a similar idea?

Cadence’s Richard Goering looks at design beyond 14nm and what’s going to change. Quick summary: Lots.

Semico’s Joanne Itow ponders whether economic downturns really create more pessimists, or whether they simply get more attention in bad times? There are a lot of cross currents and unanswered questions here, but it’s good food for thought.

Mentor’s Dennis Brophy examines the standards efforts being developed around the Internet of Things, aka IoT. If ever standards were necessary ahead of time, this is the place.

Also in the standards realm, Synopsys’ Hezi Saar examines a new acronym—time to standard. The best measurement tool for this may be a blood pressure monitor.

Cadence’s Jason Andrews finds insights in the trash bin, thereby proving data can neither be created nor destroyed, only changed. This one involves mount –o loop for virtual platform simulations.

IHS iSuppli’s Andrew Rassweiler looks at why the ARM platform is so strategic for Microsoft/s RT. Hint: Microsoft hardware. So is an IDM that started out developing software any less capable of taking market share than one that started out in the hardware business? And did you ever really wonder why all those Microsoft stores were being built everywhere?

Synopsys’ Helene Thibieroz interviews a couple of ST experts on how they optimized their validation flow. Anything to reduce validation/verification time is a good thing.

DeepChip’s John Cooley cites a Calypto survey about what technologies are most important to integrate with high-level synthesis. Answer: RTL synthesis and power analysis/optimization. It appears that engineers are looking for the big picture to make architectural tradeoffs combined with real measurements to back up their decisions.

Mentor’s Andrew Patterson looks at the Smart Society with smart applications running on nearly everything. This sounds like a really interesting gee-whiz kind of gathering.

Cadence’s Nir Hadaya digs deep into the new C interface for Specman. If you use this stuff, grab a cup of coffee.

Synopsys’ Eric Huang has discovered two wireless WiFi routers that support USB 3.0. It’s starting. Don’t sleep. Must warn others.

By Ed Sperling
Mentor’s Michael Ford concludes there’s nothing like personal interaction and sharing horror stories—as well as workarounds—to further the knowledge base. There are some things the Internet just can’t improve upon.

Cadence’s Richard Goering digs into the next SystemVerilog Language Reference Manual and how it will support real number modeling to provide chip-level simulation with analog values. That would be a big boost for mixed-signal design.

IHS iSuppli’s Jagdish Rebello examines the U.S. government’s warnings on ZTE and Huawei and what it means for the two companies and the telecom industry. What’s particularly noteworthy is that the U.S. government isn’t alone in its criticism.

Mentor’s Patrick Carrier notes that many electromagnetic interference (EMI) problems on boards occur with unintentional creation of antennas. That can happen inside a chip, too. Watch your loops.

VC Jim Hogan, writing in DeepChip, drills into on-chip networks and why they’re not just a simple bus matrix interconnect. There’s also a good compendium of on-chip communication network terminology.

Independent blogger Gaurav Jalan looks at workarounds in verification and how to make debugging more efficient.

Mentor’s Mike Jensen has a new toy: a remote-controlled Mini Cooper. What’s unclear is whether this is actually a toy, or whether he’s planning to use a real car like a drone. Mileage may vary.

By Ed Sperling
Mentor’s Andrew Patterson looks at one of the most interesting facets of the Internet of Things—cars that are connected to the Internet and to each other. Unlike your smart phone, at least if something goes haywire you’ll be able to disconnect the battery and reboot. But imagine what happens if someone hacks your steering system.

Synopsys’ Navraj Nandra digs into the shift from DDR3 to DDR4 and how that differs from DDR2 to DDR3, as well as the reason why it’s unlikely we’ll ever see DDR5. Get ready for the rise of TSV (no pun intended).

Cadence’s Richard Goering reports on a panel about mixed-signal gaps and solutions, a speech by TI’s Chris Collins about mixed-signal tribulations and an update about a universal data transfer standard.

DeepChip’s John Cooley looks at the legal shenanigans that have erupted between Synopsys and Mentor on rumors that Synopsys is looking to buy EVE. It sounds like a resurgence of the old litigious EDA, when legal firms could count on a steady revenue stream.

Mentor’s Mike Jensen examines an interesting law passed by the state of California that allows licensing of autonomous vehicles, following on the heels of similar laws passed by Nevada and Florida. We’re surprised the taxi driver union hasn’t objected. You’ll be able to call your own car to pick you up—and send it home after it drops you off.

Synopsys’ Helene Thibieroz interviews Tim Hollis, chairman of the upcoming (April 2013) Workshop on Microelectronics and Electron Devices. It looks as if he drives a Porsche, too.

IHS iSuppli’s Vinita Jakhanwal compares the LCD display of the iPhone 5 to the Galaxy S III, which is based on AMOLEDs. In a nutshell, there are pros and cons to each approach—particularly when looked at over time.

And in case you missed the most recent issue of the System-Level Design newsletter, here are some standout blogs:

—Mentor’s Jon McDonald says that different versions of tools can affect whether a design is painful or straightforward.

—Cadence’s Frank Schirrmeister compares a tree-house project with designing a complex SoC.

—Synopsys’ Nithya Ruff shows the benefits of early software development for both hardware and software.

—Sonics’ Frank Ferro looks at why system performance is more than the sum of the cores and memory.

—And Arteris’ Kurt Shuler digs into the limitations of SMP and why AMP has a bright future.

By Ed Sperling
Cadence’s Richard Goering reports on a keynote about the Hybrid Memory Cube and why it’s destined to revolutionize system memory. The comparison to DDR4 is especially interesting.

Synopsys’ Navraj Nandra examines the Universal Flash Storage standard from JEDEC and what it will mean for next-gen smartphones and tablets—better performance and less power. No surprise there. His colleague, Hezi Saar, takes a similar look at the standard and how that will impact eMMC growth.

Mentor’s Colin Walls looks at the past and present of embedded software development tools, citing a report by VDC Research that shows commercial standalone tools are in trouble. You can blame open source development for that one.

Semico’s Tony Massimini looks at Intel’s aggressive technology roadmap and concludes there’s a lot of interesting stuff ahead. Fasten your seatbelt.

Cadence’s Sathishkumar Balasubramanian digs into ARM’s next target: the microcontroller market. Consider this a war on another front, but this one has lots of competitors instead of one big one.

Synopsys’ Eric Huang has discovered a nifty controller for playing Angry Birds. Be careful where you point this thing.

DeepChip’s John Cooley looks behind the numbers on the leapfrogging game going on in the emulation market—and the fallout as defined by Gary Smith.

Mentor’s Nazita Saye compares the weather in England with the world economy—gloomy, wet and cold. Well, not everywhere. Check out the lines at the local Apple stores.

Speaking of Apple, Cadence’s Axel Scherer just got his hands on the new iPhone 5. Like many others, he likes it, which explains the long lines.

But as IHS iSuppli’s Andrew Rassweiler has discovered, one thing that hasn’t changed with the new iPhone is the supply chain. Most of the suppliers are still the same ones who churned out parts for the last version. This is like steady-state economics—at least so far. Note who made the A6 processor.

AMD’s Vikas Grover, writing for Synopsys’ VMM Central, looks at ways to connect SystemC to UVM-based verification environments. If you work in verification, take note of this one.

Mentor’s Andrew Patterson attended Freescale Technology Forums in Bangalore and Beijing—each with about 1,500 designers in attendance and very strong interest in automotive electronics. Things should only get more interesting from here.

Synopsys’ Eric Huang has discovered an unusual T-shirt message pertaining to USB. He confesses that he doesn’t understand the message, and frankly we’re not sure, but our suspicion is this person’s initials are USB.

Cadence’s Richard Goering reports on a MemCon keynote by Cadence SVP Martin Lund about cloud and mobility and how both areas are forcing changes in computing, the interconnect, and storage.

DeepChip’s John Cooley looks the “negotiations” between TSMC and Apple and Qualcomm’s over dedicated 28nm fabs. His insights into the origin of this story are particularly interesting. Who leaked it?

Speaking of Apple, what’s the bill of materials in a new iPhone 5 worth? According to IHS iSuppli’s Andrew Rassweiler, $199 plus another $8 for manufacturing. Nice markup.

Mentor’s Mike Jensen questions whether we need the latest and greatest electronics—like an iPhone 5 or a Chevy Volt—or whether we can get to the same place more simply. These are questions the operations managers at companies certainly will be asking.

Synopsys’ Navraj Nandra examines the advantages of DDR4 vs. DDR3. Lower power, better performance and cheaper—what more can you ask for?

Cadence’s Jason Andrews digs into using a network file system with the Xilinx Zynq-7000 virtual platform. Sharpen your pencils.

Independent blogger Gaurav Jalan looks at the bug communication cycle, from identification to solution, and where it needs to be improved.

Mentor’s Colin Walls is preparing for two panels on RTOS performance and power management in embedded systems. These are both great topics, and he’s offering up his slides for anyone who’s interested.

And in case you missed the most recent Low-Power/High-Performance Engineering newsletter, here are some blogs worth noting:

—Synopsys’ Cary Chin examines the new iPhone 5, and wonders whether Apple could have spared some extra battery.

—Mentor’s Dina Medhat looks at improving the reliability of a design with power-aware IC checks.

—Cadence’s Luke Lang digs into low-power test strategies and some best practices to maximize yield and still keep costs down.

—Apache Design’s Matt Elmore unveils part one of his series on signal integrity’s growing complexity.

—Atrenta’s Mike Gianfagna offers up some tricks to improve the value of RTL power estimation.

—Tensilica’s Chris Rowen recounts 25 years of the microprocessor and what the future will look like.

—MIPS’ Mark Throndsen questions design priorities for next-gen connected CE devices.

—Docea Power’s Gene Matter opens a new chapter in power modeling—one that’s scenario-based.

—Independent low-power architect Barry Pangrle analyzes what makes the IBM Power7 processor so interesting from an energy efficiency standpoint.

—Mimasic’s Bhanu Kapoor takes a look at the benefits and challenges of near-threshold computing, which is something you’ll be hearing a lot more about in the future.

By Ed Sperling
Mentor’s Nazita Saye looks at the wind resistance of dreadlocks, the best way to design a bicycle and why male athletes shave their legs. This is the kind of stuff aerodynamics engineers think about.

In case you haven’t noticed, there aren’t a whole lot of young engineers running around the hardware industry. How do you change that? Synopsys’ Karen Bartleson and Rich Goldman talked with Xilinx’ Patrick Lysaght about engineering education.

Cadence’s Joe Hupcey interviews his colleague, Bin Ju, about formal technology and what’s the best way to adopt it. Check out the blowing vegetation in the background. It looks as if a storm is moving in. Maybe it is.

Independent blogger Gaurav Jalan applies a handful of laws—Newton’s, Murphy’s, Moore’s, the law of natural selection—to verification. The reverse might also be interesting.

Mentor’s Robin Bornoff pins part five of his epic on the best location for a radiator in a room to a job interview. Apparently reading comprehension skills are required.

Synopsys’ Helen Thibieroz talks with Rambus’ Bing Chuang about speeding up DFT logic and timing verification.

Cadence’s Jason Andrews rolls out the latest installment of his Ubuntu OS epic, this one on improving fonts for SimVision.

DeepChip’s John Cooley looks into rumors about Synopsys’ next acquisition target and what’s behind it. You never can tell who’s just talking and who’s really bargaining—or whether anything will happen even if both parties are serious—but it’s an interesting snapshot of the competitive stakes and who’s got what.

Verilabs’ JL Gray ponders the possibility of a $10,000 ASIC. Break out the spreadsheets and sharpen the pencils. This is going to be a long night.

Mentor’s Colin Walls peels back the covers on evaluation boards for anyone doing embedded software development, offering several possible uses and advantages for choosing this option.

Synopsys’ Navraj Nandra looks at what it takes to bring non-volatile memory IP up to automotive quality standards.

Cadence’s Richard Goering interviews Martin Lund, who just jumped ship from Broadcom’s network switching group to Cadence. You’ll find out why.

By Ed Sperling
Mentor’s Colin Walls points to a recurring problem in software—keeping up with the capabilities provided by chipmakers to keep power to a minimum. Classify this one under sleep disorders.

Synopsys’ Helene Thibieroz offers seven tips to improve your Verilog-AMS model. The last one is priceless: Make models as simple as possible. It’s not always so easy, though.

Cadence’s Richard Goering digs into finFETs—the opportunities to reduce power and improve performance, as well as the rather significant challenges for designers. How many dimensions can you design in?

Semico’s Joanne Itow looks at manufacturing and MEMS, which she’s calling M&Ms. Well, they both come in a package. The candy probably costs more, though.

DeepChip’s John Cooley captures a candid Joe Sawicki from Mentor (is he ever not candid?) on a DAC panel talking about subjects ranging from Thomas Jefferson to Carl Icahn to Calibre killers.

Verilabs’ JL Gray examines the need for accurate project schedules and how to get there—or not get there. Make sure you check out the “Three Miracle Law.”

Mentor’s Michael Ford weighs the content in a magazine and software program, and how little of the content is useful. Maybe they should charge 5% and get rid of the filler.

Synopsys’ Eric Huang looks at the introduction of Windows 8, which comes with USB 3.0 support. There had to be a hardware connection there somewhere.

Cadence’s Reuven Naveh explores why constraints get ignored—and how to fix the problem.