By Ed Sperling
Mentor Graphics rolled out a new Eldo Premier SPICE simulator that it claims will improve performance by 20x and capacity by 10x. Support for the Questa mixed-signal verification environment will be added in the near future.

Cadence rolled out its DDR4 IP solution, building on the acquisition of Denali last year. The solution includes hard and soft PHY, controller IP, memory models, verification IP, tools and methodologies, as well as reference designs.

eSilicon inked a deal with TranSwitch to manage the supply chain for Transwitch products and to collaborate on cost optimization of new products. The deal is similar to one that eSilicon signed with Pixim last summer.

MIPS launched a new developer community for software developers working with Android, Linux and other applications for MIPS-based hardware. MIPS also said that Broadlight’s third-generation gigabit passive optical network processor family will be powered by the MIPS 74K core.

By Ed Sperling
Mentor’s Colin Walls takes a look at classes of drivers, in which the words class and driver are vague that the subject “provokes” discussion. No wonder communication is so difficult between hardware and software engineers. Even within these groups they don’t communicate effectively.

Cadence’s Jason Andrews returns with a piece about system-level design confusion and how to conquer it. Hint: Study the diagram.

Synopsys’ Chris Caerts questions whether Android will remain open and free. All indications are yes, but you never know.

Semico’s Joanne Itow examines at the secondary equipment market, which is an area few outsiders know very little about. This is the machinery used to make a variety of mainstream semiconductors, ranging from microcontrollers to industrial sensors, which are a critical part of the semiconductor market. It’s also a market where there are no clear winners so far.

Mentor’s Robin Bornoff, who decided that a toaster/PC combination would be a good use of leaky current, actually tried to order one of these devices online. He should have checked the calendar.

Cadence’s Richard Goering questions whether system-level design is creating a new class of engineer. From a knowledge standpoint, the answer is yes. From a salary standpoint, the answer is probably not.

Qualcomm’s Riko Radojcic sounds off on 3D standards in an interview with Ed Lee and Liz Massingill. This is a great update of what’s happening behind the scenes and what chipmakers are really looking for.

Synopsys’ Hezi Saar says glasses-free 3D TV. Sounds like even massive hype couldn’t sway the market in the first rev.

An anonymous Denali user, writing in John Cooley‘s DeepChip, contested the results of a quiz conducted by Mentor Graphics. It turns out the initial calculations were off by a bit. Literally.

Synopsys’ Yaron Ilani unveils part 2 of his verification insights about cool things you can do with DVE. So how many parts will this actually be? And how many other things can you do with DVE?

By Pallab Chatterjee
At the most recent Denali Memcon, there was a panel discussion and debate about the future of DRAM and possible successor technologies. The discussion was moderated by Cadence’s Steve Leibson and featured Bob Merritt of Convergent Semiconductor, Barry Hoberman of Crocus, Ed Doller of Micron and Marc Greenberg of Denali/Cadence.

The topic of the discuss was based on the growing trends in power efficiency, process scaling, and data retention as a changing environment for DRAM’s use in enterprise applications. New technologies have come and gone the past 50-plus years in solid state memory, and the debate about DRAM’s longevity has come up several times in the past. The presentations an positions of the 4 panelists were quite different, and ran the spectrum from use model, to business model, to technology issues.

Bob Merritt of Convergent started with the changes in the enterprise space that are driving the discussion. The unifying memory architecture from the ’80s was driving systems to use a central memory store for both processing and graphics memory. However, there is a shift in the type of data being created as the enterprise moves from a data-processing model to a multimedia model. As a result, graphics memory (GDDR) has become the only application for which this specific type of DRAM is still being used.

Also, the data processing has shifted from the corporate- and PC-centric side to the customer-centric side with mobile and smart devices. This has led to the conclusion it is not DRAM itself that needs to be replaced. It is the business model associated with DRAM. The historic model was based on a commodity model rather than a value-add model, which limits the ability to market into new and diverse markets.

Barry Hoberman of Crocus Technology presented the technology case for Magnetic RAM or MRAM. The cost per bit for MRAM is not on par with DRAM at this time, but in the near future it will be reaching cost parity as a solution with a DRAM/control logic/battery for NV applications. As DRAM applications stretch further in the consumer product space, additional features related to SRAM and NVRAM (flash) become more prevalent. From an embedded use perspective, MRAM processing is more compatible and less of an overhead than FLASH compared to CMOS. Hoberman concluded that with the shift in application space, MRAM will be a cost-effective and viable technology for systems.

Ed Doller of Micron, gave an overview of five technologies – FeRAM, MRAM, FBRAM, TRAM, and PCM. The FBRAM and TRAM technologies are not in production today, so their viability for being a near-term replacement is low. FeRAM and MRAM, while in production, are not application-compatible with DRAM and are not scalable to the same degree. This leaves Micron with the PCM technology it recently acquired from Numonix. The technology is in production and is scalable, but the use and application are not fully DRAM compatible. Doller said there is no need to replace DRAM immediately, but a replacement will be needed within the next five years.

Mark Greenberg from Denali/Cadence took the position that DRAM won’t be replaced at all. From its start in the 1970s the technology has undergone over 50 design iterations. The technology and concepts behind the DRAM date back to principles and components from the 18th century (capacitor) and early 20th century (transistor) and are not outdated. The cost of the technology is very low for the end product on a per unit (bit cell) basis. And while there are process challenges, there is no reason to believe that these are insurmountable as logic processes have similar challenges. And finally, Greenberg asked non-believers to show him a silicon technology that was superseded solely on continued manufacturability. He said DRAM’s demise is premature.

The overall summary from the audience questions was that as systems applications change, there are memory options, but DRAM will still play a major role

By Ann Steffora Mutschler
With the amount of IP blocks being integrated in SoCs today – in some cases as many as 100 blocks in a single chip – SoC design methodologies are shifting to address the new challenges this complexity brings. The good news is that these integration challenges has put the spotlight on the issues—along with the skyrocketing development costs for the creation, qualification, acquisition and integration of IP, which can account for as much as 25% of the total hardware design budget.

“There is an increasing amount of external IP being used and things are moving toward a printed circuit board-type methodology where we have large customers that are making several IPs and buying the rest, but we also have some smaller customers that only make one IP (the differentiator of their chip) and everything else is bought,” noted Charlie Janac, chairman, president and CEO of Arteris.

Design project managers are struggling to know how quickly that SoC can be assembled, what the cost is of the assembly, and how quickly the verification can be complete.

“The challenge is to quickly integrate IP that has multiple protocols. IP can be wrapped to chase a protocol, but that introduces unwelcome latency and risk. So you really want to use the native IP protocol that the IP comes in because that’s what is proven,” Janac said.

Further quantifying the situation today, Neil Hand, director of product marketing at Cadence Design Systems pointed out that “at 65 nm about a quarter of a $45 million design spend was spent on qualification of IP, which seems a little big but other customers tell us that for every dollar they spend on acquisition of IP they are spending $2 to $3 to make it work.”

The problem is “there is still a complete lack of consistency between the IP providers. There is no consistent set of standards for deliverables or consistent standards for quality or even what it means to be IP. Some vendors will say it has to be silicon proven when all they’ve actually done is put it in a test environment,” he said.

“Designers spend a lot of time creating the extra views, the extra models, and the extra things to integrate into their design before they can even get it to work. Even if you’ve got “silicon-proven IP” it doesn’t mean it works it all works well together,” Hand pointed out.

Mike Gianfagna, Atrenta’s vice president of marketing, believes this trend spells opportunity for EDA. “The shift from authoring to integration demands a new set of design tools to support reuse and integration. IP-XACT is one standard that is helping to drive this. There are others. At the center of the shift is the need for a rapid assembly, prototyping and validation tool set that works at a high level of abstraction on designs that are not yet complete. The need to interface to the software developer is also present here. These new tools will be in high demand, and should command a good average selling price. EDA hasn’t seen new budget dollars for quite a while – this new trend will break that streak.”

Cadence’s answer to this is its Open Integration Platform, whose stated goal is to reduce SoC development costs, improve quality and accelerate production schedules by concentrating on an application-driven development process and encouraging open, standards-based, collaboration within an ecosystem of production-proven semiconductor design companies, IP providers, foundries, service providers, EDA vendors and assembly houses. It is part of the company’s EDA360 view of next-gen, application-driven development. Cadence’s recent acquisition of Denali Software fits into this, as well.

The platform includes integration-optimized IP from the company and its ecosystem partners, an Integration Design Environment along with integration services. Cadence mixed-signal (analog and digital) design, verification and implementation products and solutions are the underpinning of the Open Integration Platform, the company said.

At the same time, while it has not been stated directly, Synopsys, with its acquisition of Virage Logic, is also expected to come out with IP subsystem products of its own at some point, possibly arranged around a sophisticated interconnect. ARM and Posedge also provide IP subsystems.

What does complexity mean for the interconnect?
While design teams have been using third-party and internally-developed IP in SoC designs for at least 10 years, what’s changed is that over time they have put more and more IP blocks onto the SoC. Today for high-end parts there could be upwards of 100 blocks on the SoC, according to Rich Wawrzyniak, senior market analyst for ASIC and SoC at Semico Research.

“The connectivity between the IP blocks is absolutely critical because the advantage of the SoC may be that you can put all of these blocks on the same chip to get the performance, but if the interconnect is incorrect, improper or not efficient enough you lose all of the advantages that you just gained. The biggest issues on these things are the type of bus architecture you’re going to be using,” said Patrick Soheili, vice president of marketing and business development at eSilicon.

Technical issues surrounding the interconnect abound, including IP re-use; efficient transport (how quickly the data can be moved around the chip); memory bandwidth issues; the number of gates needed, and routing congestion.

There is also the issue of SoC services. Here, Janac believes the industry has been confused about where those services go – whether they belong in the IP, the memory controller or in the interconnect. “The network-on-chip (NoC)-type interconnect handles the data transactions (signal packetization), which gets the SoC data onto the network and the wiring and transport services which move the data all over the chip,” he said, noting that Arteris’ NoC supports SoC services—higher level functions that control the operation and performance of the SoC. SoC services include quality of service, security, power domain management, frequency domain management and software debug.

“These higher-level functions have an impact on SoC performance, power consumption, security and software quality and belong in the SoC interconnect because they represent SoC system-wide functions that need to go to many parts of the chip. In a multicore SoC, the interconnect is the only part of the chip that sees all of the data traffic and thus is the best place to consolidate these higher level service functions,” Janac explained.

“The NoC-type interconnect is ideal for implementing these services it implements predictable networking techniques with relatively modest number of interconnect wires and communications control logic. Individual IPs such as memory controllers and processors no longer see all of the data operations that occur in an SoC and so they not the best place to try to implement these types of SoC wide functions,” he added.

Particularly on the road to 28nm, interconnect issues are a key roadblock along with IP readiness. “What’s challenging about 28nm is obviously the complexity, the readiness, the availability of the IP; the readiness of that IP becomes a major Achilles heel of getting to 28nm,” Soheili said.
In order to reduce the risks, costs and time to market for its customers headed for 28nm, eSilicon is planning to take a platform-based approach in which it would pre-design SoCs.

“This works in particular vertical markets where a customer can look to this platform that could be a certain percentage of the design already completed. Then, the customer’s value-add is in selecting and providing the software stack, the applications, the drivers all the way up to the system-level, along with marketing and channels and getting the customers. This could be done in very large volume markets or could be in smaller volume/higher margin markets or anywhere in between. The smarts go in finding a superset and going after vertical markets so you do the job once, you get through the silicon validation process and the design process and then harden it as much as you can before the customer comes in. Now the NRE is down, the engineering time and the risk are down, the time to revenue is down.

To be sure, this is an interesting time in the industry as design complexity and vendor consolidation bring up new challenges to address.

By Ann Steffora Mutschler

The EDA industry has seen a number of large acquisitions as of late, most notably of Denali by Cadence, as well as CoWare, VaST and Virage Logic which were acquired by Synopsys, but just what impact does this realignment have on the biggest EDA customers? Commenting on these changes is Jean-Marc Chateau, director of system platforms and tools at STMicroelectronics, the world’s fifth largest semiconductor manufacturer, in this exclusive System-Level Design interview.

SLD: As one of the industry’s largest EDA tool customers, how do you view the recent acquisitions?
Chateau: It is very interesting what is happening. It looks like all of the big players – Cadence, Mentor and Synopsys – are waking up to say, ‘We should change speed on ESL and try to create a market,’ which has always been so far in the $200 million range. Synopsys has been very aggressive, first with Virtio [in 2006], then with CoWare and VaST. It’s quite interesting because it can bring consolidation around pieces that were not fully interoperable. There are positive aspects of SystemC but there are things lacking in the standard – there are still missing pieces. So every company including semiconductor companies – not only tool and IP vendors – they have been obliged to build their own extensions. The fact is that companies like CoWare and Synopsys have to solve the interoperability between models and tools of what they have acquired because it’s not enough to be SystemC compatible. It will be positive because they will have to solve the problem for us.

But on the negative side, the risk is that they will build a closed solution and try to milk the user community—especially the software community—with a proprietary solution to which, when you enter you can not get out, and you have to follow all the flow with their tools. So we are looking at what will happen. I believe it will take Synopsys two years to really consolidate a single modeling solution out of what they are buying today. Cadence is more on the IP because Synopsys was very strong on IP; Cadence was stronger maybe on tools and they are trying to complete their solution. Mentor has a lot of pieces as well but still not very coherent and consistent all together.

SLD: Given that ST had a development relationship with CoWare, will the acquisition by Synopsys change ST’s relationship with the companies in terms of ESL development?
Chateau: In terms of ESL, ST has a long history of internal development. We have quite a large team developing solutions for all the divisions of ST and ST-Ericsson and this started more than 10 years ago. We have been pioneering ESL, especially pushing for open standards such as OSCI TLM. We have been chairman of the board at the beginning and also involved with SPIRIT IP-XACT for assembly of different IPs into SoC and subsystems. Therefore, we have an internal solution that is widely used for complex SoCs in TV, set-top boxes and mobile phones. The usage we have of CoWare is marginal – focused on the processor. We use technology to manage the coprocessor and to generate ISS and also to configure the coprocessor attached to a flexible processor. We have our own internal processor called XP70 – Tensilica-like, let’s say – and CoWare is our supplier in terms of technology to configure this processor. It is widely used in many applications such as set-top boxes and mobile phones. But this is very marginal.

There is another usage of CoWare in ST-Ericsson, which comes from the legacy of the acquisition of NXP Mobile and Ericsson. They were using CoWare especially in NXP so there are some platforms or subsystems that are using CoWare models, but fortunately they followed the TLM standard and we have been able easily to build a completely interoperable platform from the various pieces in ST-Ericsson. So for us, CoWare is relatively marginal and the fact that it was acquired by Synopsys is not impacting us much.

SLD: Do you sense from what you hearing that the top EDA vendors understand users’ biggest challenges in ESL?
Chateau: It is much better than it was, I would say, because we have been talking with them for years on that and there is really a change today in those three companies. I see, for example, Cadence has launched EDA 360; Synopsys of course will have to merge Virtio and CoWare into one platform, but it may leave it aside for the moment and maybe merge it later. And Mentor, they try to put together what they have in a consistent way. The verification part was a bit forgotten before but it is more part of it.

What they have not understood in the past is that the cost of modeling is very high and we cannot afford, by any means, to duplicate the platform for several flavors. We have system-level platforms that require a higher level of abstraction above RTL. You have the architects that need performance from this platform with certain flavors. There are verification people, mostly the sub-verification people, who require some testbenches at a high level. You also need to have a virtual platform for software development. The three cases would require in theory different approaches of modeling, but we cannot afford this so what we did 10 years ago was to make a decision and say, ‘We are going to define one way to do models and we have to apply it all of the categories,’ because it is always difficult to populate fully in TLM a complete system platform with models. To do that three times – no way. I think if you look at all of those companies – VaST, CoWare, etc. – they are focused on either verification or software virtual platforms or architecture investigation, but not the three of them together. Now, it seems to me, it is my perception that they need to tackle all, having in mind that the biggest population is software development. But if you look at the software budget we put on the shoulder of the software designer, it is very light in terms of CAD. We buy very few tools; we mostly rely on point tools so to introduce the same business approach as in hardware design with CAD seats that cost several $10Ks will not work in the software world. I still think they dream a bit.

SLD: With Synopsys acquiring Virage and Cadence acquiring Denali, how do you view this consolidation?
Chateau: To me it was very obvious Synopsys was missing the embedded memory part in their portfolio. With Virage they don’t target anything but that part. I don’t think they are very interested in the other part. They will have to make a choice between the differentiation on parts I’m sure. For Denali and Cadence, it is a little bit different because Cadence is still very weak overall in its IP portfolio, so I have no comment on this. Denali is strong in models so that can be a good asset for the company to position because they have acquired also a lot of companies for VIP and transactors and this is key to build an offering in ESL. So I think they have a good strategy, which is a lower cost strategy than what Synopsys did. So, we’ll see.

SLD: Does ST mind that the IP it purchases come from the tool provider?
Chateau: We preach for interoperability and we are very active in standards for that purpose, so we would like to deploy the IPs with the tools as much as possible. This is why in OSCI we are very much attached to the fact that there is an open source simulator that you can run with any models from any IP vendor to see if it is really following the standard. Of course the companies would like to kill this and do only paper for the standard because they would like to make money out of simulators in Mentor, Cadence and Synopsys, and CoWare before the acquisition. I understand, but we are fighting to keep that preference because TLM OSCI SystemC cannot be as strict and non-ambiguous and RTL-like as Verilog and VHDL. You really need to have an open source to check interoperability. The higher level you go, the more reference you will need like this, and therefore, our wish is to be able to buy IPs wherever we want independently of the tools. Today, if you look at what we buy … our biggest supplier is Synopsys, but it’s not because of the tools.

By Ed Sperling
Cadence completed its acquisition of Denali, moving the company squarely into the IP business for what amounts to an all-out IP arms race. Several sources have confirmed Cadence bid for Virage Logic first, but was outbid by Synopsys. Cadence subsequently made the $315 million offer for Denali. The selling price has lots of companies hanging out a “for sale” sign. The big question is who’s next?

ARM, the Common Platform companies (IBM, Samsung and GlobalFoundries) and Synopsys introduced a 32/28nm high k/metal gate that is “vertically optimized.” Exactly what “vertically optimized” means is something of a mystery, however. You won’t find any additional information about this in the release or in any of the links.

Mentor Graphics and Synopsys both updated some of their top tool suites at DAC, not to mention their relationships with foundries. Mentor is collaborating with GlobalFoundries on an advanced design and manufacturing flow using Calibre.  It also added verification, extraction and DFM support for TSMC’s AMS 1.0 flow, as well as ESL, integrated design, and manufacturing closure for TSMC’s Reference Flow 11.  In addition, Mentor’s Olympus SoC place and route is now supported by X-FAB.

Synopsys improved its PrimeTime performance for static timing analysis, migrated its Ly-nx pre-validated design environment for the Common Platform’s 32/28nm nodes. It also introduced a Galaxy characterization solution for standard cells, complex macros and memories, and it added StarRC custom 3D extraction for sub-45nm designs.

Cadence also provided its contribution to the Universal Verification Methodology, aka UVM—an open-source reference flow for SoC verification.

Atrenta introduced SpyGlass-Physical for physical implementation modeling. There was a lot of talk about tradeoff analysis and what-if approaches at DAC this year.

http://www.atrenta.com/atrenta-news/96.news

AMD inked a deal for Apache Design Systems’ power supply noise and reliability sign-off tools. Considering the close relationship between AMD and GlobalFoundries, this becomes particularly interesting.

Cadence plunked down $315 million in cash for Denali (minus $45 million in cash that Denali has sitting in the bank), moving Cadence squarely into the IP business. Whether this is a good move or not is pure speculation. Denali is a private company. What is memory modeling IP worth? And more to the point, what is it worth to Cadence? On a side note, will the annual Denali party at DAC now become the Cadence party?

Arteris boosted its global distribution, naming a slate of execs to handle sales in various geographies and inking deals with distributors outside of North America and Europe. This is how a company that develops interconnects makes connections. It’s also a sign that it has reached critical mass.

Synopsys is collaborating with SMIC on USB PHY for the foundry’s 65nm low leakage process. Don’t count SMIC out. Looked at differently, it’s now a three-way race between Abu Dhabi (Global Foundries), Taiwan (TSMC and UMC) and China for commercial semiconductor manufacturing.

Apache Design Systems introduced its PathFinder tool to locate potential electrostatic discharge problems all the way up in the place-and-route phase of chip design. ESD is becoming a big problem at advanced nodes, and is expected to be a persistent thorn in 3D IC stacking.

Actel made a full portfolio of IP cores available for its SmartFusion mixed-signal FPGAs. This is an interesting way of reducing time to market while still allowing for modifications and future derivative chips.

Cavium Networks has adopted MIPS cores for its Octeon II multicore processors, which play across a wide swath of markets. Cavium, which started out making security chips, bought embedded Linux vendor MontaVista last year and has been pushing heavily into the Internet infrastructure world.

From the bellwether standpoint, just in case you haven’t come to grips with the fact that a recovery is well under way, TSMC’s April sales were up 6% from March and 50% from April 2009. What a difference a year makes.

By Geoffrey James

Intellectual property was once seen as the new growth market for EDA. Dozens of firms – large and small – jumped on the IP bandwagon, attracted to the “build once, sell many times” business model.

“As late as 2004, the industry was still thinking that as much as 90% of SoCs would be reused IP,” said EDA consultant Gary Smith.

The IP segment, however, hasn’t proven to be a profitability panacea, especially for smaller firms. There are the big players—Synopsys and Mentor in the EDA world, ARM and MIPS on the processor side, and Virage Logic in a variety of markets, which has broadened recently with the acquisition of ARC and NXP’s IP portfolio. There also are players like Rambus and Denali that have staked out strong market presence. For most other companies, though, IP has been more troubling than it has been worth, as evidenced by the continued consolidation in this sector.

For one thing, IP never achieved the promised level of penetration. Reusable blocks comprise only a little more than two-thirds of today’s typical SoC, according to Smith. Perhaps as a result, since 2007, IP revenue has stalled at or around 20% of total EDA market. (See figure 1.)

Source: EDAC

But there have been other problems as well, especially for smaller firms. Far from an easy way to make money, IP has become one of the most harrowing segments of the EDA market, with five major financial and technical challenges:

CHALLENGE #1: New IP always requires customization.
Back when IP first became big business, state-of-the-art circuitry was around 180nm. At those geometries, IP was pretty much plug and play. If a block of RTL did something on one chip, it would do the same thing on another chip. While the overall chip had to use the block correctly, there wasn’t much else that could go wrong. It didn’t matter what foundry made the chip, nor what other kinds of circuits were in the general vicinity of that particular block of IP.

That all changed at around 90nm. Suddenly, a circuit that worked perfectly on one chip would go all catawampus on another, simply because of leakage from surrounding circuitry. Even the same chip manufactured at different foundries might end up with wildly different yields, due to the peculiarities of the individual processes. As a result, IP, if it’s complicated or if it’s targeted for the smallest geometries, stops looking “plug and play” and starts looking like custom design work.

This screws up the “build once, sell many times” business model, says Smith. “Design firms selling state-of-the-art IP often find themselves spending more time tuning the blocks for specific designs than creating new IP to sell,” he says. In order to survive, smaller IP firms must extract revenue from the customization, rather than from the IP license. Unfortunately, this ties up their most precious resource—top engineering talent—thereby limiting their ability to continue to innovate.

CHALLENGE #2: New IP has a short market window.
Once a certain type of IP is well-understood and has been qualified for multiple manufacturing processes, it does begin to approach the plug-and-play status that would make “build once, sell many times” workable. However, once the IP reaches that state, it’s generally no longer unique enough to command a premium price. Instead, there will be multiple plug-and-play approaches to solving that problem. The IP becomes a commodity, making it more difficult to recoup the development expense.

For example, when USB 2.0 first came out, the IP to make it work commanded a premium license fee. However, once USB 2.0 had gone into enough designs, the problems making it work with different processes were largely solved and easily imitated. Because of that, chip designers can choose from a number of different versions of USB 2.0 IP and since none of them are noticeably better than the other, semiconductor firm are likely to pick the cheapest.

That’s probably OK, if you’re selling a knockoff. But if you invested a lot of time and money to come up with the first version, and then qualify it on multiple processes, you have a very limited amount of time to obtain the kind of high license fee that would provide a good return on that development investment, according to Richard Wawrzyniak, ASIC and SoC senior market analyst at Semico.

“The IP world is driven by your ability to differentiate your customer’s product,” he says. “If you can’t provide that differentiation, then your IP has limited value.”

CHALLENGE #3: IP Litigation can get expensive.
With chip designs costing more money every year, it’s not surprising that many semiconductor firms are outsourcing designs to India and China, where engineers are plentiful and cheap. Unfortunately, China (and to a lesser extent India) has an abysmal record of protecting high tech IP. “The entire idea of intellectual property is alien to Chinese culture; China didn’t even have patent laws until 1990,” explains Usha Haley, a business school professor at the University of New Haven and author of Asia’s Tao of Business: the Logic of Chinese Business Strategy (Wiley, 2004).

Unfortunately for their profitability, IP firms can find themselves involved in legal hassles related to the unauthorized use of their IP. That’s just a cost of doing business for large IP firms. Smaller IP firms, however, simply can’t afford that expense, according to Charlie Cheng, CEO of Kilopass, a company that holds IP patents for non-volatile memory. “Our only defense is to keep innovating so that people will keep doing business with us rather than stealing our IP,” he explains.

CHALLENGE #4: Semiconductor firms want to manage their risks.
Many semiconductor firms look a bit askance at IP because it makes them dependent upon the IP supplier. If something goes wrong with the IP during, say, verification or manufacturing, the IP supplier might not be willing (or able) to drop everything and run to fix the problem. And if the semiconductor firm hopes to move a chip design to a newer node, the IP supplier may need to get re-involved and possibly retrained on the design rules for a new process.

Under the circumstances, many semiconductor firms prefer to develop as much as possible of their circuitry in-house, so that they have control over development priorities if a problem occurs. Many firms only turn to IP when they lack the expertise to develop an in-house product. CPU IP is a case in point, according to Art Swift, vice president of marketing at MIPS. “We’ve been working on the RISC computing concept for decades, which has created a vast experience base and intellectual process that would be difficult, if not impossible to reproduce elsewhere,” he explains.

In other words, smaller IP suppliers entail risk that some semiconductor firms aren’t willing to suffer, according to George Zimmerman, chief technical officer at Solarflare, a company that makes 10 Gigabit Ethernet chips and controllers. “Going with a larger firm offers more risk mitigation,” he says. “We’ll only work with a smaller IP firm when what we need is highly specialized and can offer a substantial performance advantage.”

CHALLENGE #5: IP design favors economies of scale.
In contrast to their smaller brethren, the larger IP vendors have more resources to apply to making sure the IP behaves as expected. Synopsys is a case in point. “We have about 700 people working in our IP group who focus on adapting IP to run on different process nodes and for different customers,” says John Koeter, the company’s vice president of marketing for the solutions group. This massive application of manpower allows Synopsys to achieve the “build once, sell many times” business model.

Smaller firms, however, lack the economies of scale to imitate Synopsys’s success. Instead, they’re forced to marshal whatever resources they can to help a handful of customers, most of whom will require a significant amount of custom work. And while that still is revenue, it’s not as easy as getting a check every month for your IP licenses.

This is not to say that smaller firms can’t make money in chip IP, according to Smith. “The ones doing OK are making analog content because analog is difficult and there aren’t analog engineers available to be hired,” he says. But the idea that IP could be a short cut to big money for small firms remains a dream unfulfilled. “The reality is that it’s just not as easy as it looks to make money in this business,” Koeter says.

The barrier to entry also has escalated well beyond what it was at 130nm or even 90nm. The companies looking for IP typically are at the leading edge of design, which means the IP has to be qualified and tested for that process node.

“Prior to 45nm, there was no IP ready before silicon, said Brani Buric, vice president of marketing and strategic foundry relationships at Virage Logic. “Now you have to design complicated technology for SoCs, test it and verify it. So the skill level required on a scale of 1 to 10 went from 3 to 20. It’s tough to be a small player in this market.”

By Ann Steffora Mutschler

With the cost of failure at an astronomical high, the last thing chip designers want to worry about is the physical IP they will use to build their SoC.

In addition to less willingness on the customer’s behalf to take risks, complexity and economics have driven the need for more off-the-shelf IP and a corresponding rise in interest in verification IP. Compounding matters, IP investments are being stretched out for longer periods of time than in the past. That has made verification IP even more popular. Confidence in IP is critical, and this comes through a comprehensive IP validation discipline on the part of the IP provider.

However, the maturation of any method or tools means new focus on them, and so far the design industry has not even settled on what the optimal methodology should be for IP verification.

As a starting point, it helps to define types of verification. First, there is an intense level of unit-level verification where compliance to the relevant protocols is focused on and where the functionality of the block itself is detailed, said Mark Gogolewski, CTO at Denali Software. In addition, there is a separate step during which the subsystem or the system is constructed, with verification at this point being very different.

“For a time, there was a lot of IP verification when you had a bigger subsystem, but these days, the IP gets completely wrung out at the unit level and then when you construct the system, you are focused much more on connectivity and dataflow and how the system interacts,” he explained.

“If you are testing an IP block, there are two major dimensions of verification challenge. One is the protocols that are relevant to the IP block, and the other is the functionality, which is making sure the microarchitecture that was used to design the IP was correctly implemented,” Gogolewski said. “Correct” can have many meanings in terms of correct function and leading off performance objectives of that particular block of IP, he noted.

“Verification is all about observability and control. You need to make sure you are observing every aspect of the protocol, but then you have to give the customer control. One dimension for memories is giving easy control of the data space, and another is error injection and that’s another level of investment has to be made,” he added.

Carl Ruggiero president and CEO of Trilinear Technologies, agrees that common definitions of IP verification need to be established. “Depending on [a customer’s] point of view, everyone has a different idea of what verification ought to be, and that’s really making our job very challenging. Everybody says they want verification, but right now there is really no defined vocabulary for it. You cannot call it gates and flops like you can on the design side. People want to talk about coverage and percent of coverage, but at the same time coverage is very subjective. You can get 100% coverage with five coverage points. Therefore, it is hard to say what good coverage is because if you have 300 coverage points, you might be missing that 301^st, which is the critical one. How do we go about putting metrics on it? How do we define the vocabulary so we can all speak the same language? We struggle with this on a daily basis.”

In an effort to start out clearly with customers, Ruggiero says Trilinear talks about its verification in terms of functional coverage. “We talk about the actual things that we set out to do. We talk about garnering 100% functional coverage. While we don’t say that we’ve tested every ad nauseum combination of things, that for the things that our software drivers and reference drivers, the functions that are listed in the data sheet and in the specification, those are the ones we’ve tested to.”

IP Verification Challenges

Ken Brock, director of physical IP marketing at Virage Logic, said that when it comes to IP validation specifically for on-chip physical IP, challenges and solutions can include taking a standard cell library of more than 1,600 unique circuits and running them through one of several EDA vendors synthesis tools, running them again through the same or different EDA vendors’ physical synthesis/place and route tools and have them all work perfectly; taking a memory compiler with a dozen different knobs and switches and producing a fully functional memory IP over the number of words and bits with multiple aspect ratios, test options and power optimization configurations; mixing them together with other IP on an SoC; and doing all of these things over the full speed, voltage, temperature and process variability extremes of a specific leading edge silicon process.

He noted that the IP validation process requires a rigorous discipline, which includes unit validation, integration testing, platform validation and silicon validation.

Indeed, IP giant ARM is pursuing just that. Tom Lantzsch, VP of ARM’s Physical IP Division noted, “We spend a lot more time with the EDA partners integrating our IP under their flows much earlier and having them leverage it and test it themselves. It is a constant activity because when we do our verification, unlike an internal supplier, which probably has a limited EDA flow, and maybe even a limited customer set within their company, we have to be much more systematic and have to create a verification environment that supports us for multiple years.”

The Cost of Providing Verified IP

Whether making an investment into a new technology for entrepreneurial reasons or encouraged by major customers, the latter of which Denali did with its entry into the PCI Express arena, making it pay off is no small task both to the customer and for the IP provider.

As Gogolewski explained, with the company’s entry into PCI Express, “the world got a lot more complicated because it is extremely configurable, programmable and complicated. What we mean by configurable is that before you even put a design in silicon there are many choices. We have a couple hundred choices in our configuration spec just to correctly specify what that particular device even looks like at a specification level. It is programmable because it has all sorts of register settings that have to be set correctly and which can change the behavior of the device. And then it’s just complicated—our engineers had to become experts on two to three thousand pages of documentation. We had to make sure all the functionality was in there with the flexibility and programmability; we had to make sure all of those thousands of pages of spec became error checks and assertions. And then the way that [PCI Express] protocol works, your IP has to both handle correct functionality and incorrect functionality and respond properly. So there was a multitude of error injection that we had to make available to our customers as well as our own design team to make sure that they could inject all these levels of errors and validate whether or not their design caught it correctly.”

To deliver this level of backup data to customers for PCI Express, Denali estimates the extra engineering effort required is equal to approximately 70 to 75 man-years of effort over 7 years, with about 550,000 lines of new code created, not including the company’s Purespec library code.

The IP Verification Horizon

In the next phase of IP verification, one thing is for sure—there will be more of it provided by third parties.

“We’re at a tipping point from ‘make unless you have to buy’ to ‘buy unless you have to make,’ and the current economic climate is going to accelerate that. Basically the fundamental premise of third party IP is that if it is a ubiquitous problem and it is solved well, then the market is overall more efficient and better off when a third party solves it, rather than each customer solving it on its own,” Gogolewski said.

He also sees more IP verification moving toward third party IP vendors, even though there will always be customers that will create their own IP to maintain their place on the very bleeding edge of design. And he believes coverage-centric verification will be embraced. “It used to be something that leading-edge design teams would use, but now it is becoming ubiquitous,” he said.

By Ed Sperling

Santa Clara, Calif. — Feb. 3, 2009 — Build or buy has always been a question for system-level developers. There are time-to-market pressures to create and test a system, and there frequently are integration issues even with the best-qualified third-party intellectual property.

But what’s the actual tipping point where it makes sense to buy IP? Mark Gogolewski, chief technology officer at Denali, said it’s based on a factor of 10. If it costs 10 times more to build than to buy, then it makes sense to go outside.

Gogolewski noted that it generally costs IP vendors 5 times the initial investment to productize, sell, market and finance IP development. Profit-taking accounts for an additional factor of 3. Those numbers get multiplied, so it costs 15 times the investment to create a final product that can be licensed commercially.

The numbers for an IP vendor, however, can still be significantly lower than an internal development team within a semiconductor company. There is less overhead, more specialization, and sometimes there is an opportunity for re-use of code that already has been developed. On top of that, many companies simply don’t have the skilled engineers on staff to develop specialized IP, which has become dramatically more complex over the past decade.

Quality from third-party IP also has improved from the early part of the decade, when off-the-shelf IP blocks often caused more integration headaches than they were worth. They are now viewed as essential building blocks on complex chips, which is a testament that repeatedly throwing very smart people at a problem and learning from mistakes eventually pays off.

There also is enough critical mass in the market to be able to test IP designs in a variety of applications. “Our internal rule is that if there are not 40 designs a year, it’s not a viable enterprise,” Gogolewski said. “You even want more designs than that because not everyone will outsource this work at the same time.”

In addition, the companies selling the IP are likely to be around in five years. The majority of IP vendors at the beginning of the decade were small startups. Those startups have since been acquired or grown enough through their own sales and acquisitions to have gained staying power—even in the worst downturn in decades.

Virtually all the major EDA companies offer IP. Mentor Graphics, Synopsys and Cadence all sell IP blocks. And companies such as ARM, Virage Logic and Denali have grown large enough, and specialized enough, to have built expertise in the respective areas of focus.