By John Blyler
The essence of Design for Manufacturability or DFM is to ensure that what is designed can be manufactured. The challenge is that both processes – design and manufacturing – use different metrics to measure success. For the design of today’s complex chips, power and timing remain the critical constraints. In manufacturing of those chips, the critical parameters are yield and process variation.

DFM relates the manufacturing parameters back into the design process, i.e., the chip design’s statistical sensitivity to yield variations. This relationship is accomplished through the use of several DFM tools, including lithography sensitivity, thickness variations of the wafer, particle variability and others.

But what should have been a helpful relationship between manufacturing and design instead became a burden. “It seems that the industry tripped over DFM,” explains David Abercrombie, program manager for advanced physical verification methodology at Mentor Graphics. Instead of using DFM to improve the manufacturability of designs, many designers saw DFM as yet another metric, another constraint to limit what they could do in the design.

To a large extent, they were right. DFM tools historically have been used to predict which design methodologies, teams, and intellectual property (IP) are more likely to be repeatably manufactured.

“But what we are trying to tell designers is that they need to use DFM tools as part of an overall metrology approach to improve their design process,” says Abercrombie. The challenge is that, when these tools are first run on a design, a number or score is produced. Understandably, designers want what this number means? Is it a good score or a bad one?

Abercrombie believes this is where the industry locked up. Designers didn’t understand what the score meant since they had nothing to compare it to. The answer was to create a baseline for this score. But that meant running the same DFM tools on previous designs, e.g., on the IP from the last design on a previous node. The score for that node would probably be different from the current node. But designers would begin to establish a range of values for which they could compare one design to another in terms of design teams, best practices, tools and processes.

Using that data, designers could begin to know which designs are easily manufacturable and which were not. The score will become a useful metric.

Naturally, collecting this data takes time and effort, something that most designers don’t have. Also, Abercrombie feels that the industry has not been successful in getting design teams to use DFM tools in this manner. “Most design teams won’t run the DFM tools unless the fabs tell them that they must.” Indeed, some of the litho and CMP problems have gotten so severe that the foundries require designers to run these metrics before a design is accepted. If the tools flag certain parameters that are beyond a certain limit, then the designers must fix them.

Using DFM tools as a last ditch effort to find glaring errors and have the fabs force changes, is not the best use of these powerful tools.

What is the future? Abercrombie would like to see an industry standards board that would help establish acceptable metrics or scores. Then, publically purchasable IP could be scored in terms of its manufacturability. These scores would be shared with the industry, giving designers a reference frame for future designs.

Scoring IP is hardly a new concept. But scoring it from the foundry perspective adds a new dimension, one that designers have yet to fully embrace.

By Ann Steffora Mutschler

At 65nm, design for manufacturing optimization and analysis has mostly been an afterthought. At 40nm and beyond, DFM has been pushed well up into the design phase.

There are good reasons for this shift. What emerged at the 65nm node were signoff tools that understand manufacturing used in semiconductor design, said Manoj Chako, a product director for digital sign-off solutions at Cadence Design Systems. DFM used to occur post-DRC and included the work done by the foundries. At 40nm, ‘design-side DFM’ is forcing design teams to take into account the lithography, CMP (chemical mechanical planarization) and electrical (parametric yield) issues.

“The systematic effects on the layout have now become a prominent problem,” Chako said. Among the problems to surface at 40nm and beyond are parametric yield due to tight geometries and the very tight pitch in designs, performance issues caused by strict design rules and the addition of stress in designs that is being added to improve the mobility and performance of transistors.

From a high level, this is being caused by a fundamental disconnect. The process geometries are scaling but the wires do not scale uniformly. The wires are getting narrower, which is causing a problem with cross-talk, but they’re not getting as short as everyone expected, said Rob Knoth, technical product manager for Magma Design Automation’s design implementation tools.

Moving from 65 to 40 and 28nm has driven other changes, including the penalty of a via. “There are now rules governing redundant vias and the shape of a via, for instance, said Knoth. “Some foundries change their recommendation for what a good via would look like. This can be multiple square or rectangular cuts.”

Knoth said he is also concerned about stress-induced lithography violations at 28nm, a lot of OPC (optical proximity correction) checks, and very complicated end-of-line rules. “At 65-nm, things were a little more vanilla. People were looking at dummy metal to improve the gradient across the chip. They were definitely looking at redundant vias but it wasn’t nearly as critical as it is at 40nm and 28nm, both from a manufacturing standpoint and a timing standpoint.”

These technological impacts have changed the way semiconductor implementation is performed, noted Sudhakar Jilla, director of marketing for Mentor Graphics’ place and route products. At 28nm it’s important to have the router be able to call the signoff quality engine during the routing phase. Typically what happens is that once routing is finished, DRC (design rule checking) and LVS (layout vs. schematic) are run. At 65nm, the DFM analysis was an afterthought once the design was judged DRC and LVS clean. At 40nm and beyond, it needs to be considered much earlier in the flow or it will cause some very late stage surprises that will make recovery difficult, he said.

Jilla said that for one 28nm library a customer ran the design through the flow and performed the LFD (litho friendly design) analysis. It showed a number of L1 hot spot errors due to fidelity issues of the manufacturing process.

“This occurred one week before the tapeout, and if they had to go and fix all of the violations it would have taken a few more weeks and would have to be done by hand,” he said. “We are working on a technology for the router – which is utilized four to six weeks before tapeout – that can invoke the same LFD engine inside the router. Once the router is done routing it asks if it is LFD clean. If yes, it is done. If not, the fixes are made at that time. If you don’t have a solution where the router can take advantage of the signoff engines, you are going to have to wait until the last minute or let the design go as it is, taking a risk on the yield.”

Knoth said that one of the big things Magma is doing, especially moving from 40nm to 28nm, is changing some of the cost functions that are driving the tool, and looking at things like spreading wires earlier so that congested hot spots are not created. The company also is building intelligence earlier in the cycle to avoid future manufacturing problems.

“It’s hammering more on that ‘correct-by-construction’ concept,” Knoth said. “The cost of fixing a problem once you analyze it is huge. That being said, though, the other main effort that we are working on for 28nm is building a better infrastructure so that timing can be considered as you are going in and fixing lithography problems.”

In Magma’s place and route toolset everything is integrated: the timer, the DRC checker, the router, etc., so the router can call the other engines as it is making decisions. If it is reordering wires, or is jogging something to make it more litho-friendly solution, it understands the timing impact of that because you can’t just fix DFM.

“That’s a very big fallacy that I think happened early on when a bunch of DFM solutions hit the market at 65nm,” Knoth said. “Everyone was just looking at DRCs and DFM and we made sure that timing was also part of that, so that as we went off to hammer on those problems we weren’t creating a new timing violation that would cause you to rip up and rebuffer a whole net.”

The foundry effect
“DFM in general is a concept that is never going to go out of style,” Knoth continued. “The frustrating thing about DFM is that it just reflects a foundry’s lack of familiarity with a process. As a process matures the foundry figures out what yields better and what doesn’t. They make hard rules to improve the yield and a lot of the soft rules that are needed for DFM, those go away.”

At 65nm, TSMC and most of the foundries had DFM as a recommended rule, but it was not a mandatory signoff check. But starting at 40nm, most of the foundries are making DFM handoff mandatory.

“What that tells you is that the foundries are now starting to realize you can’t just squeeze the DRC rules some more and hope it addresses DFM success,” Jilla said. “DFM is a big enough issue that they can’t hide it in the back. And what that indirectly means is that although the customers say they do run a DFM check and find 20 or 30 LFD hot spots. or you do the critical area analysis and there are a lot of opens and shorts, what do you do about it? That’s where the router comes into play and the designer needs to have a router that can respond to these sign-off checks and give a clean design that not only is DRC/LVS and timing clean, but also DFM clean.”

System-Level Design sat down with Lisa Su, senior vice president and general manager of Freescale’s networking and multimedia, to talk about changes in the communications sector and how that’s affecting design. What follows are excerpts of that conversation.

By Ed Sperling
SLD: Where does multicore fit into the Freescale world?
Lisa Su: The difference between us and an AMD and Intel and IBM is they’re focused on multicore for the compute market. Freescale is focused on multicore for the networking market. Our focus is wireless infrastructure and network routers. Multicore is certainly prevalent in our world. We have an 8-core device running at 1.5GHz on each core. We’re also in the DSP space with multicore, because of all the parallelism there. We have a six-core DSP.

SLD: What’s changing as a result?
Su: With all of the competing standards in base stations, network equipment providers are looking at how to re-use their hardware equipment investment and operators are looking at how to maximize their CapEx investment. The trend is to go to common platforms that allow you to run multiple standards on a single platform. If you think about 3G, wideband CDMA is where a lot of the CapEx investment is going on the operator side. But LTE is right on the horizon and there is a great desire to be able to use the same common platform in 3G and LTE and in some cases WiMax. You need to get the performance of LTE and satisfy the cost points for 3G. Multicore is our strategy for doing that.

SLD: But don’t you still have the same challenges as the multicore computing world, such as parallelization of applications?
Su: We do have similar challenges and the results are mixed. On the signal processing side we’re able to take advantage of the parallelism. On the general-purpose processing side there is the challenge of fully using the processing capability. If you have an 8-core processor, you want 8 times the performance. There is a lot of work going on in tools, though. From a tooling standpoint, we’re getting better. Virtualization is a key piece, as well—being able to put applications on different slices of the chip. Multicore is taking off in communications right now. There is a lot of work by the OEMs to be able to convert their code.

SLD: Frequencies seem to be climbing again on individual cores. When do we blow the power budget?
Su: The frequency will go up, but not tremendously fast. You can put more cores on the chip. We built a data path infrastructure that manages the data across the cores. We believe you can scale up to 32 cores, if you want to. The real challenge is whether to use all those cores, or whether it’s better to improve performance in each of the cores—which is what we’re hearing from our customers. They can’t evolve their software that fast.

SLD: Is part of the strategy also to use cores for acceleration of processing?
Su: Yes, we can run an asymmetric processing mode where you have a master core and some others. What’s interesting here is not only do we have eight cores, but we have special acceleration engines like security accelerators on the chip. You can operate on the general processor or these specialty engines.

SLD: Are the cores homogeneous?
Su: When we call the devices 8-core, those are homogeneous. But there are additional acceleration devices. My view is that heterogeneous will become more popular as the applications become more specific.

SLD: That’s a much harder design problem though, isn’t it?
Su: Yes, but when you have high-volume applications it makes sense to do it that way because it’s the most optimized solution. When you’re in the infancy of a market, homogeneous is much easier.

SLD: Multicore also makes it harder to schedule shared resources on a chip. What’s new there?
Su: We have a hardware scheduling function. The key in multicore is to eliminate the contention between the cores to maximize the performance output. There are things we can do in hardware and software to schedule who gets access to resources.

SLD: Does this also affect the various states of applications and cores?
Su: Yes, there’s a lot of power management. Our world is 8 cores in less than 30 watts. It’s a tight power window. That’s our challenge—getting all that processing power in that power envelope.

SLD: Does this come down into the mobile device space?
Su: Yes. That’s the other part of our business. In our multimedia business, you’re seeing multicore devices. They’re going from single core to dual core. When you talk about mobile form factors it’s a slower progression, but it’s the same concept—how do you do more with less or within the same power envelope. It’s power and price point. There’s a consumer space, the low end of the enterprise, the midrange and then there’s the high end of the enterprise. At the low end it’s going from 1 to 2 cores, in the midrange it’s from 2 to 4 cores, and at the high end it’s 4 to 8 cores.

SLD: What process node are you at?
Su: 45nm.

SLD: Are you pushing to 32nm and beyond?
Su: Yes, the next node for us will be 32nm.

SLD: The foundries are beginning to talk about restrictive design rules at future nodes. How will that affect Freescale?
Su: That’s more of a style of design. I consider restrictive design rules like DFM on steroids. But it does require more design resources to migrate from one generation to the next.

SLD: Last time we talked, you mentioned that DFM tools weren’t all there. What’s missing?
Su: The challenge is still the interoperability with the tools. All the DFM tools need to be calibrated to a given foundry or fab, and that needs to come back to us. Ensuring that flow is seamless requires work. But I do have to say that since I made that statement all the EDA vendors have been calling to say they’ve solved the problem. I’ve been very popular with the EDA vendors. But the net of it is DFM is not optional and it’s important that when we use multiple foundries, the tools have to work well across the entire tool suite. It’s not something we can do as a post-processing thing anymore.

SLD: Is it a matter of chip developers choosing best in class from a variety of vendors and not having interoperability?
Su: Yes, that’s correct. Although we are going to primary EDA vendors, we’re not going to a single EDA vendor.

SLD: So having standards is vital?
Su: Yes.

SLD: How often do you increase cores? Is it the same node or the next node?
Su: It’s next node, because we want to keep a fixed power envelope. It’s not that you can’t add more cores, but you need to stay within the power envelope the application requires.

SLD: How about vertical stacking?
Su: It’s an option that can be used as the technology becomes more mature.

SLD: How far down does your road map extend?
Su: In the product business, we’re looking at 32nm and 22nm. The evolution of the technology has a lot to do with how fast we use it.

SLD: Is there a possibility that after that you don’t go further?
Su: I won’t say that yet. People have said that at every node and it hasn’t come true. But the product adoption rate may be different. There fundamentally still is improvement in technology. As long as there is improvement in density and performance, we will continue to look at new nodes.

By Ed Sperling

For the past couple of years, restrictive design rules have been looming over advanced process nodes as the best way to get a chip out the door with minimal re-spins, on schedule and for the least amount of money.

Even with immersion technology, 193nm wavelengths mean the laser beam is entirely too large to create the masks used to create complex systems on chip at 32nm and below. It’s like trying to operate on a patient with a dull butter knife rather than a razor-sharp scalpel. And with extreme ultraviolet and e-beam still years away from commercial availability—and some doubts lingering about whether they ever will be ready—restrictive design has emerged as a requirement for foundries such as TSMC.

But exactly how tightly those rules will become is unknown at this point. Just as many predicted the end of Moore’s Law at 1 micron because of lithography limitations, it’s hard to predict where there will be new breakthroughs. Self-assembly and carbon materials may entirely change the way chips are created at future process nodes, for example. But for the immediate future—32/28nm, 22nm and all the way down to 15nm—most scientists and engineers are looking at evolving existing technology rather than radical breakthroughs.

One such tool is computational scaling, which uses complex formulas to create masks rather than actually etching them. While it doesn’t entirely eliminate the need for restrictive design rules, it certainly raises questions about just how onerous those rules will become.

“As an integrated systems company we still have to sit down each generation with the process guys and figure out who’s better off taking the pain,” said Brad McCredie, an IBM fellow and vice president of the company’s Power Technology group. “At 65nm, it was all about shapes so we could print on the right grid. With design restrictions, it’s easier to print the shape. But you still have to have conversations like that at every node.”

Most chipmakers and foundries have come to the conclusion that more regular shapes in the design, as well as more regular spacing of those shapes, helps improve design success with minimal re-spins. There likely will be additional restrictions in the future, as well, such as what can be added where and when in a design.

“We will have convergences like that at every node,” said McCredie. “There is no panacea showing up. It’s getting tougher and tougher for CA (the first contact layer in chip design) and M1 (first metal layer in the chip).”

IBM introduced computational scaling last fall for the 22nm process node, offering one more tool to help in design for manufacturability. An IBM paper published in September 2008 says there is “tremendous pressure on the design process and the mask technology that need to overcome the two-dimensional limitations of the lithographic process.” The paper noted that the amount and complexity of the processing will be “very large, requiring source/mask optimization and optimized design rules.”

IBM also inked a deal with Mentor Graphics to jointly develop some of the tools around computational scaling, based upon Mentor’s Calibre platform. Mentor introduced computational optical correction and acceleration last year.

But IBM and Mentor aren’t the only ones wrestling with difficult processes at future process nodes. All of the major chipmakers are dealing with the same issues, and all of the commercial foundries are struggling to balance the needs for creativity in design with the ability to get chips into production in ever-shorter market windows. Tom Quan, TSMC deputy director, said that at 40nm there will be some rules for design, but he said the bank of rules will increase at 28nm and again at 22nm.

“When you have restrictive rules for layout you increase your predictability,” Quan said. “For the layout designer, that means less freedom.”

For the chip companies, it also means less differentiation in hardware and significantly more in software. But a lot of very smart people are working on the problem, even if they don’t have a clear answer at this point.

By Cheryl Ajluni

With system design such a complicated task these days, it is increasingly likely that designers will inadvertently overlook some details of the design process, or worse yet, simply not have the time to address them adequately.

Time is readily spent focusing on things like performance, area, timing, and power, but what about something a bit more esoteric in nature—namely, quality? Defined many different ways, its overall impact in today’s highly dynamic, highly competitive marketplace is clear. Quality designs breed successful products with a true competitive market advantage. Those lacking quality are set up for failure.

While quality has always been important in electronic design, device scaling is now making it all the more important to achieve and, all the more difficult to obtain. In 2000, Dr. Ali A. Iranmanesh, founder and chairman of the International Symposium on Quality Electronic Design (ISQED), explained the problem this way: “We have witnessed a phenomenal increase in the level of device scaling as well as in semiconductor manufacturing quality. This has enabled the industry to provide ever more complex electronic products. However, the advancement in semiconductor technology has drastically surpassed the progress in the capability and quality of EDA tools and design methodologies. The result is a fast-growing disparity between the available capability and what can be realized in design practice.”

After nine years, has much really changed? Not really. Disparity is still present, as are other pressing concerns. Vendors continue to struggle to gain the advantage of being first-to-market. Once there, they must be able to meet increasing demand with a reasonably stable supply of product. But with process geometries shrinking, ensuring good and reliable performance from complex system designs as well as economical yields becomes difficult at best. It requires the designer to play close attention to every aspect of the design process, including the design’s reliability, manufacturability and yield. If the design is unreliable, its overall quality will suffer. If it cannot be manufactured easily or correctly, or if there are too many defects caused by the interactions between the design and the manufacturing process, then yield will decrease and quality will suffer. With reliability, manufacturability and yield all intricately tied to quality, what’s the system designer to do?

Design for X Strategies

Luckily, the EDA industry has not turned a blind eye to the situation. Over the years it has rolled out solutions specifically designed to help designers improve quality by dealing with issues related to a design’s manufacturability, reliability and yield. As a result, DFx technologies—Design-for-Manufacturability (DFM), Design-for-Reliability (DFR) and Design-for-Yield (DFY)—have now become common terms in the designer’s vernacular and are even finding their way into the earliest portions of the design cycle.

“As dimensions shrink below 65nm, the difficulty of manufacturing is forcing designers to reassess their physical designs, a method alternately referred to as DFM, DFY or DFR,” said Jean-Marie Brunet, product marketing director for Litho Friendly Design and DFM products at Mentor Graphics. “Interestingly, the same methods and tools actually affect both manufacturing yield and reliability because the goal is to remove or adjust layout patterns that are difficult to render in the manufacturing process, and therefore are most likely to cause failures either during factory test or when the product is in the field. DFM/DFY/DFR tools apply rules and models to predict which specific shapes in a layout will cause problems in manufacturing, rank them in importance and, in many cases, fix them automatically, for example, by widening or moving interconnect wires, doubling up on vias, or repositioning layout edges.”

Employing DFM, DFY and DFR technologies, and the capabilities they enable, is a key way in which today’s system designers can improve the quality of the electronic systems they design.

Design for Manufacturability

DFM technology helps optimize a design so that it is as easy and low cost as possible to manufacture. What started years ago as standalone DFM tools have now evolved into offerings that are more tightly integrated with physical implementation. TSMC’s Unified Design for Manufacturing (UDFM) architecture opened the door to this possibility by providing EDA flows with access to TSMC DFM foundry data. For 45nm and 40nm process nodes, the data is provided in a DFM Data Kit, which includes data for lithography pattern check, critical area analysis and chemical mechanical polishing.

Beyond 40nm, DFM data along with an exact copy of the production model that was used is provided in a DFM Design Kit. EDA tools use this data to help designers quickly identify and fix any potential manufacturing issues. Today, DFM solutions are available from a range of EDA vendors, including Mentor, Synopsys, Cadence, Magma and Micrologic.

Design for Yield

DFY is considered by many to be a subset, or even a new generation, of DFM that evolved to address the declining yields in IC production stemming from increasingly complex semiconductor processes. With nanometer range process geometries, yield is a function of the chip layout as well as the defects from interactions between the chip design and the manufacturing process. Yield can therefore be increased by reducing the defects or changing the design to make it less susceptible to those defects. As an example, reducing the critical area in the design layout can enhance yield (Figure 1).

Of course, DFY is not limited to the manufacturing process. Stratosphere Solutions offers a silicon-proven platform and modeling platform, StratoPro, to address parametric yield and performance issues during both design and manufacturing. These platforms work together to characterize, model and analyze the impact of variability on parametric yield and performance. Appropriate changes can then be made to the design to make it more tolerant to process imperfections and variations.

A critical part of DFY technology is yield analysis, which helps determine those parts of a design that are most likely to be incorrectly manufactured. Earlier this year, Synopsys launched a yield management product, Yield Explorer, designed to bring design information into yield analysis by linking all aspects of the design, manufacturing and test flows into a single data bank (Figure 2). Product engineering teams can use this solution to quickly find and perform root cause analysis on systematic yield limiters, thereby improving yield and minimizing design respins.

Design for Reliability

DFR refers to the process of designing reliability into products to ensure customer expectations are met. System engineers use DFR methods (e.g., correct-by-construction) and tools to design complex systems having a specified reliability. Generally this process begins with establishment of the system’s reliability requirements. During system design, these requirements are allocated and designed into the various subsystems. Reliability models are developed which evaluate the relationships between the system’s various parts, assessing differences in design alternatives. Some of the analyses that may be performed include: thermal analysis, fault tree analysis, root cause analysis, and EM analysis. While these techniques may be effective, ultra deep submicron (UDSM) design environments will require another option.

One company claiming to have the answer to this challenge is Micrologic Design Automation. Last year, it introduced a nanometer range EDA tool, nanoRVInteractive, designed to interactively eliminate reliability issues during the early stage of physical design (Figure 3). As opposed to other solutions that verify blocks only after they have been designed, going back to correct the design as necessary, Micrologic’s approach provides a reliability check in the early design stage by creating what it calls a reliability-aware design environment. In this environment, nonRVInteractive automatically analyzes a design for reliability phenomenon like electromigration, self heat and voltage drop (IR Drop) during the construction of IC layout. Designers can then use the resulting analyses to quickly determine the severity of any reliability issues.

Conclusion

Developing quality electronic systems does not occur accidently. Disparity between semiconductor technology and design tool capabilities, as well as issues caused by scaling only makes this goal more challenging. Quality depends in large part on the design itself and its influence on reliability, manufacturability and yield. Consequently, to achieve a high level of quality, today’s system designer must pay close attention to the design’s reliability, manufacturability and yield using tools based on DFx technologies. Information garnered by these tools provides critical data that can be used to change the design to avoid specific problems. Doing so will not only improve quality, but also shorten development time, minimize cost and enable faster time to market—providing today’s designers the competitive advantage they need to succeed in the marketplace.

By Ed Sperling

Gabe Moretti is out in front this week with a blog about how Cadence may have cut its design for manufacturability staffing but that it actually hasn’t abandoned DFM. Hmmm. You could have fooled us, especially with that official announcement. The revised word, now, is that only portions of the DFM budget are being cut. Or so says an anonymous employee. Gabe’s reporting of this insider’s view, not to mention his healthy cynicism, are a great example of how to approach this kind of point-counterpoint misinformation. Nice job, Gabe. You get the Blog of the Week award and a thunderous round of applause.

He’s not alone talking about DFM, either. Mentor’s David Abercrombie takes on DFM for non-PhD.’s, and it’s another great read. His premise is that reliability is what decreases defect density, which in turn improves yield. Given that DFM has to be integrated with abstraction models at 45nm and beyond, that’s a high-level of abstraction for what’s really going on beneath the covers. But it’s a great way of gleaning the essence of this problem and cutting through the misunderstandings that surround it.

Synopsys’ Frank Schirrmeister addresses the free software business model at Imperas and why the company has started charging for its tools—namely because you can’t sell free stuff for very long and still expect to be in business. But Schirrmeister does bring up an interesting point. Where is the value in virtual platforms? And are people charging for it?

Team Specman is updating the e/Specman reference card and looking for input. For anyone who uses this language and wondering where all the new stuff is, this is your chance.

Harry the ASIC guy is back with another incisive look at the FPGA world. It’s chock full of good information and lots of analogies and insights, which is why Harry Gries is still one of our favorites in this business. Great stuff, Harry.

Mentor’s Karen Chow begins addressing the subject of mixed signal SoC verification, but she winds up asking questions rather than providing answers. There reason is simple. There are no answers. After talking with dozens of people on this subject, we believe there are many more questions than answers. Worse, that will likely be the case for the foreseeable future. Mixed-signal verification remains one of the thorniest problems in system-level design.

Lisa Su, chief technology officer at Freescale, talks about the future of system-level design, what’s working and where the problems are.

By Ed Sperling

Design for manufacturing has been talked about for at least the past five years, but somehow it always seemed to be a problem that would be dealt with by the foundries or internally with a company’s own fabs.

Two things have changed since then. First, almost all companies have jettisoned their digital fabs—the remaining holdouts are IBM, Intel, Samsung, Toshiba—which means they no longer get information back on a second-by-second basis from the fab. And second, creating SoCs has become so complicated that tools are necessary to help guarantee the chips can be manufactured with decent yield to meet shrinking market windows.

At 45nm, DFM has become the norm. At 32nm, it will likely not even be called DFM anymore. It will simply be part of the integrated tools flow. That was the hidden message during a recent ISQED panel that looked at whether DFM was marketing hype or a secret weapon for foundries and developers. In reality it is neither. It is the formalized resurrection of a communications channel between the foundry and the design team that disappeared with the internal fab, along with some automated ways of implementing that feedback.

Walter Ng, vice president of design enablement alliances at Chartered Semiconductor, said his company began working in earnest with DFM at 65nm, which is about two process nodes after the hype began about design for yield and design for manufacturing.

Since then, virtually every sector of the system-level design industry has put its stake into DFM. Luigi Capodieci, president of Global Foundries—the AMD foundry spinoff that has backing from a United Arab Emirates venture fund—said DFM is no longer an option. It is now a requirement. That view was shared by executives at Mentor Graphics, Atmel and Virage Logic.

And for the skeptics who insisted for years that DFM (termed design for marketing even by some high-ranking EDA executives) was a ploy by EDA vendors to sell more software rather than bridging the communications between the front and back ends of the design process, increasingly it looks as if they were wrong.

By Ed Sperling

Santa Clara, Calif.—Feb. 5, 2009—Design for manufacturing was a great buzz phrase for the past five years, but at 45nm and beyond DFM is becoming a necessary approach. As a result, differences between system-level designers and foundries have escalated from hypothetical to tangible.

Joe Sawicki, vice president and general manager of Mentor Graphics’ Design-to-Silicon Division, said during a panel at DesignCon that DFM has moved from the hype phase to the “slope of enlightenment.” He added that at the 45nm and 32nm process nodes it will become a design diagnostic requirement.

That also means DFM needs to be developed and tested like any other suite of tools in chip design. Kimon Michaels, vice president and general manager for DFM at PDF Solutions, said much of the data that DFM tools now provide are “overly conservative.”

“There is a need to provide DFM data that is accurate and practical for both the foundry and fabless companies,” Michaels said. He noted that the quantity of the data has not been a problem. There is plenty of available, but not of the quality necessary to avoid respins and ensure manufacturability of designs.

To a large extent, this depends upon cooperation between the fabless companies and the foundries that manufacture their chips. That cooperation has improved over the past several years, but there is still hesitancy on both sides to cement a partnership.

On the side of the developers, Mark Radford, Cambridge Silicon Radio, said questions remain about the data. “The foundries provide DFM kits and SPICE models and EDA provides tools,” he said. “But does the data statistically capture what we want and the level of detail we need?”

The answer to that question becomes increasingly important at every new process node. “At 32nm and 28nm, variability will be the dominant new challenge,” Radford said. “There will need to be DFM checks on third-party IP. All parties must work much more closely together. Right now there is competition and suspicion. We need to find a collaborative EDA, fabless and foundry working model.”

All of this concern—by EDA companies, foundries and end users—signals a change in how companies are looking at DFM. Walter Ng, senior director of design solutions at Chartered Semiconductor, said that until now there has not been a lot of adoption of DFM by customers.

“The big question now is, ‘Do customers see the value of purchasing additional tools,’” he said. “Through 65nm, we have not seen much impact.”

Ng noted that DFM will be most needed where there is the least amount of silicon—at the leading edge of development—and where variation tends to be greater because there has been limited learning on a new process. He said that variability decreases as volume increases and processes can be refined, but there is a challenge for companies looking to utilize the most advanced process nodes.

Among the problems is the cool air thermal limitation of 100 watts per square centimeter, said Jamil Kawa, group director of Synopsys’ advanced technology group.

“Voltage is not scaling properly anymore,” Kawa said. “There is also an increase in short-channel effects. Silicon trench isolation will be difficult unless we move to SOI (silicon on insulator) or finFETs.  In addition, planarization will become very critical.”

By John Blyler

Chips continue to grow in complexity. This is nothing new. But even at the existing process nodes of 180nm and 130nm, complexity is increasing as designers attempt to squeeze in more feature sets while shrinking the power budget and chip size. This growing complexity, married with the shift to time sensitive consumer product markets has led to an increase in the use of prototypes to verify these chips prior to production.

But what do users really seek in prototyping tools? The report that follows contains the summary and analysis of a survey conducted with more than 270 qualified respondents in the ASIC and related markets. The results track well with similar surveys in this space, but the details present some surprising implications.

Application Markets

Most responders listed the communication market as their primary product area, followed closely by the Consumer, Computer and Other markets (see Figure 1). Most prevalent “Other” markets were Industrial, followed Mil/Aero, Automotive and Medical.

Figure 1

In the category of communications, most respondents listed wireless handsets and wireless and wired networking as their chief application areas, followed closely by wireless base station design, telephony/VOIP and wireless Metro Area Networks (MANs). A small percent listed research, remote controllers, CDMA networks, fixed networks, telemetry and military as other areas of focus within communication category.

In the consumer market most respondents list multimedia designs – involving both video and audio subsystem – as their primary area for developing ASIC prototypes. Multimedia design concerns will be reflected proportionately in other parts of this survey, i.e., processor types, interfaces, etc. Interestingly, several designers listed games as their chief concern. That’s a trend we will watch in future surveys.

Computer design issues were most closely tied to peripherals such as storage, printers and the like. PC and workstation systems came next, with others including prototyping systems, servers, data acquisition modules, and instrumentation and software/firmware design issues.

Job Function

Most of the respondents identified themselves as ASIC or ASSP designers, followed by engineering management, corporate management, verification engineers, system architects and software designers. A small percent of users listed their function as applications engineers, business development, academia and sales/marketing.

Figure 2

ASIC/ASSP/SOC Design Details

When asked to describe their current ASIC/ASSP/SoC design, more than half of the respondents indicated a design size of less than 5M gates, with that majority below 2M gates.

In terms of memory, most designers focus on SRAM memory, suggesting the strength of on-chip memory prototyping. Still, DDR and Flash memory account for about 22% each of memory usages.

Embedded processors usage is led by the MIPS processor, which matches up with the respondents’ applications markets. ARM, Tensilica and Intel comprised roughly 16% each of the remaining usage. Other processors used for ASIC prototyping ran the gamut from microcontrollers like the 8051, Microchip’s PIC and Xilinc’s MicroBlaze to proprietary cores. A large number of DSP cores also were cited, including Ceva Teak Lite, TI and in-house multimedia DSPs.

To the question concerning the types of external interfaces used in ASIC prototyping projects, the top three busses were PCI, USB and Ethernet. SPI, SATA, XAUI and HDMI finish up the lower quadrant. Though not listed in the survey, questions have arisen about the use of the PC-104 bus. Several experts believe PCI Express represents the path forward for PC-104. This projected growth will be the subject of a future survey.

The majority of users listed Serial RapidIO (sRIO) as the main external bus of choice under the “other interface” category. This is no surprise, since the sRIO interface is commonly used to connect multiprocessor designs, especially for DSPs. This tracks well with the use of DSPs highlight in the “Processor” usage category cited earlier. Other interfaces include I2C – a low-speed serial bus used to attached peripherals to a motherboard, embedded system, or cellphone; DVI, RS-232, parallel bus, CAN – automotive bus, DigRF – digital serial interface for 3G air standards; and even UART.

Re-spins

A little over half of the respondents indicated their previous design project required no re-spin. Of those acknowledging re-spins were necessary, 50 percent stated that only one re-spin was needed. About half as many reported by two re-spins were required and slightly less than 10 percent admitted to three re-spins.

The main reason for chip re-spins was the presence of logical and functional errors. This result tracks well with other recent studies that indicate more than 60 percent of re-spun ASICs fail due to logical/functional errors, not because of timing or power issues. This means that functional verification is now the most critical phase of the chip development cycle.

Figure 3

Verification Environments

When asked what type of verification was used for a current project and planned for future work, the largest groups of respondents selected Mentor’s ModelSim/Questa. This was followed by Cadence NC Simulator and Synopsys VCS.

Figure 4

Other software simulation environments consisted of tools from IBM, Altera’s QuartusII and Xilinx’s ISE, Synplicity’s Synplify, Dolphin’s SMASH and Catena’s Analog and Mixed Signal (AMS) Simulators, Aldec’s Active-HDL Simulator and homegrown systems.

In terms of emulators, most users listed Cadence systems, followed by Mentor and Eve. An interesting side note is that only Eve emulators saw a planned increase for future projects. Formal verification favorite was Formality, followed distantly by OneSpin, Real Intent and Certess. System Verilog lead the way in Assertion-based tools, followed by OVL and PSL.

Here’s where the results get interesting. When asked what type of virtual prototyping environments were currently being used, ARM was the favorite – but by a decreasing margin for future projects. Synopsys’s Virtio was the second most popular choice, showing projected growth along with CoWare, VaST and Virtutech. One should exercise caution when interpreting these results, since the slower pace in usage of ARM tools may simply reflect the growth of virtual prototypes in non-telecom related industries.

Figure 5

Looking at the other end of the prototyping spectrum revealed that Synplicity was used more often for ASIC prototyping with FGPA-based systems – at least in the market areas highlighted by this study. ProDesign followed second, then came Dini and Gidel. It must be noted, however, that 36 percent of respondents still used custom-built FPGA-based prototyping, though the percentage was on the decline for future projects. This marked decrease in custom-built systems may attest to the growing complexity of ASIC designs and hence the corresponding complexity of FPGA prototypes.

Conclusions

This survey points to the changing dynamics in ASIC prototyping tools and methodologies. Prototyping of specific blocks on an ASIC core now seems mandatory, especially since ASICs continue to increase in design complexity. This complexity is manifested by an increase in logical and functional errors in the chips, which has resulted in a need for more complete verification tools and methodologies.

But prototyping itself has taken on a new dimension with the advent of virtual prototypes – used more often by software designers – and FPGA-based prototypes used by chip hardware engineers.

These trends have been confirmed by other studies. For example, Aberdeen’s “Best in Class” study cites verification as one of the most prevalent concerns in chip companies. Chip Design Trends reports, which tracks ASIC pre-silicon architectural trends, confirms the growing complexity of ASIC chips – at all levels of design metrics. Contrasting this complexity with the continued decrease in ASIC starts suggest that ASICs may be getting larger in size though less numerous in unique projects. All of these trends support the growth of prototyping as a key element in future chip designs.

On the business side of the equation, one should note the shift away from corporate electronic expenditures to the rapid increase in consumer’s consumption of electronic products. The consumer world is outpacing the corporate world in the purchase of electronic goods, but there is a caveat: Consumer electronics have a shorter time to market, high product volume but lower cost per unit that corporate electronics. What does this mean to chip designer? It means that they must find a way to reduce ASIC re-spins, such as with ASIC prototyping.