By Ed Sperling

Santa Clara, Calif. –There are three new buzzwords you’ll be hearing a lot about in coming months: ecosystem, reusability and platforms.

We’ve all heard them many times before, of course, but we’re about to be barraged with them. As the price of developing SoCs continues a race for the stratosphere, the table stakes for getting into the business, doing something wrong that could put you out of business, or doing everything right but miscalculating the payback are potentially career-limiting moves.

ARM joined hands with the Common Platform last week, and today at the opening of the ARM Developers Conference the company—with the help of Common Platform member Chartered Semiconductor–began detailing just how ugly the convergence of technology and business has become.

ARM sees an upside in all of this, of course. Its partner base is growing, which means an increase in IP licensing and an emphasis on reusable, integrated IP blocks. Complexity feeds into the IP licensing model, particularly when the IP is integrated with other IP blocks and verified to work as a package.

Warren East, ARM’s chairman, said the macro market changes are opening vast new opportunities for those who can take advantage of them. The difficulty is mapping the changes to the right features, the right form factors and the right market segments, some of which are still ill-defined.

 “In Web 2.0, there is no typical consumer yet,” East said. “There in lies lots of opportunity and excitement.”

ARM’s focus on energy efficiency, which years ago was considered a plus, is now considered “the killer feature,” East said. Adding the ability to assemble devices relatively quickly using integrated and tested off-the-shelf parts—which includes IP—to help shield system developers from some of the complexity only makes the package more attractive.

But none of this totally gets around the growing complexity and rising risk, which accounts for the interdependency that has sprung up in the electronics industry. Kevin Meyer, VP of industry marketing and platform alliances at Chartered, said it now requires 5 million units be shipped to recover design costs—and that’s providing you’ve done everything right. The cost of a missed market window has risen from 8 percent two decades ago to 24 percent, which is enough to kill many companies.

“The smart companies will figure it out and offset up-front fixed costs by taking advantage of recurring costs,” Meyer said. “That means greater design re-use.”

He said companies also have started to do business differently. While foundries are creating new processes every two years, keeping pace with the Moore’s Law road map, many of their customers are skipping process nodes. “The 40nm to 45nm process node is not one that everyone will take advantage of.”

He said some companies are moving directly from 65nm to 32nm, and will likely ride that process a half node to 28nm to minimize costs and risk. “If you make an incorrect choice, it’s difficult to get back,” he said. 

By Ed Sperling

The idea that IP blocks would be as interchangeable as Legos is proving impossible to implement. In its place, consolidation of IP vendors touting integrated suites of IP are becoming the rule rather than the exception.

This week, both ARM and Virage Logic began touting integrated packages of physical, memory and logic IP, along with tighter relationships with big foundries. Both deals are significant from an SoC perspective, because they point to a maturing market for IP, where complexity, increasing costs and fewer customers at the bleeding edge are shrinking the number of players.

This should sound very familiar to anyone who has watched the EDA industry over the past decade. Integrated flows replaced individual tools, and even in cases where the tools offered in those flows weren’t best of breed, the value of the integrated pieces proved at least, if not more, valuable to many designers than having the best point tools. And in the case of IP, consistency and guaranteed peformance is at least as important as innovation.

IP vendors won’t get off that easily, however. While IP does shorten the development process, each IP block has to be verified for every manufacturing process. That means dozens of iterations for every IP block, and at the most advanced nodes where processes are not well defined and tested, it still might not work right.

That puts the burden on the foundries and the IP developer to raise designs to a higher level of abstraction, something that becomes more difficult at every process node. The goal, according to Simon Segars, general manager of ARM’s Physical IP division, is to “abstract away the underlying horror.” ARM inked a deal with the Common Platform companies—IBM, Chartered Semiconductor and Samsung—to jointly tackle the integration and consistency challenge.

 “There’s a lot more integration than you’d expect,” said Dean Freeman, an analyst at Gartner. “The advantage is that ARM is networked and integrated with everyone because of its cores—everything from cell phones to the Power architecture.”

Virage Logic cut a similar deal with IBM and Chartered, and a more extensive one with TSMC. The TSMC one is particularly interesting, because it involves what amounts to custom work for top customers—something that Virage has the right to refuse if it doesn’t think it can turn a profit on the deal.

“What we’re finding is that there is more and more investment in new and existing process nodes,” said Brani Buric, executive vice president of marketing at Virage Logic. “Everyone is trying to get the maximum out of 90nm so they’re going to 85nm and then to 80nm.”

He noted that TSMC wants IP available as early as possible for each half-node and every new process node. But more than anything, it more tightly integrates the front end of design with back-end manufacturing. Now the question is how much pain that eases for what goes on in between.

By Ed Sperling

Sept. 24, 2008—Santa Clara, CA—Verifying intellectual property blocks at the bleeding edge of technology is as much guesswork as it is engineering, and the result is often a combination of bad yields, bad chips, and truly bad business choices.

Two panels at the GSA-IP conference here looked at the chip design business at the most advanced process nodes, both arriving at similar conclusions. Because IP has to be developed as early as possible for each node, and because process technology is not stable at first, the marriage starts out like two people who have never met. At best it doesn’t work optimally. At worst, it’s a disaster.

“If I have a brand new standard and IP, I will do the best I possibly can at every node,” said Kamalesh Ruparel, VP and general manager of ASIP Solutions at Virage Logic. “But it can’t be 100% validated. The only thing we can do is put a process in place for consistent improvement.”

Ming Hsu , VP of worldwide IP support at foundry UMC, called it a “chicken and egg problem. We know the process is not mature. It has a learning curve, and that takes time.”

Ruparel noted that large customers often get the benefit of lots of attention from the foundries and know which questions to ask. Midsize companies, meanwhile, typically don’t get fully validated IP. “It is a nightmare for them. You’ve got DFM, ever-changing parasitics and new SPICE models. The problem is that a lot of customers don’t know what to ask for. IP is moving so fast that what we see a lot of times is buzzwords.”

Even where digital IP can be verified, analog typically cannot. The list of things that can go wrong in a mixed signal SoC are endless. Robert Heaton, director of analog solutions architecture at MIPS Technologies, said there are no consistent methods for verifying mixed-signal chips. “It’s not universally formalized,” he said. “There are no tools.”

In addition, because IP is changing so quickly and chips are becoming so complicated, the checklists that companies use to make sure they’ve checked everything are quickly outdated, Heaton said.

Nevertheless, it often is the IP that is the problem in low yields and chips that don’t work. Wayne Dai, CEO at VeriSilicon, said his company has a 90 percent rate for first silicon. He said the other 10 percent is almost always due to IP problems.