By Pallab Chatterjee
At the most recent Denali Memcon, there was a panel discussion and debate about the future of DRAM and possible successor technologies. The discussion was moderated by Cadence’s Steve Leibson and featured Bob Merritt of Convergent Semiconductor, Barry Hoberman of Crocus, Ed Doller of Micron and Marc Greenberg of Denali/Cadence.

The topic of the discuss was based on the growing trends in power efficiency, process scaling, and data retention as a changing environment for DRAM’s use in enterprise applications. New technologies have come and gone the past 50-plus years in solid state memory, and the debate about DRAM’s longevity has come up several times in the past. The presentations an positions of the 4 panelists were quite different, and ran the spectrum from use model, to business model, to technology issues.

Bob Merritt of Convergent started with the changes in the enterprise space that are driving the discussion. The unifying memory architecture from the ’80s was driving systems to use a central memory store for both processing and graphics memory. However, there is a shift in the type of data being created as the enterprise moves from a data-processing model to a multimedia model. As a result, graphics memory (GDDR) has become the only application for which this specific type of DRAM is still being used.

Also, the data processing has shifted from the corporate- and PC-centric side to the customer-centric side with mobile and smart devices. This has led to the conclusion it is not DRAM itself that needs to be replaced. It is the business model associated with DRAM. The historic model was based on a commodity model rather than a value-add model, which limits the ability to market into new and diverse markets.

Barry Hoberman of Crocus Technology presented the technology case for Magnetic RAM or MRAM. The cost per bit for MRAM is not on par with DRAM at this time, but in the near future it will be reaching cost parity as a solution with a DRAM/control logic/battery for NV applications. As DRAM applications stretch further in the consumer product space, additional features related to SRAM and NVRAM (flash) become more prevalent. From an embedded use perspective, MRAM processing is more compatible and less of an overhead than FLASH compared to CMOS. Hoberman concluded that with the shift in application space, MRAM will be a cost-effective and viable technology for systems.

Ed Doller of Micron, gave an overview of five technologies – FeRAM, MRAM, FBRAM, TRAM, and PCM. The FBRAM and TRAM technologies are not in production today, so their viability for being a near-term replacement is low. FeRAM and MRAM, while in production, are not application-compatible with DRAM and are not scalable to the same degree. This leaves Micron with the PCM technology it recently acquired from Numonix. The technology is in production and is scalable, but the use and application are not fully DRAM compatible. Doller said there is no need to replace DRAM immediately, but a replacement will be needed within the next five years.

Mark Greenberg from Denali/Cadence took the position that DRAM won’t be replaced at all. From its start in the 1970s the technology has undergone over 50 design iterations. The technology and concepts behind the DRAM date back to principles and components from the 18th century (capacitor) and early 20th century (transistor) and are not outdated. The cost of the technology is very low for the end product on a per unit (bit cell) basis. And while there are process challenges, there is no reason to believe that these are insurmountable as logic processes have similar challenges. And finally, Greenberg asked non-believers to show him a silicon technology that was superseded solely on continued manufacturability. He said DRAM’s demise is premature.

The overall summary from the audience questions was that as systems applications change, there are memory options, but DRAM will still play a major role

By Ed Sperling

Single event upsets used to be as rare as some elements on the Periodic Table, with the damage they could cause relegated more to theory than reality. Not anymore.

At 90nm, what was theory became reality. And at 45nm, the events are becoming far more common, often affecting multiple bits in increasingly dense arrays of memory and now, increasingly, in the logic. Known alternatively as soft error rates, these errors increasingly must be accounted for in designing SoCs, FPGAs, embedded IP and memory chips, adding to the cost and the complexity of these devices and straining power budgets with error correction technology.

“About two years ago most of the system companies, when they handed down the spec, there were a few lines of code in there called SER, or soft error rate,” said Tom Quan, senior director of EDA and design service marketing at TSMC. “It used to affect the RAM more, and you had to put in error correcting. The issue now is the logic. It’s so dense already, and it’s going to get denser as we go to 28nm and 22nm. “

Already, the problems have moved beyond a single-bit error. Olivier Lauzeral, president and general manager of iRoC Technologies, an independent testing firm, said the level of single-bit errors has remained stable as manufacturing processes moved from 130nm down to 45nm, but the number of multi-bit upsets has risen dramatically. That creates an even bigger problem. While it is possible to correct for single-bit errors, it is not possible to detect more than two bit errors at a time or correct more than one.

“The mechanism we are dealing with is that charged particles travel through silicon for a certain range before losing their charge,” Lauzeral said. “In the memory, a zero or a one is held by a small charge, which is the critical charge. If a particle deposits its own charge, it can flip the one to a zero or a zero to a one. At 65nm, the charge is 1.1 volts. At 45nm, it is 0.9 volts.”

Sources of the problem

There are two known sources of soft errors: One is caused primarily by alpha particles emitted by decaying radioactive elements while the other is caused by stray neutrons, which are present in great abundance. As the voltage and capacitance have been reduced in conjunction with the finer geometries at each process node, the destructive power of these particles has increased proportionately.

“Flip-flops were no problem before 130nm,” said Lauzeral. “As we go to 90, 65 and 45nm, the failure rates are increasing.”

SRAM is particularly sensitive to soft errors because the way the charge is stored. In fact, that is the primary reason why Actel has shifted away from SRAM to flash memory. In FPGAs programmability has to reside somewhere, and historically that’s been in SRAM.

“With flash, you can’t get enough charge on a floating gate to cause an error,” said Mike Brogley, product marketing manager at Actel. “SRAM is more sensitive. You can do some things to mitigate it, but it’s difficult to protect from the SRAM effect without sacrificing area and performance.”

Xilinx, which has been working on the problem for nearly two decades, has developed an epitaxial layer on a heavily doped substrate for parts used in outer space, where highly charged alpha particles can wreak havoc on electronics. Gary Swift, senior staff engineer at Xilinx, said the real concern in space is latch-ups or gate ruptures, which can destroy a device.

“In space, you should monitor your configuration continuously,” said Swift. “For commercial applications, Xilinx provides reference designs to do the same thing. Most of our commercial customers are happy with detection of single event upsets. In the Virtex-5 devices, you also can correct a bit error autonomously. But even as we scale to future nodes, these events are relatively infrequent at sea level.”

Swift said that most people are comfortable re-booting their computer or cell phones a few times a year, if there is an upset, but their tolerance would be severely tested if they had to do it once a day.

Particle physics

Studies of alpha particles began with atomic bombs in the 1940s. The field of study shifted to cosmic radiation in the 1970s because there was concern that spacecraft and airplanes could be affected by the more highly charged alpha particles in the upper atmosphere. The study was expanded even further to include terrestrial neutrons (as well as protons) in the 1980s by computer systems vendors, which were concerned about the reliability of their systems.

By themselves, neutrons cannot affect the systems because they carry no charge. But they can merge with other neutrons to create a heavier nucleus, which does have a charge. Error correction in DRAM was one of the first attempts at addressing this problem in the semiconductor world. In addition to stray neutrons, some DRAM packaging contained trace levels of decaying radioactive material from elements such as thorium, polonium, radium and uranium, which in turn produced alpha particles.

All of those effects proved manageable at 1 micron and above. But as Mentor Graphics chairman and CEO Wally Rhines has said publicly, at deep submicron geometries the laws of physics don’t change, but they are more rigorously enforced.

Where the problems strike

“We’ve got several customers in the telecomm space who were seeing system-level failures from these effects,” said Actel’s Brogley. “In an FPGA, these can change the circuitry. They can disconnect a customer or completely change the system. It could be benign or it could be a basic change.”

That threat is less severe in ASICs, where everything is hard-wired, and it rarely happens in software. In fact, Lauzeral said software can be used to mitigate the problem. “You can use an algorithm to protect data. In network communication, for example, when a packet is corrupt you can recall it. But if you get corruption in the addressing of where that packet needs to go, you have a problem. If data is corrupted it’s less of a problem than if it’s the base station for cell phones or the braking or driving system of a car.”

In most cases, there are workarounds. Even in packaging, impurities can be removed for a significant amount of money. But increased density—caused by more bits in a smaller space, even though the bits increasingly are smaller—is elevating the problem out of pure research and into mainstream designs. What remains unclear is just how much extra these workarounds will add to cost, particularly in sensitive consumer markets, and what the overall effects will be as we progress from one process node to the next.