System-Level Design sat down to discuss where the value has shifted in the supply chain with Tom Quan, director at TSMC; Kalar Rajendiran, senior director of marketing at eSilicon; John Koeter, vice president of marketing in Synopsys’ solutions group, and Phil Yastrow, product marketing manager at Avago. What follows are excerpts of that conversation.

SLD: Do you get more value as a customer than before?
Rajendiran: The rule of thumb used to be that you got 15x your investment that was good. If you invested $30 million and you were going after a $450 million market that was good enough. The problem is that it’s no longer $30 million to do a 40nm chip, it’s more like $80 million. And on the other side the markets are no longer generalized. It’s no longer a $450 million market. It’s probably a $200 million market. So in the past you might have been satisfied with 30% market share. Now you need 80% market share. Moore’s Law is great, but the reality has changed the problem from a technology issue to a business issue. The ROI has to be higher. You can’t change the end market.

SLD: What differentiates one chip from another in the future? Is it software or hardware?
Rajendiran: It’s both. If you ask a software engineer and a hardware engineer they’ll have their own take on which one is more complicated, which is harder to test and which is harder to break. But the real smart companies figure out a way to not just build a chip, but also the firmware and the software stack. If software is completely new, there’s a higher probability it will have bugs in it.
Koeter: At 40nm, if you look at the total cost of a chip, the cost of the software will just exceed the cost of the hardware.

SLD: Is that the whole stack?
Koeter: It’s what a semiconductor company would develop. It used to be low-level drivers. Now it’s highly integrated, sophisticated software. But 40nm is the crossover point. So if you look at semiconductor companies, increasingly they’re creating value through software engineers and also their architects. They absolutely want to move up. Unfortunately, every semiconductor company I talk with says that while they put 50% of their costs into developing software, they don’t get any return on that. They don’t get to charge for the software.

SLD: Does that mean Synopsys going to buy an RTOS company?
Koeter: We have a very strong push in this area. Recently we announced an M-language synthesis tool (Synphony). We’ve also been in virtual platforms for three or four years. Systems historically has been a very fractured space, but that’s getting to be a strong opportunity for EDA companies.

SLD: Is the value in the pieces or the integration?
Yastrow: Both. You have to have good IP and you have to have a way to integrate it. You have to have a way to make it work in a customer application. This comes back to channel modeling and how the package fits in. But it’s interesting when we start talking about software vs. hardware. It’s easy to argue that everything is software. People are writing RTL, getting the code to work, making sure they’ve covered all the corner cases and verifying it all. We’re seeing with Moore’s Law that verification is becoming a huge, huge chunk of the work.
Koeter: It’s 70% for the hardware, and then it depends on how you validate the software.
Yastrow: So not only do you need the great IP—memory, logic and I/Os—but you need someone to take that and integrate it first in the form of RTL, and then for the physical designers to make sure it meets timing and it meets power budgets.

SLD: At 32nm and 28nm we’re starting to see restrictive design rules. How does that affect all of this?
Quan: That’s for better yield in the long run.

SLD: But TSMC also is rating IP, right?
Quan: At 40nm we started asking customers and IP providers to run full DFM checks on IP blocks or the full design. It used to be recommended but not mandatory. One of the reasons for this is we’ve seen a lot of layout patterns that might not be reproduced perfectly in silicon. That will affect yield. At 28nm it gets even more difficult in terms of lithography, CMP and DFM. If we give the designer less freedom then it’s easier to validate and check and have better yield. You used to be able to put a lot of bends and jogs into a polygon. Now you try to have more regular structures with no bandwidth jogs. That will facilitate double patterning at future nodes, too.
Rajendiran: Customers don’t like restrictions of any kind. People are talking about orthogonal routing, which gives more flexibility. And companies are developing libraries so that when lithography progresses everything works fine at future geometries. If that can be achieved, every designer will be happy.
Quan: We build our own libraries and we collaborate with IP providers on theirs. Once you get the signal out to the pin and you do place and route, you also know which direction it should go. But it does require a joint effort from the IP provider, the company building the library, and the tool provider to make sure the whole design flow can use these new cells.
Koeter: It certainly makes life harder for an IP vendor. Now we have to worry about multiple layouts of the same IP block. You’re going to see more consolidation in the physical IP space.
Yastrow: We will find a way to deal with it. Competitively, everyone is dealt the same cards. But that’s not the only challenge. Voltage levels are also a problem. You’re trying to comply with standards back to the system level and getting the customer channel to work. You get a performance hit from a higher voltage level, and then the standards run at 1 volt instead of 0.85.
Koeter: USB has to have backward compatibility to 5 volts. Try doing 5-volt tolerance in a 1.8 volt I/O device.

SLD: Does a 3D stacked-die approach change where the value is—providing it works?
Quan: It’s a way to put more stuff in the same area. People have been going down the path of shrinking the die and getting more performance. But there’s always some technology that cannot scale down that easily, like analog and RF. In memory if you have 1 megabit and you want 4 megabits you build them horizontally or you stack them. That’s already been done. From an SoC perspective, where you’re mixing different blocks—memory, analog, RF, digital baseband—it’s a different approach to how you build them. But there will certainly be challenges. Through-silicon vias present more challenges in terms of validating the timing through these vias. And when you stack up things, the thermal profile will be different.
Yastrow: There are two things we know for sure. One thing is customers need more memory. The other thing we known is it’s becoming more difficult to combine an eDRAM process with a logic process and to be able to have them both optimized. Now you end up with tradeoffs. You optimize for the embedded memory or the logic. That’s why 3D where you have a memory chip and an ASIC that are tightly coupled is very real.
Koeter: One of our concerns as an IP vendor is whether 3D ICs will change the fundamental way chips are partitioned. Will all the analog be put in a 130nm or 180nm and the digital be put in a 32nm or 22nm chip. We’re looking at it all the time and talk to customers about it, but right now there’s no indication that’s a significant trend. People continue to integrate analog and digital with big ‘D’ little ‘a’ chips. What they’re doing in 3D is stacking memory on top of those chips.
Yastrow: Besides stacking we’re also seeing new standards developing beyond DDR3. You will still have a discrete chip. But I don’t think you’ll see as much embedded memory on chips. Maybe there will be some SRAM and DRAM, but it’s getting harder and harder to make those two match. So maybe you’ll have two side by side, instead of on top of each other, with an extremely high-speed link between them. That’s why some of these standards that are being developed, like GDDR5 (graphics double data rate, version 5).
Quan: There has been talk about a silicon interposer where instead of stacking them you connect them through a silicon substrate.
Rajendiran: That’s already happening. 3D is taking it to the next level. Will it happen? I think it will. The question is how soon. I don’t think it will happen in the next two or three years because it is easier said than done. It’s a bigger floor plan issue.

SLD: Does the highest value go to people solving the hardest problem, such as power modeling?
Yastrow: It’s a table stake. You have to reduce the power. You won’t necessarily get more money but you won’t lose the design.
Koeter: I absolutely agree. At least you won’t lose money.
Quan: The system-level spec is only getting harder and harder. Even though you leverage the latest process, so you can reduce power and leakage, you still have to have a lot of design techniques. If you have better power consumption, you have more chance of winning the design.

By Ed Sperling

The market for EDA and IP was down in Q4 of 2008. That should come as no surprise to anyone.

Nevertheless, there were a couple of bright spots even in that bleak picture. Statistics compiled by the EDA Consortium show IP sales were up 7.6 percent, which is a reflection of increased complexity in making SoCs at 65nm and 45nm, as well as better tools and standards for integrating that IP.

IP is about a $1 billion market, according to EDAC Chairman Wally Rhines. Within that sector, ARM is by far the largest single provider of IP and posted most of the gains, he said. Other beneficiaries include MIPS, Virage Logic, Denali, the IP divisions of Mentor Graphics and Synopsys, and a number of smaller players.

Other bright spots:

·      Parasitic extraction, up 10%

·      Process simulation, up 18%

·      Mixed Signal, up 39%

·      Services, up 25%, although much of that is due to eliminating contractors and taking the work in-house.

Most of the growth follows the trends in system-level design, with the greatest growth showing up in the areas of most pain. Since those numbers were recorded, however, there also are glimmers of life in other parts of the industry.

“What we’re seeing is a bounceback from desperation in the fourth quarter to a point now where there is a need for finished goods,” Rhines said. “The February [Semiconductor Industry Association] numbers were negative. In March, there were signs of a bounceback. But the semi industry and electronics tend to sort out early and prices readjust. EDA is one level removed from semiconductors, which makes it harder to read anything into the numbers.”

The total EDA industry was down 17.7%. But industry sources say at least part of that was skewed by Cadence’s change in the way it recognizes revenue, from up-front recognition to recording revenue as it is received. Taking Cadence out of the picture, the industry declined about 8%. That’s still severe, but at least it’s a single-digit decline.

Still, the tools industry is hardly on solid ground. More than half of semiconductor companies are rated “B” or worse. If a number of semiconductor companies go out of business, the overall effect on the EDA industry would be profound.

On a global basis, Europe’s decline was in the single digits while the rest of the world showed double-digit declines. Europe is very system-oriented, but some of its chip makers have stumbled badly in the downturn. 

By Ed Sperling

San Jose, Calif.—Keeping track of the rising costs for designing and producing new chips is hard enough. Keeping them under control is even tougher.

Costs are skyrocketing at every new process node, and the Moore’s Law road map appears to be intact to about 6nm, said Chi-Foon Chan, president and COO of Synopsys, during a keynote speech at ISQED this week. He said that in addition to cost, power, size and packaging, which have traditionally been the top issues for engineers, they now have to worry about “interdisciplinary integration” and signal integrity.

“Every node adds $1,500 to $3,000 to the cost of a wafer,” he said. “Gartner estimates that the cost of a wafer for leading-edge processes now costs $7,000.”

And that’s just the manufacturing cost. The design costs and time-to-market pressures are forcing engineers to incorporate more third-party IP blocks than ever before.

“What’s apparent is that the ecosystem has to change,” Chan said. “In the future nanotechnology and exotic materials will be playing a huge role, but nanotechnology is a discipline and not an industry. The key on all of this is integration.”

He noted that the future will include everything from bioMEMS, MEMS, photonics, carbon nanotubes and molecular computing, where interconnections may be done by quantum entanglement. 

Also in the future will be new forms of packaging, which will include 3D stacking, functional integration and stronger partnerships.

If you think things are bad, be glad you’re not in the Taiwanese foundry business—where the pain level is strangely uniform.

TSMC’s sales dropped 59.5% in February compared to the same month last year, and 7.5% compared to January. How many ways can you spell ouch? 

UMC’s numbers are down 56.9 percent in February 2009 vs. the same period in 2008. That’s pretty close. In fact, it’s remarkably close.

This kind of information is only available in Taiwan. SMIC, based in Shanghai, and Chartered, based in Singapore, don’t report monthly sales numbers.

Nevertheless, there was at least some encouraging news out of Chartered. It said that sales seem to be stabilizing and wafer starts appear to be increasing for Q2. 

There is evidence of this showing up in other parts of the market. U.S. retail sales, excluding big-ticket items like cars, show modest increases in areas like clothes and consumer electronics. Numbers were up in January and February. It certainly wasn’t a robust gain, but it wasn’t negative, either. That will translate into new design starts sometime in the next few months, which barring any more major drops will start this whole cycle rolling again.

Design activity has to begin at least six months prior to any turnaround, which means that if the overall economy is expected to show growth in 2010,  electronic designs have to begin by mid-year—perhaps even sooner.

None of this is perfect, however. Why, for example, did National Semiconductor just announce plans to cut 26% of its workforce? At least part of that can be explained by closing of an assembly and test plant in China and a fab in Texas. Too much capacity is expensive, and we wouldn’t be surprised if National ultimately begins outsourcing some of its work to foundries. Yes, it’s analog, but is it still more efficient to run fabs yourself, even if they’re fully depreciated, when TSMC and UMC are begging for business?

Meanwhile, in the FPGA realm, chip design is getting so complex that EDA vendors are finally beginning to find inroads. This is a market previously owned by tools from the FPGA vendors, which they readily gave away to customers at little or even no cost. That worked fine before the industry got to 90nm, and at 45nm it’s tough enough even with the best of tools.

Mentor introduced its Precision Synthesis Tool family for Altera’s Stratix and Arria families. Our guess is that you can expect to see a lot of activity in this market in the near future, and not just from Mentor. Synopsys’ purchase of Synplicity gives it a vested interest in the FPGA market, as well.

–Ed Sperling

It was a good week for globalization, but a bad week for the global economy.

ARM made a “strategic” investment in eSOL, a Japanese embedded software vendor. The real way to read this announcement is that ARM has bought its way into the Japanese car market, which is about the only way you can actually get into that market if you’re an outsider. Despite its prowess around the globe in many markets, Japan’s domestic market remains impossible for non-Japanese companies to crack. But the downturn is hurting Japanese companies, too. Remember when Japanese firms were buying up U.S. real estate in the 1980s?

The economy may be down, but that isn’t stopping Moore’s Law. Mentor Graphics issued an announcement that STMicro is using its Eldo simulator to characterize 32nm cell libraries. Seems like the folks in Europe are staying busy to keep from freezing (or at least to justify their jobs.) Get ready for more power islands, really complex verification—as if it wasn’t complex enough before—and lots of complaints about tools not doing enough because there’s now lots more to do. 

That’s only part of the shift, though. While companies like ST, TI and Intel push to the next process node, others are jumping a half node. TSMC is looking at half-node increments to stay ahead of the pack, which may explain why NEC has partnered with Virage Logic at 40nm.

Speaking of TSMC, did anyone notice that Intel is pushing its Atom chip into the commercial foundry world? The two companies inked a deal to collaborate on IP, platform and SoC solutions involving Atom. There are two ways to read this. One is that, in light of Intel’s $7 billion investment to upgrade its fabs, Intel doesn’t see Atom as a core part of its chip lineup. The other way is that Intel believes it can further reduce costs on its core platform by outsourcing some of the manufacturing. Our guess is there’s a little bit of both involved, meaning Intel is hedging its bets on whether Atom will really pay off while simultaneously giving it a chance to compete with ARM.

The competitive stakes for Intel are growing from a different side, as well. Intel has always been proud of its ability to maintain its own fabs. The spinoff of AMD’s fab business and a subsequent investment into that business by Abu Dhabi-based Advanced Technology Investment Co.—read huge oil company profits looking for a new market opportunity—could make even Intel question its go-it-alone strategy. AMD’s ploy is to open its fab to outsiders while reaping the same unbridled flow of information back and forth between fab and design team—while utilizing capacity from outside companies the way IBM has done with its fab in East Fishkill, N.Y.

And if that doesn’t make chip manufacturing interesting enough, Shanghai-based SMIC received approval from the U.S. government to export its 32nm technology to the United States. That SMIC has gone from 65nm to 32nm and is now talking about success at 45nm is rather surprising, considering the bulk of its work has been at 180nm. That the U.S. government isn’t putting up any roadblocks is less surprising—at least when you think about all those U.S. bonds being held by the Chinese government. The last thing the U.S. can afford right now is a trade war with China, and SMIC is one of China’s most important companies.

–Ed Sperling

By Ed Sperling

Santa Clara, Calif.—Feb. 5, 2009—Cross-cultural communication has always had its challenges, but globalization is raising it from the level of nuisance to necessity.

Across the board, from systems companies to those that develop the tools to build the components that go into those systems, building international teams that can embrace a single corporate culture has emerged as one of the big business challenges.

“The main learning about having different sites around the globe is respecting the culture of where that site is,” Rich Goldman, vice president of strategic alliances at Synopsys, said during a panel at DesignCon. “Engineers are the same around the world, so there is a certain level of communication that always works. But at another level, cultures are very different. What you may think is the worst thing possible is a normal part of culture for another country. You have to go to that country to experience it. That’s the only way to overcome differences.”

And overcoming those differences is essential. Cisco’s vice president of engineering, Sri Hosakote, said globalization is a core competency of every company that does business in a global economy. “It’s a skill that is mandatory,” he said.

Hosakote said one of the keys is getting employees in other countries to understand the corporate mission the same way employees do in a place like Silicon Valley. That frequently requires bringing managers to the United States, letting them sit in on meetings and work in Silicon Valley and sometimes even enrolling them in executive courses at schools like Stanford. He said when that happens, “they get it.”

“It takes two to five years to get a culture of globalization,” he said. “Collaboration is the hardest piece. It’s particularly hard when it comes to multiple sites.

But there’s more to operating in a global environment than just a common vision. There also has to be an efficient structure everywhere. Brani Buric, executive vice president of marketing and sales at Virage Logic, said that for every situation—whether the operation is located in a place where labor is cheap or expensive—the office has to be optimized.

“What we’re seeing with globalization is just the first phase,” Buric said. “A couple of years from now this will go way beyond product engineering and R&D. New markets are opening and we will see good product specs for markets in places like China. There will be R&D, specs, marketing, implementation and a sales channel in these places.

One facet of globalization is outsourcing. While outsourcing continues to gain ground in markets such as IT services and support, many technology companies believe the cost differential is not enough to offset the benefits of having their own operation—whether it’s R&D or sales—in a foreign country.

“Sometimes running it ourselves is cheaper in some ways,” said Kirk Law, vice president of systems products engineering at NetApp. “There are a lot of different ways to measure value. It’s not just a spreadsheet decision.”

By Ed Sperling

Feb. 4, 2009— Santa Clara, Calif. — Moore’s Law is still alive, but just how well it is depends on your perspective.

Paolo Gargini, Intel’s director of technology strategy, said the good news is that Intel can see its way to remaining on the Moore’s Law road map for at least the next 10 years. The bad news is that it’s going to cost a lot more money to do that—about $9 billion for fabs, $1 billion for technology and another $2 billion for products. And that’s at every new process node.

Speaking at DesignCon, Gargini said Intel is counting on 1 billion users of mobile Internet technology, 100 megabits per second of wireless throughput and 1 billion transistors on the go to turn a profit from that enormous investment. But the number of other companies that can afford to keep pace with their own fabs will continue to shrink.

From a technology standpoint, what will drive those changes are continuous shrinkage in the length of gates, the thickness of the insulation and voltage, as well as strained materials, high k dielectrics, metal gates and a host of new materials. In fact, Gargini said that in the future silicon may simply be the base material on which everything else is built. Intel is in the process of developing new deposition methods and experimenting with new materials and approaches. Those new approaches include nMOS, or n-type metal oxide semiconductor, quantum-field effect transistors (QWFETs), as well as nanowires and nanotubes.

Intel is on track to deliver 32nm chips this year, he said. 

By Ed Sperling

Santa Clara, Calif. — Feb. 3, 2009 — Build or buy has always been a question for system-level developers. There are time-to-market pressures to create and test a system, and there frequently are integration issues even with the best-qualified third-party intellectual property.

But what’s the actual tipping point where it makes sense to buy IP? Mark Gogolewski, chief technology officer at Denali, said it’s based on a factor of 10. If it costs 10 times more to build than to buy, then it makes sense to go outside.

Gogolewski noted that it generally costs IP vendors 5 times the initial investment to productize, sell, market and finance IP development. Profit-taking accounts for an additional factor of 3. Those numbers get multiplied, so it costs 15 times the investment to create a final product that can be licensed commercially.

The numbers for an IP vendor, however, can still be significantly lower than an internal development team within a semiconductor company. There is less overhead, more specialization, and sometimes there is an opportunity for re-use of code that already has been developed. On top of that, many companies simply don’t have the skilled engineers on staff to develop specialized IP, which has become dramatically more complex over the past decade.

Quality from third-party IP also has improved from the early part of the decade, when off-the-shelf IP blocks often caused more integration headaches than they were worth. They are now viewed as essential building blocks on complex chips, which is a testament that repeatedly throwing very smart people at a problem and learning from mistakes eventually pays off.

There also is enough critical mass in the market to be able to test IP designs in a variety of applications. “Our internal rule is that if there are not 40 designs a year, it’s not a viable enterprise,” Gogolewski said. “You even want more designs than that because not everyone will outsource this work at the same time.”

In addition, the companies selling the IP are likely to be around in five years. The majority of IP vendors at the beginning of the decade were small startups. Those startups have since been acquired or grown enough through their own sales and acquisitions to have gained staying power—even in the worst downturn in decades.

Virtually all the major EDA companies offer IP. Mentor Graphics, Synopsys and Cadence all sell IP blocks. And companies such as ARM, Virage Logic and Denali have grown large enough, and specialized enough, to have built expertise in the respective areas of focus.           

By Pallab Chatterjee

The tightening worldwide economy finally has forced the consumer products arena to adopt an aggressive single-SKU mentality for their products. This means companies are now making a single standard product that can be sold into multiple applications.

This marks a radical shift in the way products are being designed, a direction that makes the design and development process far more efficient. Already, this approach has begun making its way into flat panel TVs, mobile appliances and radios, with common designs that are targeted for the United States, Europe, Australia, and Asia. All of these products are platform designs that are firmware-programmable.

Two of the companies with major products on display this year at the Consumer Electronic Show that highlighted this approach were Xcieve and Imagination Technologies. Xcieve is a semiconductor company shipping standard product ICs to OEMS with a firmware development toolset. Imagination Technology is an IP core licensing company that also completes the design chain by providing reference designs and full application development software.

Xcieve makes a monolithic 0.18um SiGe single chip tuner for flat panel TV and PVR applications. What makes this interesting from a system-level design standpoint is that most of the other products on the market are traditional hybrid technology can tuners that are fixed-format, based on the wider variation component values. The other solid-state tuners typically utilize 0.25um SiGe technology and do not maintain enough performance margin to be adjustable for the different signal formats.

The new tuner (the XC5000) is DSP based, supports all major analog and digital broadcast standards worldwide, while minimizing the power requirements and component area. The small size makes the product advantageous for the new slim line LCD & Plasma displays as well as low profile PVR set top boxes. At this time the XC5000 has adopted by LG, Miele, Sony and others in their TV, combo TV/Monitor and PVR products.

All personalization for region of destination is done with a downloadable firmware routine rather than making component changes in the custom circuits. The chip has the ability to real-time monitor the incoming RF signal and dynamically adapt the output to produce a correct signal.

Imagination Technologies has both video and audio IP cores. The audio cores are proven in many designs by PURE, Bose, B&O, Philips, TEAC and Sony and support most of the DVB radio standards, as well the internet radio format model. These cores have an advanced firmware/software framework (called META AAF, or Advanced Audio Framework), which provides a comprehensive suite of audio codecs implementing all major audio formats including MP2, MP3, AAC, eAAC+, WMA, Dolby Digital, Real, plus audio post-processing tools. This is an application of the Imagination Technology META HTPP-Audio solution, which is made of IP blocks that include multi-threaded DSP cores, a customized Linux kernel, and a middleware application library in addition to the AAF product.

The company also released some multi-format HD display targeted multi-threaded PowerVR SGX543 core. This core brings high-performance shading and 3D graphics presentation to a large-format display, based on the same low-power, high-performance multithreaded cores that have been used on their mobile display cores. These cores are joined by a new frame grabber core, which provides for inter-frame generation for 240hz refresh rate applications on flat panel televisions. The use of multi-threaded DSP style cores, in these applications allows for in-application optimization through firmware such as optimizing the Flash 10 performance in browsers on MIDs (Mobile Internet Devices).

These cores and ICs are the new architectural direction of globally targeted semiconductors that are optimized for power and area. The targeting of “standards” such as dictated by the broadcast TV, radio and cell phone industries allows for companies to capitalize on their semiconductor design and manufacturing expertise rather than pushing the performance envelope beyond a usable limit. This trend is broadening in the industry as the communication standards solidify and more multi-function products (media servers, netbooks, graphics capture devices, etc.) enter the marketplace.

By Ed Sperling

One of the strange things about downturns is they force companies to re-examine what they do and question what kind of value they bring to the market. This is particularly true in the semiconductor world, where the average selling prices for chips has been sliding for the better part of two decades.

In the case of the chip industry, which is heavily cyclical, that leaves lots of time for reflection. And the latest trend seems to be somewhat different than the last downturn, which produced, ‘Do more with less.’ The current direction seems to be, ‘Do much more,’ although not necessary with less.

“Companies have to deliver whatever they were delivering before plus more value,” said Ian Mackintosh, president of OCP-IP. “For IP vendors, they need more software content—drivers, broader connectivity and more validation of the process they use. For EDA providers, they need more offerings. There will be a lot of fallout as a result of this downturn, and people will make acquisitions they couldn’t make a year ago. Products will get into a stronger sales channel. This is the classic integrate or die. Consolidation will do that for them.”

But there are two inherent business problems that have to be solved before system-level design can extract more value for its efforts. The first is a broader definition of exactly what’s involved in designing and developing a system rather than just a chip.

“EDA has to become the general contractor for design,” said Jim Hogan, a private investor in the technology world. “If you’re building an SoC, you’re most likely creating platforms for a vertical market using third-party IP and your own secret sauce. The problem is verification. You can’t run it with the application.”

That helps to explain some of the recent acquisitions and changes under way within the semiconductor tools world. Synopsys, for one, bought Synplicity for its FPGA tools and part of ProDesign to move into ASIC prototyping and verification. As Synopsys CEO Aart de Geus said, “All trends that existed before the downturn have not changed.”

De Geus noted that in the future, makers of semiconductors will have to deliver embedded software and even applications, which is the reason behind acquisition of prototyping companies like Virtio. “Everyone would like to have the chip before the software and they want to have the software before they have the hardware. These two statements may sound like contradictions, but increasingly they’re not.”

The other piece of the equation that needs to be ironed out is complexity. That helps explain Mentor Graphics’ intense focus on TLM 2.0, which is basically black-box technology to speed design across multiple areas. IP-XACT, which is aimed at making IP more plug-and-play, fits squarely into the TLM 2.0 world, as well.

Standards become stronger in dowturns because there are fewer dollars available for developing new technology. Most R&D budgets are flat to down. Even de facto industry standards, which typically precede the adoption of technology by standards bodies, grow stronger in a downturn because there is less money to challenge them.

“If you look at the systems space, ARM is the de facto standard in the wireless world,” said Hogan. “In the interconnect space, Sonics and Arteris are making a play, and the interconnect strategy will become important. It also will be important to have IP that works together. Chip Estimator is like the yellow pages of IP and IPExtreme is repacking silicon process IP blocks, but so far no one has a total solution.”

The same challenge persists in the software world. There is no uniform test bench strategy, so far, and application software is not part of that entire process. “Right now we have articulation points in software signoff, but with the application all we have is intent verification,” Hogan said.

In system-level design, the real mantra might literally be to think outside the box. Chris Rowen, founder and CTO at Tensilica, said the value in devices isn’t what’s in the box, but how it works on the network.

“It’s all about what it enables,” Rowen said. “When they put it on their customers table it has to now all the protocols and standards used by the end consumer, no matter what market it’s in. Chips need to know what the home services look like.”

And for the companies that design chips, or which create the tools to design and develop them, the end of the downturn could be a rather rude awakening to the new rules of the game.