By Ed Sperling
EDA revenue grew 12.8% in Q4 to $1.7 billion vs. $1.5 billion in the same period in 2010, and 10.1% sequentially from Q3 to Q4, according to numbers provided by the EDA Consortium.

For the quarter, the highest growth reported was in physical design and verification, which grew 30% year over year to $392.4 million. IP revenue also grew 13.4% to $432.2 million. Even services revenue grew 9.8%, an indication that either there is a shortage of workers or an astronomical increase in complexity. The largest category, CAE, grew 11.9% to $644.8 million.

On a geographical basis, revenue in Asia/Pacific led the globe with 34% growth, increasing to $419.6 million. The Americas grew 12.8% year over year to $726.3 million, which still represents the largest market. Europe, the Middle East and Africa also grew 11.8% to $306.1 million. Revenue in Japan was down 10.5% to $248.1 million.

By Ed Sperling
EDA software and IP sales exploded in the third quarter of 2011, increasing 18.1% to $1.54 billion, up from $1.31 billion in the same period in 2010. Sequentially, revenue increased 7.4% from Q2 to Q3.

What was particularly significant was that revenue grew in every major product category and in every geography, a sign that even mainstream designs at 65nm and below now require more EDA tools.

“This growth is phenomenal,” said Wally Rhines, chairman and CEO of Mentor Graphics and the charman of the EDA Consortium. “Semiconductor companies hit $300 billion in sales in 2010. This is a reflection that they are spending R&D at the traditional percentages again.”

They have little choice at advanced process nodes. Rhines noted that every process node brings a surge in new tools and requires more engineers. But while much of the manufacturing has shifted to places like Taiwan and China, the design work has remained centralized across a variety of markets ranging from the Americas to Europe, Japan and Asia/Pacific. That explains why growth in the Americas increased 22.4% to $706.7 million from Q3 2010 to Q3 2011. Asia/Pacific grew 17.6% to $322.4 million during the same period. And in Europe, the Middle East and Africa, growth surged 14.9% to $257.9 million.

CAE, which is the bulk of EDA, grew 10.5% to $556.7 million. IC physical design and verification increased 16% to $338.3 million; PCB and multi-chip modules increased 11.6% to $140.3 million; and IP increased 37.4% to $410 million.

“We’re seeing a number of factors driving this growth,” said Rhines. “The move to 40nm and 28nm requires new tools. The increase in re-use is driving IP growth. And the increase in complexity means you need new tools for things like ESL and resolution enhancement that you didn’t need before.”

He noted that EDA historically has a run rate of about 2% of semiconductor industry revenues. He said the recent numbers are very much on target.

EDA revenue increased nearly 18% in Q2, rising to $1.44 billion compared with $1.22 billion in the same period in 2010, according to the latest EDA Consortium numbers. Revenue was down 0.6% sequentially from Q1.

All geographies were up, year over year, with double-digit growth in the Americas, Japan, and Asia/Pacific. In addition, EDA employment was up about 3% year over year, and 1% sequentially. In the Americas, revenue was up 21% year over year; 18% each in Japan and Asia/Pacific, and 9% in Europe, the Middle East and Africa.

By category, CAE grew about 20%; IC physical design and verification grew 6%; PCBs and MCMs grew 22%; intellectual property grew 23%, and services revenue increased 20%.

EDA companies weren’t the only ones showing optimism. Semico Research issued its forecast that analog within the computing consumer and communications markets will grow 14%, 9% and 13% in 2011, 2012 and 2013 respectively.

Semico anticipates the market for analog will reach $61.9 billion in 2015. What’s particularly interesting is the consumer market will only account for about 23% of that number in four years; it currently represents 33% of the total analog pie.

By Gabe Moretti
Electronic computing systems have gone through an evolutionary cycle since the invention of the mainframe, and the process is continuing. Semiconductor technology, mostly based on CMOS fabrication methods, has enabled an increase in design complexity and device functionality that have revolutionized the world.

But 20nm processes may be the last that obey Newtonian physics. The next process, 14nm, must deal not only with atomic effects, but most likely with quantum effects. At those dimensions, the laws of physics laws are different and much more costly to obey.

The development of electronic computing devices
A brief history will help clarify this. Until the late ’60s, mainframes were the only way to execute computer programs. The hardware was built by electronic engineers, the operating system and device drivers by system programmers, and application programmers developed application programs to automatically solve specific problems.

The introduction of microprocessors followed the increased capacity of manufacturers to diffuse sufficient transistors on a die, and opened the opportunity to build a computing system on very few—and eventually only one—printed circuit board. The systems were still designed using standard parts from suppliers offering both digital and analog components and continued the separation between hardware and software.

Synopsys’ introduction of the first commercially available digital logic synthesis marked a watershed in the design of computing systems. By 1992 Design Compiler was mature enough to understand the semantic flavor of both VHDL and Verilog. It allowed designers to develop integrated circuits that replaced the functionality of standard components to such an extent that it made that industry relatively obsolete. Only analog components survived, because no one had found a way to synthesize an analog design in a cost-effective manner.

Today ICs containing hundreds of million of transistors are built almost routinely. Analog functions can be easily integrated with digital function using IP cores, or, in some cases, even take advantage of specific analog synthesis applications.

The EDA industry is focused on enabling engineers to do the same thing with every processing node. Integrating more functionality in an IC seems the “thing to do”.

Reality will force a new paradigm.
But during the impressive growth in computing capacity of an IC, the semiconductor industry has failed to manage costs. Financial realities are replacing engineering capabilities as the determining factor in deciding what to build and what markets to serve. The ITRS road map shows that unless a new development paradigm is found, the cost of developing an ASIC could reach the $1 billion mark by 2015. This, of course, is an unsustainable proposition. It just does not make sense.

The generally accepted architectural solution today is to design and build a family of devices. Starting from a common hardware architecture, designers count mostly on software to tailor each device to specific tasks or human interfaces. The aim is to keep manufacturing costs constant, or to slightly lower them by increasing yield, while producing end products that look different enough to entice consumers to purchase a new device in the same family every couple of years.

This strategy is enabled by the fact that CMOS fabrication technology has remained constant enough, from a product design point of view, to allow engineers to focus on integration as the primary goal. The increasingly complex DFM, meanwhile, has followed the rules of Newtonian physics. The last process that supports this approach is now being ready for commercial release—the 20nm node.

To design and develop such complex devices, engineers have had to face the daunting task of designing hardware/software systems in the same amount of time as was required for hardware systems. This has turned out to be impossible, because no one can debug a software system without executing it on the hardware it is destined to use. EDA vendors have used their creativity to provide virtual prototyping capabilities. Just like in the old days when engineers developed instructions set simulators of the CPU, today virtual prototyping aims to allow the development of a model of the hardware system before the system prototype is available.

This is not an easy task, and one that has yet to reach maturity. In the last couple of years Synopsys has focused on developing and supporting efficient virtual prototyping. After purchasing Virtio a few years ago, it discovered that having a virtual prototype of a CPU alone was not enough. It looked for complementary technology and eventually purchased both CoWare and VaST. Last week Synopsys announced the result of the integration of these technologies: the Virtualizer. The product is a big step forward, but it still is based on the common methodology of building a compute system in CMOS.

A possible future
The EDA industry was built to provide tools for hardware designers. This has now morphed in supporting system designers, as well. But the tools still keep hardware and software as separate disciplines that require new methods to co-exist efficiently. In the future designers will have to look at providing complete system solutions that erase this distinction. A system architecture should not be based on the characteristics of hardware or software, but instead on the characteristics of the system itself.

Companies still have to address four fundamental issues in deciding to develop a product: cost (time and resources), power use, chip size and packaging, and product family ROI. These four items taken individually for a new ASIC program may be difficult to solve until development is so far along as to make it impractical to even start the project. That means system tools will be needed not just to estimate, but to predict with enough accuracy both the power consumption and the size of the device.

Reusable IP is a partial solution to the problem, but it is still marketed as a replacement to the old component market. In insufficient number of standards make the choice non-deterministic, at best. Hardware IP integration is still difficult and time consuming as busses become more and more complex. Even with advances in virtual prototyping, software development and integration will continue to increase in difficulty, especially due to the lack of standards in software architecture. There also are no standard platforms—true computing systems tailored to a specific application market. Standard platforms can deliver solutions to both power consumption and packaging, thus simplify the problem considerably.

This isn’t without risk, of course. It potentially puts EDA vendors in the position of competing with their customers. But if the customers fail, so will the EDA industry. EDA must still provide all of the tools necessary to develop a product specific platform, should a customer choose to do so, but an increasing number of companies will require system solutions, not just an inventory of IP components. To successfully grow, EDA must be in the system business, not “just” in the tools business.

By Ed Sperling
All is well in EDA—really. Every sector in every geography showed growth in Q1 compared with the same period in 2010, and in many cases that growth was in the double digits.

Perhaps nowhere is this trend more evident than in the drop in services revenue. In down years services revenues are up because many companies contract services rather than hire engineers internally.

“We saw 16% growth in EDA and IP, while services dropped to 2.2%,” said Wally Rhines, chairman of the EDA Consortium and CEO of Mentor Graphics. “Normally, in a downturn you get rid of staff and temporary staff, and in an upturn you hire back more temporary employees and use outside services. We’re now one year into an upturn and we’re seeing more hiring and less services.”

Here are some of the standout numbers:

1. Emulation grew 66%, in part because software engineers are now using these tools;
2. Design for test grew 45%;
3. PCB design grew 28%;
4. Logic verification grew 25%.

“I’ve never seen a quarter where all areas were up simultaneously,” said Rhines. “There is strength in every sector, geography and grouping.”

Still, Rhines noted that caution should be used in assessing these trends. They are based on one quarter of data. A full year of data is necessary to understand what’s really changing and to draw meaningful conclusions.

Bernard Murphy talks with System-Level Design about what’s changing in the semiconductor design area, how 3D stacking will affect design and what’s needed in EDA tools.

Open-Silicon’s CEO talks with System-Level Design about getting the business priorities of designing a complex SoC in line with the technology; why getting chips out the door on time is critical and why it’s not happening.

By Ed Sperling
The EDA industry will grow and 3D stacking eventually will kick into gear, but nothing will be quick or consistent until the EDA vendors overcome a fundamental issue: Cutting the costs out of designs.

Gary Smith, president of GarySmith EDA, kicked off the opening session of the annual Design Automation Conference in San Diego with a chart showing EDA revenues will increase from $4.9 billion in 2011 to $6.6 billion in 2015. But while the growth line points steadily up and to the right, he said that for EDA to really succeed the price of an SoC must be held below $50 million.

“The EDA industry is responsible not only for enabling the design process,” Smith said. “It is responsible for developing a level of automation that allows the design process to be affordable.”

He said design teams should be no larger than 30 engineers for 100 million-gate designs for a cost of $18.7 million, but that with 160 software engineers that still pushes the price up to $75 million for an SoC. He added that the ideal number of blocks is 5, vs. the 25 to 35 blocks in many designs, and that anything over 35 blocks slows down the design process significantly while driving up costs.

One way around this problem is a heavy reliance on re-use, which in a 100 million-gate design may mean a 90 million-gate platform. That only leaves 10 million gates to design. He also said the very least a tool should handle is 4 million gates on an average overnight run, and that ideally it should be able to handle 20 million gates.

Smith was critical of the process of creating tools, which he said created a disconnect between what is needed by design engineers and what’s available to them. “We still have far too many R&D engineers that don’t have the slightest idea how design engineers use their tools,” he said.

A re-use option that has gained widespread attention in recent months involves stacking of die, either into a complete logic-on-logic stack using through-silicon vias, or as a 2.5D system-in-package approach or package-on-package using interposer technology. Mary Olsson, an analyst at GarySmith EDA, said the real driver will be re-use, but that real success in this market depends heavily upon the ability to produce more known good die for sale commercially.

One driver of that market, she noted, will be the emergence of a middle class within emerging economies, probably in 2015, and only then if there are some advancements in the technology. “Success will be based on a variety of interposer technologies,” Olsson said. “But the technology will be delayed for the next three to five years because there are too many other safe and workable options.”

By Ed Sperling
System-Level Design sat down to discuss the future of EDA with Neil Hand, group director for product marketing in Cadence’s new business group; Mike Gianfagna, vice president of marketing at Atrenta; and Johnson Teng, COO at Springsoft. What follows are excerpts of that discussion.

SLD: Where will the growth come from in EDA? Will it be integration or traditional EDA tools?
Hand: For us it will come from two areas. One is the underlying IP. The second is the integration. Those are both potential growth areas. If we don’t address those, the other stuff doesn’t work.
Gianfagna: A lot of this IP exists today, so if you’re going to re-use it you’d better have a good methodology and documentation for your IP and a good repository. And you better have a front-end tool to help you assemble it. All of those things exist in 3D. They’re just more complicated and the stakes are higher. But the benefits are higher.
Hand: Very few companies use these capabilities today even for a single chip. You need to spend time up front trading off the various IP implementations, and then you need to track it throughout the design.
Teng: 3D stacking will compress the growth for EDA. The whole chip will become more complicated. It’s more than a human being can comprehend.
Hand: But complexity has exploded over the last 20 years. EDA hasn’t.

SLD: What does EDA look like five years out?
Hand: The way we see it is a top-down approach. There will still be the existing class of tools. But in addition to that there will be new tools to address SoC integration. And beyond that is the true system analysis, which is more on the software side.
Teng: Software will play a more important role. In addition, different companies will have to work together to develop solutions.
Gianfagna: It will be a completely different industry in five years. To use the Cadence terminology, if you look at the silicon realization piece—which is the physical implementation through the back end to the foundry—well, you can count the number of foundries on one hand. And each foundry will have its own optimized back-end process to do silicon realization for that process. That means all the back end will be bought up by the foundries, and there will be a new EDA industry that will include everything before that. And there will be a new set of problems that includes IP re-use, assembly, 3D planning, analysis of a 3D stack, and integration at a higher level. The whole EDA industry makes a sharp left and the stuff that pays the bills today becomes a captive technology inside of the foundries.
Hand: Even if it isn’t captive, it’s not a growth engine. But if we don’t address the challenges design starts continue to decline and fewer and fewer companies can afford to do chips.

SLD: Will startups drive EDA growth?
Gianfagna: If you follow it back to the money, I don’t know of an investor that will put down money for an EDA startup in the United States. That’s not true in Europe and Asia, so maybe the industry growth shifts there.
Teng: Asia is not putting money into EDA companies. There are not many companies there.
Gianfagna: But will it change?
Teng: Possibly. Our company is based in Taiwan.
Hand: But it may not be one or the other. It may be a living ecosystem, with the larger companies making these changes to enable customers. Once customers have this fundamental enablement they can start to work at that level of abstraction. Then startups can begin working on those problems. Now, if you’re a startup you can’t innovate because of the complexity. But if we can compartmentalize the problems, then that creates an opening for startups.
Teng: I agree with that. If there’s an opening then smaller companies will build on top of that.
Gianfagna: There’s no emotion here. It’s all about return on investment. If there is a return then the money will come back into EDA.
Hand: Unless the customer can change the way they design as a starting point, then it’s going to be hard to build those capabilities.

SLD: Will the balance shift to software owning hardware or vice versa?
Gianfagna: I think software will drive hardware in the future.
Hand: The software drives the problem. Whether they own the problem remains to be seen. If we don’t give visibility into the problem, then it becomes a purely software-driven problem and a lowest-common denominator for the hardware. That would be a loss for the whole industry. If you’re forcing everyone into commodity and the price becomes exorbitantly expensive, then you start to limit innovation across the board.
Gianfagna: The world will not be homogenized. If you do, someone will figure out a way to differentiate. For many years the hardware guys drove the train and the software guys were along for the ride and trying to figure out how to get this all to work. That’s changing.
Hand: I think it’s already changed.
Gianfagna: I don’t agree with that because I don’t have a clear example yet of a software team driving the hardware architecture.
Hand: But they do define the feature set, which defines the hardware spec. Years ago we built the chip and the software guys utilized it as best they could.
Gianfagna: But what ultimately could change the industry is when the software guys are not simply specifying what they need and are active participants in the design process.
Hand: It’s starting.
Gianfagna: It is, but it’s not all the way there. That’s where the growth is.

SLD: Does that redefine what EDA is today?
Gianfagna: Yes.
Hand: Absolutely. Very few people, when they think of EDA, think about integration and software challenges. There are two ways EDA can grow. One is to convince existing customers to buy more tools. The other is to fundamentally change something so more companies build stuff. If you can change the cost of design and it’s not as hard to build a chip, that’s not necessarily bad. If you can double the size of the market, then you can grow. Now you sell more tools per design start, but the number of design starts is going down because the complexity is going up. Just to keep even you have to get more out of each design.
Gianfagna: That’s going to be important. Otherwise you’re in a death spiral.

By Ed Sperling
System-Level Design sat down to discuss the future of EDA with Neil Hand, group director for product marketing in Cadence’s new business group; Mike Gianfagna, vice president of marketing at Atrenta; and Johnson Teng, COO at Springsoft. What follows are excerpts of that discussion.

SLD: What does EDA need to address that it hasn’t addressed so far?
Hand: EDA traditionally has worked bottom up, and for some problems that works well. But that isn’t always true. Verification is causing a huge explosion in design effort. We haven’t solved that yet, but in the meantime software has become a huge problem and now integration is becoming a problem. We can’t move quickly enough with the bottom-up approach. That’s why we’re starting to look at a more top-down approach.
Gianfagna: Another side to that question is whether EDA is stuck serving the same customer base with the same budget and the same problems, versus finding new customers and expanding the business. That’s one of the things that’s wrong in EDA. As an industry we’re not good at acquiring new customers. We’re all good at fighting for the same pie but we’re not good at expanding the pie. Software is a new challenge. Maybe we need a different approach to verification and a different methodology.
Hand: Part of the reason for that is we look at it from the standpoint of how we go after a new industry, not how we should look at a design problem. People in EDA talk about how we use technology and expand into an adjacency. Even within our existing base we’re not asking questions about what customers need to do design.
Gianfagna: It’s different versus better. Those aren’t the same thing.
Teng: We do have new problems, but the old problems still exist, too. The question is where we’re going to add value for customers. There are new areas like IP and system-level design, but even in verification and closure we have to make sure it’s complete and that all the EDA vendors can work together on this because customers continue to pick best-in-class tools.
Hand: But even if you make verification two times faster, that’s not enough. It’s a huge effort, but the problem is growing faster than that.

SLD: One of the complaints by large companies is that EDA companies aren’t investing in technology to solve the really big problems. Is this the same problem?
Hand: There are going to be two approaches in design. One will be from companies doing front-to-back design. That’s going to be a fairly small subset, though involving very large companies. The problem is too big for most EDA companies to solve, but it’s also too big for most customers—even with better tools.
Gianfagna: To move from an authoring to an integration flow requires massive retooling and changes in the way things are done by the customer. Most customers are very unwilling to make those changes. Does EDA have to lead that charge? My sense is yes, but most EDA companies are viewed as followers rather than leaders by their customers. That’s a problem. As an industry we should be more than a supplier. We should be a partner to our customers.
Teng: I don’t think any single EDA vendor can solve their customers’ problems. It requires the whole EDA industry. We need an open environment so customers can pick the tool to solve their problems.

SLD: Companies in this industry aren’t known for cooperating with each other, yet you’re asking for a tight ecosystem play. So what do you do?
Hand: If you look at this from a customer perspective you can start to define new ways in which the tools and the industry need to work together. If everything is homogeneous, that’s not going to happen. But if you define better points of integration and implementation, it’s easier for companies to work together.

SLD: But that raises issues about who’s liable when something goes wrong, doesn’t it?
Hand: Even today you have those problems. Was it a problem with the tool vendor or an internal one?
Teng: That’s right. Customers have to do integration. Fortunately Cadence introduced OpenAccess and now everyone can write to that open standard.
Gianfagna: The software guys have built a scalable infrastructure. You’ve got middleware, the OS layer, and everyone knows who does what. EDA doesn’t work like that. EDA is like software was in the 1960s. There were one or two players that wanted to own the whole thing.
Hand: The embedded space was like that until recently, as well. Now it’s a more scalable model.
Gianfagna: If software does start to drive hardware, does the embedded software educate the EDA market or does the EDA market begin to corrupt the embedded software world?

SLD: What happens with 3D stacking? This is the coming storm in EDA. Do the tools get used the same way?
Hand: If 3D becomes a technique for system integration and you’re using a class of tools to create known good die, then it does open up new markets. Right now it’s all about new ways of building chips by the same companies. If it becomes a tool for a new class of company where they integrate on the chip rather than in the system, then it opens new opportunityies.
Gianfagna: It also creates more design starts and, hopefully, a more vibrant semiconductor business.

SLD: But most of this seems to be heading toward re-use of older chips and analog IP.
Hand: Yes, but that does create the opportunity for a new class of design.
Gianfagna: There’s a supply chain challenge along with that. Who will be the general contractor? Who takes the inventory risk?
Hand: And who does the integration and confirms it’s going to work? Known good devices sometimes aren’t all that good once you put them into these 3D stacks. So who’s liable in those circumstances?
Gianfagna: I like to think it’s going to open new markets and new opportunities.
Hand: The challenge is coming up with integration-level tools. We’re not there yet.
Gianfagna: If you think about the way the EDA business is growing, it’s growing around the edges rather than in the middle, and more at the front edge. What that means is if you’re going to do a single chip you can battle it out and get it right. For 3D it’s a need to have. There’s a natural focus on the need for more tools and technology. That’s a growth opportunity.
Hand: And there’s lower risk. If you can get more re-use then you have re-use that is lower risk. Ultimately it will lead to die-level re-use.