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Blog Review – Monday, April 10, 2017

Monday, April 10th, 2017

This week, there are traps and lures in the IoT, as discussed by ARM and Maxim Integrated; Xilinx believes a video tutorial is a good use of time; Get cosy with SNUG for some insight; and ON Semiconductor is keeping an eye on you

Beware of delivery men bearing IoT gifts, warns, Donnie Garcia, ARM, who also looks at trap doors and NXP’s Kinetis KBOOT bootloader to foil a new attack vector and advertise a related webinar on April 25.

Nagging parents had the right idea, decides Russ Klein, Mentor Graphics, remembering entreaties to turn off lights, and whose energy saving advice he now applies to SoCs and embedded systems, with the help of the Veloce emulator.

Gabe Moretti, Chip Design, gets a bit saucy, trying to figure just what is Portable Stimulus. He gets down to the nitty gritty with how the Accellera System Initiative can help, but still believes some areas need to attended to. Let’s hope the industry pays heed.

More warnings from Kris Ardis, Maxim Integrated, and connected devices. While a Jacquard print may not be to everyone’s taste, the idea of protecting the IoT and its data has universal appeal.

The appeal of Agile design is not lost on Randy Smith, Sonics, who writes about the concept and Agile software development. He deftly dives into advances in Agile hardware design and IC methodology for Agile techniques – keeping every design engineer on their toes.

A visit to ISC West, the security expo, has made Jason Liu, ON Semiconductor, think about surveillance systems, as he throws a spotlight on one of the company’s introductions.

14 minutes does not sound like a long time to pack in all you need to know about Zynq UltraScale+ MPSoCs and Vivado Design Suite, but Steve Leibson, Xilinx points readers towards an interesting, informative video, which he describes as a fast and painless way to see the development tools used in a fully operation system.

It sounds like a self-satisfied neck-warmer, but SNUG (Synopsys User Group) events can be informative. Tom De Schutter attended the one in Silicon Valley and relates what he learned from the technical track with experts from ARM, NVIDIA, Intel and Synopsys about prototyping latch-based designs, ARM CPU and GPU increasing densities and more besides.

Striving to improve the lot of IoT designers, John Blyler, Embedded Systems, talks to Jim Bruister, SOC Solutions, about markets, licensing, open source and five elements that will drive improvement.

Compiled by Caroline Hayes, Senior Editor

Blog Review – Tuesday, January 10, 2017

Tuesday, January 10th, 2017

Moving on from 4K and 8K, Simon Forrest, Imagination Technologies, reports on 360° video, as seen at this year’s CES in Las Vegas. That, together with High Dynamic Range (HDR) could re-energize the TV broadcasting industry in general and the set-top box in particular.

The IoT is responsible for explosive growth in smart homes with connectivity at their centre. Dan Artusi, Intel, considers what technologies and disciplines are coming together as it introduces Intel Home Wireless Infrastructure at CES 2017.

Announcing a partnership with Renault and OSVehicle, ARM will work with the companies to develop an open source platform for cars, cities and transportation. Soshun Arai, ARM, explains how the ‘stripped down’ Twizy can release the brakes on CAN development.

Some Christmas reading has brought enlightenment to Gabe Moretti, Chip Design, as he unravels the mysteries of CEO comings and goings, and why the EDA industry could learn a thing or two from the boards of spy plane and stealth bomber manufacturers.

Still with EDA, Brian Derrick, Mentor Graphics, likens the automotive industry to sports teams, where big names dominate and capture consumers’ interest, eclipsing all others. This is changing as electric vehicles become a super power to turbo charge the industry.

It’s always good to welcome new blogs, and Sonics delivers with its announcement that it is addressing power management. Grant Pierce, Sonics, introduces the technology and product portfolio to enhance design methods.

Caroline Hayes, Senior Editor

Blog Review Monday April 11 2016

Monday, April 11th, 2016

Mbed development board seeks therapy; in praise of HPC; IoT security – can it be improved?; EDAC name change; acquisition fever runs high

Checking and testing safety critical systems can be performed using the Zynq-7000 All Programmable SoC (AP SoC) with dual ARM Cortex-A9 processors, and dual Neon FPUs. Austin, Xilinx, explains the routine.

Therapy from an mbed development board may not threat therapists just yet, but ELIZA, the computer program that simulates a psychotherapist, is now available for the mbed platform. The obvious question to ask Wilfred Nilsen, ARM, is “How do you feel about that?”

Who needs High Performance Computing (HPC), asks Wim Slagter, Ansys. He addresses computing as a strategic asset, scalability benefits and what to do with a server cluster.

The Internet of Things (IoT) security market will be worth $28.90 billion by 2020, yet it is flawed, argues an unattributed blog from Rambus. Interviews with Simon Blake-Wilson and Ted Harrington, Rambus, assess how much ground needs to be made up.

Still with security, Robert Vamosi, Synopsys reports on the Synopsys and Underwriter’s Laboratory (UL) collaboration to create the UL Cybersecurity Assurance Program (UL CAP). The aim is to increase transparency and confidence in the security of network-connectable devices using expertise from both camps.

Looking ahead to the connected car, Andrew Macleod, Mentor Graphics, considers what will be coming together for a centralized processing system, handling communications and autonomous driving functions. The vehicle’s systems will be consolidated, but how best to achieve that is up for debate.

It may take some people a while to adjust, but the EDA Consortium has changed its name to the Electronic System Design Alliance. Gabe Moretti, Chip Design Magazine, looks at the whys and wherefores behind the change and the expertly analyses the Alliance’s expanded charter.

Intel has bought Yogitech, the functional safety company and Ken Caviasca, Intel, looks at what this means for the company and, in particular, its IoT offering.

Still with acquisitions, it is all getting a bit too much for Chris Ciufo, eecatalog, who traces some recent ‘musical chairs’ before focusing on what the Mercury Computer purchase of three Microsemi businesses will meet for the military market.

Caroline Hayes, Senior Editor

Blog Review – Monday, February 15, 2016

Monday, February 15th, 2016

Research converts contact lens to computer screens; What to see at Embedded World 2016; Remembering Professor Marvin Minsky; How fast is fast and will the IoT protect us?

The possibilities for wearable technology, where a polymer film coating can turn a contact lens into a computer screen are covered by Andrew Spence Nanontechnology University of South Australia’s Future Industries Institute. The lens can be used as a sensor to measure blood glucose levels to a pair of glasses acting as a computer screen.

If you are preparing your Embedded World 2016, Nuremberg, schedule, Philippe Bressy, ARM offers an overview of what will be at his favourite event. He covers the company’s offerings for IoT and connectivity, single board computing, software productivity, automotive and from ARM’s partners to be seen on the ARM booth (Hall 5, stand 338), as well as some of the technical conference’s sessions and classes.

Other temptations can be found at the Xilinx booth at Embedded World (Hall 1, stand 205). Steve Leibson, Xilinx explains how visitors can win a Digilent ARTY Dev Kit based on an Artix-7 A35T -1LI FPGA, with Xilinx Vivado HLx Design Edition.

Showing more of what can be done with the mbed IoT Device Platform, Liam Dillon, ARM, writes about the reference system for SoC design for IoT endpoints, and its latest proof-of-concept platform, Beetle.

How fast is fast, muses Richard Mitchell, Ansys. He focuses on the Ansys 17.0 and its increased speeds for structural analysis simulations and flags up a webinar about Ansys Mechanical using HPC on March 3.

If the IoT is going to be omnipresent, proposes Valerie C, Dassault, can we be sure that it can protect us and asks, what lies ahead.

A pioneer of artificial intelligence, Professor Marvin Minsky as died at the age of 88. Rambus fellow, Dr David G Stork, remembers the man, his career and his legacy on this field of technology.

I do enjoy Whiteboard Wednesdays, and Corrie Callenback, Cadence, has picked a great topic for this one – Sachin Dhingra’s look at automotive Ethernet.

Another thing I particularly enjoy is a party, and Hélène Thibiéroz, Synopsys reminds us that it is 35 years since HSPICE was introduced. (Note to other party-goers: fireworks to celebrate are nice, but cake is better!)

Caroline Hayes, European Editor

Deeper Dive – Wed. April 30 2014

Wednesday, April 30th, 2014

The gang of three, or the Grand Alliance, refers to the co-operation of foundry, IP and EDA companies to make 14nm FinFET a reality. Caroline Hayes, Senior Editor, asked Steve Carlson, Director, office of Chief Strategy Officer, Cadence Design, what was required to bring about FinFET harmony.

What foundry support is needed for any chip maker looking to develop 14/16nm finFET?
SC: The foundry needs to supply a complete enablement kit. This includes traditional PDKs (physical design kits), along with the libraries, technology/rule files for the synthesis, design-for-test, extraction, place and route, EM, IR, Self-heat, ESD, power and timing sign-off, DFM and physical rule checking.

Put another way, enablement content spans from the transistor level support, up through complex SoC design. To get to the production phase of enablement roll-out there have been several tape-outs and test chips of complex SoCs specifically architected to mimic the needs of the early adopters.

What IP technology is needed?
SC: There are many IPs that would be useful in accelerating the development of a new 14/16nm SoC. First and foremost, getting the cell libraries (at least for use as a starting point) is critical. Along with that, many complex high speed interface IPs, such as SERDES are very useful.
If called for architecturally, processor IP, and standard interface IP make a lot of sense to buy, versus make.

What is needed to develop an efficient ecosystem for 14/16nm finFET?
SC: TSMC’s chairman [Morris Chang] has talked about the “grand alliance” with the inclusion of the foundry, IP and EDA partners in a process of early collaborative co-optimization. This co-optimization process gets the new process to production readiness sooner, with known characteristics for key industry favored IP and ensure that the tool flows will deliver on the performance, power, and area promise of the new node.

EDA (Cadence) has made some critical contributions in the roll-out of enablement for FinFET:
We have solved technology challenges such as sign-off accuracy demanded by 14/16nm to within 2 to 3% of Spice on all sign-off tools (Tempus, Voltus, QRC, etc.) We have also brought about low Vdd, which 14/16nm allows, with its challenges in terms of optimization and sign-off.

Other challenges, met and solved are to improve routability for small standard cell size (7.5 tracks).

There are multiple challenges we are meeting today. One is Hold. This is critical, especially with low Vdd and it is supported at different stages in the design and sign-off flow.
There is also signal EM optimization and technology challenges to meet 14/16 nm requirements in terms of placement rules and also routing rules

Assuming that 14/16nm finFET will be used to exploit its dielectric isolation, where do you envisage it will be used?
SC: SOI will continue to fill niche applications and is very unlikely to unseat bulk CMOS. FinFET on SOI may have some advantage over FinFet on bulk for both leakage power and radiation hardness. So military and possibly certain applications (for safety concerns, maybe automotive) may choose FinFET on SOI.

Blog Review – Mon. April 21 2014

Monday, April 21st, 2014

Post silicon preview; Apps to drive for; Motivate to educate; Battery warning; Break it up, bots. By Caroline Hayes, Senior Editor.

Gabe Moretti attended the Freescale Technology Forum and found the ARM Cortex-A57 Carbon Performance Analysis Kit (CPAK) that previews post silicon performance, pre-silicon.

In a considered blog post, Joel Hoffmann, Intel, looks at the top four car apps and what they mean for system designers. He knows what he is talking about, he is preparing for the panel at Open Automotive 14 – Automotive Suppliers: Collaborate or Die in Sweden next month.

How to get the next generation of EDA-focused students to commit is the topic of a short keynote at this year’s DAC by Rob Rutenbar, professor of Computer Science, University of Illinois. Richard Goering, Cadence reports on progress so far with industry collaboration and looks ahead.

Consider managing power in SoCs above all else, urges Scott Seiden, Sonics, who sounds a little frustrated with his cell phone.

Michael Posner, Synopsys, revels in a good fight – between robots in the FIRST student robot design competition. Engaging and educational.

Blog Review – Mon April 14 2014

Monday, April 14th, 2014

Static warning about keyword variables in C language; wearable electronics; more power to the user interface; IP sales – where and when to shop around; EDA consolidation concerns. By Caroline Hayes, Senior Editor

Defining the static keyword in the C language can cause mayhem and confusion, but Jacob Beningo, ARM, has helpful advice in his blog about when and where to declare.

With an eye on the aesthetics of wearable electronics, Ansys’s Sudhir Sharma writes about cool, wearable electronics design, with some interesting examples and practical news for a related webinar using Synapse for engineering services.

As a follow up to his web seminar, called Create Compelling User Interfaces for Embedded with Qt Framework, Phil Brumby sits in the guest blogger seat at Mentor Graphics. He uses it as a platform to complete unfinished business, posting and answering questions not covered in the seminar and to help assess the processor power required for a particular project.

When and what to buy and if to buy at all, is the focus of a well constructed blog by Neha Mittal , Arrow Devices. It defines the four IP development models, and lists the advantages and disadvantages of each.

John Blyler looks at the EDA market’s recent activity for mergers and considers the future, with a Consolidation Curve and the effect consolidation has on the industry and its innovation.

Blog Review – Jan. 13 2014

Monday, January 13th, 2014

Even if you made CES, chances are there were one or two booths you may have missed! This week’s blogs look back at CES 2014, forward to changes that have to be made in EDA, adds gravity with the hunt for an author and sounds a rallying cry for 3D simulation.
By Caroline Hayes, senior editor

Boys’ toys rock as Cadence’s Richard Goering delights in solar powered cars, an ultra-HD 3D wall, a “spy” drone and just where Tensilica IP belongs in all of these.

Still in Vegas, ARM’s Andy Frame takes a tour of CES with videos of racing cars and 3D printers and an interview with ARM CEO Simon Segars – and yes, he does mention IoT but also poses the question of what will this year’s launches produce next year.

At Mentor Graphics, Robin Bornoff has obviously been kept away from the bright lights of Vegas and instead puts the case for 3D computational simulation.

Hamilton Carter continues his epic quest and brings us down to earth with gravity issues.

Gabe Morretti considers the atomic size difference as process nodes continue to count down and the changes for the EDA industry.

Accellera Systems Initiative has taken over OCP-IP

Tuesday, October 15th, 2013

By Gabe Moretti

Accellera has been taking over multiple standards organization in the industry for several years and this is only the latest.  The acquisition includes the current OCP 3.0 standard and supporting infrastructure for reuse of IP blocks used in semiconductor design. OCP-IP and Accellera have been working closely together for many years, but OCP-IP lost corporate and member financial support steadily over the past five years and membership virtually flatlined. Combining the organizations may be the best way to continue  to address interoperability of IP design reuse and jumpstart adoption.

“Our acquisition of OCP assets benefits the worldwide electronic design community by leveraging our technical strengths in developing and delivering standards,” said Shishpal Rawat, Accellera Chair. “With its broad and diverse member base, OCP-IP will complement Accellera’s current portfolio and uniquely position us to further develop standards for the system-level design needs of the electronics industry.”

OCP-IP was originally started by Sonics, Inc. in December 2001 as a means to proliferate it’s network-on-chip approach.  Sonics CTO  Drew Wingard has been a primary driver of the organization.  It has long been perceived as the primary marketing tool of the company and it will be interesting to see how the company (which has been on and off the IPO trail several times since its founding) fairs without being the “big dog” in the discussion.

A comprehensive list of FAQs about the asset acquisition is available.

Tech Travelogue June 2017 – Moore-Metcalf, IOT Chasm, Mechanical Design and 5G

Thursday, August 31st, 2017
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