By Ed Sperling
EDA was up across the board in the last quarter of 2010 in almost every category, rounding out an upswing in the market that began early last year.

In total, EDA revenue increased 19.4% to $1.5 billion, compared with $1.3 billion in the same period in 2009. Sequentially, the numbers grew 15.4% from Q3 to Q4 of 2010. Given the fact that the recovery began in earnest last year for EDA, those sequential numbers arguably are even more significant.

Wally Rhines, CEO of Mentor Graphics and chairman of the EDA Consortium, said the typical pattern is for the semiconductor industry as a whole to emerge from a slump well before EDA takes off again.

“The semiconductor industry began taking off in late 2009,” said Rhines. “This is true to the pattern.”

Those areas showing robust growth were IP, system-level PCB and MCM (multichip module), and DRC. Those areas that were flat to down were layout (except for layout verification), and services.

By geography, the fastest growth was in the Asia/Pacific region. North America and Europe also showed some growth, but not as high as Asia/Pacific. Japan was relatively flat. (See Fig. 1)

Fig. 1: Source: EDAC

By Ed Sperling
Growth returned to almost all sectors of EDA in Q3 of 2010, from ESL to semiconductor IP. Moreover, that growth occurred in all geographies except Japan, with Asia showing the strongest upswing.

In raw numbers, EDA revenue for Q3 was $1.3 billion, which is 11.9% higher than in Q3 of 2009. The numbers also increased sequentially by 6.9% over Q2, so the comparison isn’t just to a down year.

“Typically after a recession EDA lags,” said Wally Rhines, chairman of the EDA Consortium, and chairman and CEO of Mentor Graphics. “That makes this pickup especially encouraging.”

The big winners in the technology categories were IP layout, which grew 11.8% globally (28.5% in Asia/Pacific); Emulation, up 18.5%; design for test, up 75%; and IP, up 25%. ESL grew 4% and power analysis grew 30%, reflecting the complexity of designing semiconductors at advanced nodes.

The number of engineers working in EDA also increased by 1.9% to 26,474 in Q3.

Things were a bit slower in the system-design world. PCB and multi-chip module revenue were down 5.4% compared to Q3 of 2009. The four-quarter moving verage for this sector was down 1.8%.

By region, the Americas were still the strongest buyers of EDA tools. Sales were $577 million, up 12.9% over the same period in 2009. Asia/Pacific bought $274 million in tools, up 34.6%. Rhines noted that most of the tools sales in that region, which includes India, China, Taiwan and Korea, came from large multinational semiconductor companies, whose design teams typically are spread out around the globe.

Source: EDAC

By Ed Sperling
System-Level Design sat down to discuss what’s broken in EDA with Riko Radojcic, director of engineering for CDMA Technologies at Qualcomm; Surinder Dahaliwal, executive director for VLSI Core Engineering at Mindspeed Technologies; Andy Brotman, vice president of design infrastructure at GlobalFoundries, and Paul McLellan, a start-up CEO and blogger. What follows are excerpts of that conversation.

SLD: Where are the problems in chip design these days?
Brotman: We are taping out chips and getting chips out the door, but the real issue we’re see is time to volume. There’s lots of stuff that would allow us to get that fixed and ramp to volume sooner. At advanced nodes there are all sorts of new effects. We need better ways to analyze them to get to working silicon sooner. That includes all the stress effects, layout effects. How do we take layout effects into account early—maybe even estimate them.
Radojcic: We are working on the leading edge, and my sense of what’s broken is the stuff on the fringes of traditional EDA.

SLD: Where there isn’t enough volume to make it worthwhile for the big EDA companies to invest?
Radojcic: Yes. Five years ago the things on the fringes included DFM. A startup company needed to hire one or two guys to understand DFM. Now the fringes are package-chip co-design, or hardware-software co-design. They’re quite broad, fairly separate disciplines, and it’s a hard thing for startups to span and it’s not quite big enough for the big companies to feed yet. That’s where the gap is right now.
Dahaliwal: The industry has been focused on the physical side for some time with DFM and the tools that allow people to get reasonable yields and predict their yields. What they haven’t been focused on is the implementation side. When you have 100 clocks in a chip and get all those clocks synced up correctly, that brings up all sorts of new issues. I agree with the comment about co-design, as well. You may have a chip ready to go but it typically takes you another two years to develop the software. How do you bridge that gap? People have tried to do it with modeling tools, but you can’t model everything. The industry is going through an FPGA prototyping phase now. That will help drive software development ahead of silicon.

SLD: Is Qualcomm doing FPGA prototyping?
Radojcic: We do for some chips.
Dahaliwal: The FPGA gives you the test benches. Either you need a whole new testbench verification or you wing it.

SLD: Are more things broken at each new node, or is it the same stuff plus new stuff?
Radojcic: The new stuff amplifies the Band-Aid from the last node. Stress is a good example.
Brotman: Yes, it was always there but it wasn’t as significant.
Radojcic: Right, we didn’t worry about it. With 3D [stacking] we start worrying about stress in spades. It’s thinning down silicon to nothing.
Brotman: The hardware-software issues are getting bigger because things are getting so complex. And then there are physical effects that are becoming more important. They’ve always been there, but they haven’t been as important. I remember doing a study on the effect of fill at 65nm and it was negligible. At 28nm it’s not negligible.
Radojcic: That was always there, too. But what technology tends to make harder at every node has been something that a point tool could solve. What’s new is that point tools can’t solve it.

SLD: How about the big flows from Synopsys, Mentor and Cadence? How are they holding up?
Brotman: They’re adding stuff. All three of them and Magma have timing-aware fill. They force you to use a DRC (design-rule checking) tool you’re not used to using. It would be smoother with better standards and integration.
Radojcic: They are adding stuff on the leading edge of mainstream. One can argue they’re too slow. But with the fringes they’re not sure it’s going to be big enough. Synopsys has all the pieces, particularly after all the acquisitions. But I don’t see them driving this yet.
Brotman: But even with co-design, they’re talking about the need to develop models to do the co-design. Typically those are more abstract than synthesizable Verilog. On the analog side, you need models for that, too. We don’t see a whole lot of activity in connecting those models to what you’re implementing. Sometimes there’s a disconnect between your model and the analog block.
Dahaliwal: In order to do that you need all the models.
Brotman: And they need to be matched to what you’re implementing.
Dahaliwal: Exactly.
Radojcic: Which is part of the problem. Qualcomm does architectural work and hardware-software co-design two years before the technologies exist. Sitting and waiting for all the pieces—the early development stuff needs to happen two years before the technology exists.
Dahaliwal: And that’s definitely difficult for a small company.
Brotman: It’s also new for the chip developers. They have to develop models, in languages you don’t know.
Radojcic: It’s being able to do early estimating of a design to find the sweet spot for architecture and process technology before all the pieces are in place if you want to tape out at the leading edge.

SLD: The most advanced chip developers have no choice, right? That goes with the turf.
Radojcic: Yes, and in the past you could do that. A smart guru could sit down and say, ‘I know what’s going to happen at 45nm after doing a tapeout at 65nm, or 28nm after 45nm.’ You know it’s going to be smaller and leakier. When a disruptive technology like 3D comes in, you can’t extrapolate from your experience into the future.

SLD: Is it broken or just uncharted?
Radojcic: The fact that we’ve doing all of this early stuff based on a guru’s gut feeling means it’s broken. In uncharted water, that isn’t good enough anymore. So it’s broken.
McLellan: When we’ve had disruptive technologies come along in this industry, historically it’s been startup companies that produce the technology and big companies that apply them. There are almost no examples of big companies generating this stuff internally. Calibre is probably the one big exception. But startups aren’t being funded anymore. It’s not clear where this technology will come from. 3D technology is an example. There are people doing bits and pieces.
Radojcic: There are two issues here. One is that the things that are broken are too big for startups. The other is that startups aren’t funded. I think they will be. The recession is over. Startups will begin again. But the gaps are still too big for startups. Those gaps will remain even if there is funding.
Dahaliwal: What we’re also seeing is the EDA companies are focusing outside the EDA business. Synopsys is adding to its IP business. Cadence is buying Denali. How much will they invest in true EDA as opposed to leveraging adjacent markets?
McLellan: The business model for mainline EDA is broken. It used to be the case that you worked with the leading edge guys, then the mainstream would come through and that would be the cash cow. The mainstream doesn’t come through anymore.
Dahaliwal: The number of companies has gone down, too. There aren’t the companies out there to buy the tools. You’re left with a few large companies buying expensive tools and the small guys trying to live with the tools they have, taking them off maintenance.
McLellan: The small guys are doing FPGA design.

SLD: What you all seem to be agreeing on is that the business model for EDA needs to change, right?
Radojcic: We get the EDA we deserve and are willing to pay for.

SLD: But at the same time, you need EDA more than ever to solve some of these issues.
Radojcic: There’s no doubt that its scope is expanding. The EDA business model grew up when the industry was in expansion mode.
McLellan: The ideal business model for EDA is when loads of people are doing designs and lots of lots of them need tools.

SLD: How about IP? How much of a chip uses third-party IP?
Dahaliwal: In our chips it’s a very large percentage of the content. It’s external IP you build into an architecture. You wrap your own IP around it.
Radojcic: We use a lot of third-party IP, whether it’s soft, like ARM, or harder stuff, like SerDes.
Brotman: We work with the IP vendors. When we’re doing IP with a lead customer and we’re developing it with the IP vendor, there are DFM signoff models. I’ve seen IP that’s better quality and some that’s worse quality from a manufacturing standpoint. A lot of times when we’re working on the development of the IP, there are DFM criteria for them to get paid for the IP.

By Ed Sperling
The EDA industry posted year-over-year positive growth for the first quarter of 2010 vs. 2009, up 4.6% to $1.25 billion. While sequentially that was down 1.2%, it’s still a sign that growth is returning to EDA after successive years of decline.

“This is the first time we’ve seen positive growth since Q4 of 2007,” said Wally Rhines, chairman of both the EDA Consortium and of Mentor Graphics. “Most of that growth was in the front end with CAE, ESL, analog-mixed signal, formal verification and design for test.”

Back-end implementation was weak while silicon IP was strong. And geographically, Europe and North America were flat, Europe was down, and the rest of the world—particularly India, Korea and China—showed strong growth. Asia/Pacific was up 33.2%.

In raw numbers:

1. CAE grew 7.2%
2. Semiconductor IP increased 35.8%
3. IC physical design and verification shrank 9.2%
4. PCB and multi-chip module revenue dropped 8.8%
5. Services revenue declined 20.7%

By Ed Sperling

System-Level Design sat down with Antun Domic, senior vice president and general manager of Synopsys’ Implementation Group; Serge Leef, vice president of new ventures and general manager of the System-Level Engineering Division at Mentor Graphics; John Busco, CAD manager and blogger, and Sanjiv Kaul, executive chairman at Oasys. What follows are excerpts of that conversation.

SLD: The EDA industry often gets the blame for lack of progress in semiconductor design. Why?
Domic: Sometimes the EDA industry gets criticized that we haven’t invested in systems—whatever that means at a certain level. Part of the issue is the wide spectrum of the problem and the lack of definition. We can get you a tool to get from ‘D’ to ‘G’ in a certain sequence.
Leef: And combined with that are poor economics. People interested in solving the system-design problem at the front end are not very numerous. When I used to run the internal EDA organization inside Silicon Graphics we had a guy who was the architect of the graphics pipeline. He had all sorts of fascinating problems and all kinds of things he wanted to model—but he was only one. If a commercial EDA vendor could satisfy him they would sell one copy of the product and charge $1 million for it. The areas with the problems also have poor economics.

SLD: With modeling environments like TLM 2.0, hardware-software co-verification and high-level synthesis, there are a whole bunch of new areas that are not well defined or included in the flow. How do you deal with this?
Leef: There is a dimension of co-verification that has been well understood, which is at the RTL level where you have your design in RTL and you introduce a processor that is expected to run embedded software. The co-verification problem is essentially solved. You have a transmission mechanism that allows the software to be simulated very rapidly with hardware that is not all relevant, and the transmission slows down when you want to observe the bus cycles. At that level of abstraction, this has been solved. But at the higher level of abstraction what we’re running into is a lack of commonly accepted practices as to how people model systems like that. There are numerous examples where people decide to create abstract models that go really fast, and at the end of the day these models are rejected because they do not have enough details to be useful. And once they have enough details to be useful they lose the speed.
Kaul: Most of EDA is not market-sector dependent. RTL-to-GDSII uses the same synthesis tools and place-and-route tools. But when you get to system-level design, people designing cars have very different needs from the people designing airplanes, who have very different needs from the people designing DSPs. The models are key to that. The amount of detail needed on the models varies based on the kind of analysis you want to make. That’s one of the reasons why the market requires very deep domain problem about what the end customer is doing. For most of EDA, you need to understand semiconductor design. But with system-level design you also need a deep understanding of the end market. It’s hard to build, and especially to build it in a cost-effective way.
Leef: If you look at Bosch in the automotive sector, they really do need to model the hardware. However, once they deliver their solution to BMW, then BMW no longer cares what’s inside the electronic control unit. They care about the software and the network. They assume the electronic control unit and all the underlying hardware works correctly. Even though they characterize the problem as system simulation or co-verification, what they’re trying to analyze is drastically different from what Freescale or Infineon are trying to analyze before they gave it to Bosch.
Domic: The problem there becomes how many. In general, the EDA industry is investing much more. EDA has had emulation for quite awhile. We offer boards based on FPGAs where you can map and do some of the software verification. The reason a larger investment is going into these areas is the need for models. It may be hard to create a model for BMW when all they care about is the connection with the outside world. But when a platform gets standardized like a TI OMAP, where you have a couple of ARM cores and DSPs, you can’t provide a virtual platform. The problem has to be bound and specified.
Leef: The back-end part is relatively predictable. At the end of the day you’re going to build silicon. But the front-end part is more and more application-specific. IBM uses similar language to what we use, but once you dig into what they’re trying to accomplish it’s quite different. For example, they were talking about doing simulation at the car level and they were talking about simulating a network that contains 80 computers with sensors and actuators, gigabytes of software, all united by different types of networks. You’re not trying to verify the correctness of a Freescale semiconductor that lives on the ABS (antilock braking system). You’re trying to figure out when a customer presses the brakes, what are the external things that can be tolerated. That involves simulation of traffic on the network, mechanical modeling of the brake system.

SLD: Is this even an EDA problem?
Busco: And how have companies solved this in the past? Is it through in-house modeling? Or have they not even used automation?
Leef: The degree of design automation declines as you move further from tier-two suppliers. The silicon providers in this case—Infineon, Freescale, Renesas—are no different than TI and Intel in terms of the problems they’re trying to solve. When you go to Bosch and Delphi, they start to look more like PCB players. And then you go to the next set of players, they’re airframe designers. It’s a system of systems. The people who run those companies come from either a mechanical background or a financial background. They don’t have a direct appreciation of design automation. They wouldn’t think twice about spending $300 million to $400 million on prototypes, but they would argue over a $5,000 or $50,000 piece of software forever.
Kaul: People in those areas would use C models or The Mathworks.
Leef: The degree of automation in automotive is variable. One company has been trying to use MatLab Simulink, which only allows them to look at one dimension.
Domic: Given this lack of uniformity, and everyone trying to build something ad hoc, people try to answer very specific and narrow questions. Does the ABS react and work with the steering system? It’s a very specific question. You’re not trying to create a model that describes everything that happens to the car because that’s impossible with the current technology. On the other hand, when you do RTL for a chip you have an expectation it is an incredibly complete description of what a chip does. We have no tools that would synthesize a transaction-level model into a C model down to RTL. One part of the problem is that when you build a model you are trying to answer a very specific question.
Leef: The problems you’re describing are deterministic. In distributed systems, determinism is lacking. The problem they’re trying to find as the customer presses the brakes is why the signal doesn’t get to the brakes. It’s because the network is jammed with the temperature reading from the rear seat. The traffic on the bus is something that is irrelevant.
Kaul: These are very domain-specific and very hard to make a commercial business out of. That’s why customers end up doing a lot of this on their own.
Busco: To take a baby step of synthesis and try to raise the abstraction of that hasn’t been more accepted in the design community. Everyone does RTL synthesis. There are so many different domain languages, whether it’s C or SystemC or something based on MatLab, and yet designers are very hesitant to let go of the control and the quality of results they get from RTL.
Leef: The hardware guys are really married to this idea of precision and concurrency and timing being embedded into the language and the software guys see it differently.

SLD: Is it becoming a choice? You’re no longer designing the RTL. You’ve got power issues, software and signal integrity issues. Can you ignore these new techniques and still progress with a chip?
Kaul: Why haven’t people moved higher? Because getting from RTL to silicon is still such a problem. People need to have the level of control they get from RTL, and they need the visibility downstream to be able to design those chips.
Domic: The tools have progressed in terms of taking care of these things. But 20 years ago, if you look at RTL description languages, Intel had its own language, IBM had its own, and Digital [Equipment Corp.] had its own. VHDL took over. There are a myriad of descriptions above RTL.
Leef: But they don’t have a link to implementation.
Domic: I don’t think that’s a problem, because RTL methodology in large companies took over before synthesis was a viable alternative. Intel was using IHDL in the mid-1980s. I don’t think the key issue is a lack of a path to synthesis. But we have not done a good job in telling developers that C may not be perfect, but it’s more than enough to make good progress. Verilog may not be perfect, but for a lot of people it solved 90% of their problems.

By Ed Sperling

System-Level Design sat down with Antun Domic, senior vice president and general manager of Synopsys’ Implementation Group; Serge Leef, vice president of new ventures and general manager of the System-Level Engineering Division at Mentor Graphics; John Busco, CAD manager and blogger, and Sanjiv Kaul, executive chairman at Oasys. What follows are excerpts of that conversation.

SLD: Where is EDA today? Is it more valuable than it used to be?
Leef: EDA user crossroads right now, which has to do with what’s happening with our customers. The group of customers we historically have served is dividing into two camps. One group is doing huge, very complex platform chips. They need sophisticated back-end flow tools, as well as sophisticated front-end tools that allow them to model and experiment with sophisticated 500 million-gate designs. The process for those people is being strained on both edges. However, there are fewer and fewer people that can afford to do huge chips like this, and certainly fewer that can afford to manufacture them. The second group that is emerging and becoming much more prominent is the group that does systems. Their challenge is to take those systems and add value to them, whether it’s through software or industrial design or packaging. The community that’s emerging includes system designers, for whom the large, vertically focused platform chips are becoming more adequate. The motivation for them to do original hardware declines. But they do have to solve system-design problems.
Kaul: You can’t get a chip designed without EDA, and chip design is still very important to our economy. But if you do an analysis on the EDA industry, its competitive position is diminishing. There are fewer people doing these big chips. There is less differentiation between the EDA players. Some would argue there are too many EDA players, and therefore the differentiation is less and the negotiating power of the EDA players is diminished. If you talk to EDA companies, they think they’re not getting enough value for what they produce. It’s more a structure of the industry, with regard to the customers and the competitive position of the industry.
Leef: The trend of the separation of the design community means the EDA industry is having a hard time satisfying the platform chip designers because they really are pushing the state of the art. At the same time, they don’t know what to do about the system-level designers. We have one market that’s diminishing in size but growing in complexity, and then we have this other market that is potentially large but we don’t know how to tap it.

SLD: What’s the user perspective?
Busco: Of course EDA is important, but the value is splitting because the way the design community is getting strung out over many generations of silicon. For people that are still willing to design ASICs for their application at 130nm, or even FPGAs, EDA is necessary. But it’s more of a commodity product. If you’re designing at 40nm 32nm or 28nm, EDA is not only important, it’s incredibly valuable. You can’t do you design without it. That market is getting smaller because the NRE costs are becoming such a high hurdle that many companies cannot justify the design. But for those that can justify it, EDA is just as valuable as it was in the past.
Domic: There are people doing very important and profitable designs at 130nm, and there are people moving to 28nm. The spread is much larger than it used to be. I don’t need the latest signal integrity analysis tools if I’m going to be doing another 130nm derivative. On the other hand, I see that even with the decrease of the number of very large chips, the number of licenses we see being consumed by our customers continues to go up. Going to 32nm and 28nm and forward, we’re finally getting to the point where the only ones able to make the investment will be two or three [EDA] companies. Startups tend to go for not even a tool but a subset of a tool. To design a 100 million-cell chip, very few companies can do it.

SLD: We’re coming at this from two perspectives. One is from the user, the other is from the EDA company.
Domic: But if someone today wants to provide a full place-and-route solution with all the parasitic extraction, DRC and LVS, the R&D investment EDA companies need to make is enormous. You can’t invest more than 30% or 35% of your sales in R&D or Wall Street will question your existence. So we’re seeing a similar problem in EDA. A customer cannot just say they’ll design a 50 million-cell chip. EDA is seeing the same problem. They have to be selective about where they develop their tools.
Kaul: One of the challenges for EDA has been that with new technologies it doesn’t take a very large team to build the technology. Most successful products were built by four or five brilliant guys. Obviously the first release of the product has to have enough value that people will buy it, and the bar can go higher and higher as you move into more complex technologies. But that’s one of the reasons there has been more competition in EDA than is probably healthy.

SLD: Will that continue?
Kaul: As long as the current solutions are not meeting the needs of customers—if it takes five days to run place-and-route on a complex block, for example—there is an opportunity for someone to come in with a better solution. If you need 20,000 servers to run simulation and you’d like to see a 20x improvement, there’s an opportunity. It’s not easy, but it’s what you have to do.
Leef: When I started working at Intel in 1982, they believed the reason they would win was architectural superiority, their ability to push the state of the art in process, and because of their CAD tools. At that time, the EDA landscape was pretty bare and Intel had 300 to 400 people working on EDA tools. It was predicated on the fact that Intel didn’t believe anyone outside of Intel understood their problem well enough to solve it for them. At 22nm, Intel once again believes no one else understands its problem. It’s not inconceivable we might start seeing big semiconductor players bringing EDA back in house.
Kaul: IBM already uses a lot of internal tools.
Domic: It’s more complicated than that. Every quarter Synopsys announces we had one customer that contributed more than 10% of our revenue. At the same time, the internal team than what they had for EDA is larger. I don’t see a return to internal tools, but I do see a combination where they work with a few suppliers in specific areas, and those areas may change in time.
Leef: But if Intel decided one day that it was important enough to distinguish itself with EDA, that could have a big effect. It’s not economically challenging for them.
Domic: Nobody has money to do everything.
Busco: There will continue to be innovation by startups and small shops. It’s something that everyone benefits from. EDA is an academically rigorous and exciting field, so there are a lot of extremely bright people going into these areas. They’re anxious to start up a company with a small team, and we see the benefits. There are needs for new point tools. Some of the existing tools can’t keep up with design sizes or process complexities. Either the point tools from these startups will solve the problem or they will wake up the major players, which is a side benefit. The major players have a strong tendency to become complacent or focus their efforts elsewhere. When a startup shows them that something can be done in a revolutionary way either the startup will walk away with the business or the established player will turn the battleship and come up with a much better product, as well.

SLD: At 28nm and below, are the big chipmakers relying on internally developed tools until the other stuff becomes commercially available?
Busco: It depends on the style of designs. For digital ICs, commercial EDA comprises the vast majority of the solution. Companies have CAD groups to integrate flows and develop point tools where they can add value, but a customer will not write anything like a place-and-route or synthesis tool. Back when signal integrity was a novelty, we may have had to develop our own tricks. But now it’s part of every EDA tool, so there’s no need to develop an in-house solution.
Kaul: Whatever EDA can solve, customers will buy commercially. But EDA companies also have to make business decisions. They try to solve problems they think will give them a competitive advantage or which they can make a business out of. There are certain problems where the data required to make a good product is proprietary. Intel and IBM don’t want to share that with you. They’ll develop it themselves. Either that or the EDA companies don’t want to solve the problem for them because it makes no sense economically. But if these companies can buy commercially, it’s less expensive.
Domic: If you look at innovation at the large companies, Mentor and Synopsys have done a good job providing things that didn’t exist like, lithography checks. Everybody did chip layouts, even though to keep up with the set of rules at 28nm is tough. But when you look at lithography checks, we built a completely new router that will carry us to 28nm and 22nm. When I do see internal efforts, it’s because there is a lot of flux in terms of preferred rules. Every company interested in coming out early with a new technology is doing their own schemes to develop what is important and what isn’t. The investment from the large companies has been pretty significant and has managed to satisfy IC developers. I don’t see many people trying to develop their own lithography checker.
Leef: In the areas where the tool footprint is well defined, the major EDA vendors jump in, invest heavily and come up with good solutions. In areas where the footprint of the tool and the definition of the need are fuzzy, that’s where the customers have a tendency to invest their internal cycles and do things specific to them. But if you’re architecting a chip with 500 million gates, the architectural and system-level alternatives are profound and the EDA industry has not come up with a cohesive set of tool footprints in that area. Almost every customer I talk with that’s trying to solve front-end problems has a home-cooked solution or some combination of commercial, public domain and home-cooked. The boundaries between what the commercial tools can provide and what the in-house tools can provide are fluid, and that’s where we see internal EDA groups putting a lot of effort.

By Pallab Chatterjee

The high cost of SoC development at advanced process nodes is forcing a significant shift in many of the methodologies used in design.

Hierarchical design methods are giving way to IP integration and hierarchical analysis at the architectural and functional design levels. Previously, large blocks were implemented at the top level of the chip and the analysis was pushed off until these top blocks were done and the chip was checked as a whole. The rising complexity of today’s designs and the ability to interpret results from current EDA tools cannot sustain this approach.

This shift in design tasks has been a major point of discussion at a number of recent industry events. The focal point of integration and analysis was presented formally for discussion by Jim Hogan and Paul McLellan at the recent ICCAD conference, and was amplified through the rest of the ICCAD conference as well as at ARM’s Techcon3, the MEMS Executive Congress and the Low Power Workshop. While the main context of the discussion by Hogan and McLellan was EDA business models and the location of the rapidly dissolving profit margins and value in the design flow, the technical conferences presented panels and papers exemplifying the new focal point and methodology.

The role of the integration phase has pretty much been unchanged since the start of IC design. It is separated into three levels: component/device design, IP/block design and architectural/system design integration. While the breadth of the work at these levels has grown and now includes level-specific analysis, the overall scope of the levels remains fairly unchanged over the past 30 years. The component/device design activity has shifted from being a common task performed by all semiconductor companies to a specialized task performed by just a small portion of the supply chain and specialty semiconductor firms.

The MEMS and Low Power events focused on the base process technology and new application device areas. Both areas, which are currently undergoing double-digit revenue growth, are focused on traditional component-level design and process per device functional performance optimization. The MEMS and low power marketplaces have joined standard product memories and largely shifted out of the modern design ecosystem, requiring them to use the old “IDM style” design flow. Due to a lack of transportable and standard design tools, these markets create custom devices, IP blocks and then final full designs on in-house flows for in-house standard product chips.

There is no functional multi-company IP market in these channels. The primary analysis tools are at the mathematical, mechanical and physics levels rather than transportable in high-level languages. The analysis also is very company- and function-specific rather than standards-based.

Following this trend, the fabs and IDMs that are still in the primitive device creation market have been focusing on creation of customized software tools to support integration and analysis. ICCAD had several papers on NBTI (negative bias temperature instability), SEE (single event error), thermal issues, yield and reliability tools and models created by these device manufacturers to perform fab-line specific-use analysis. These are not general-purpose tools with large target audiences. Instead, they are being created by the fabs and IDMs, in conjunction with the universities, for internal use.

At the ARM event, ARM was the primary transistor-level provider of design knowledge for sub-90nm processes, surrounded by an ecosystem that includes a large number of design partners who could use these transistor-level elements as function blocks. Among them are IP and software companies targeting the next level of hierarchical major design activity, which includes analyzing and optimizing these IP blocks. Correspondingly, the technical sessions were no longer focused on the creation and use of the IP in a technology node, but on the integration and interoperability of the IP blocks to implement functions.

Follow the money
The biggest shift in the design trend is that most of the integration and analysis is solely a hardware task, even though the largest development portion for an SOC is the application software. This effort is currently both the largest segment of the development cost and the largest manpower allocation on a project. The software is implemented at multiple levels from microcode to control in-hardware state machines and embedded processors/controllers to standard interface control firmware (such as for DDR3 memory control) to higher-level code such as ECC, operating systems, GUIs, and in-system applications.

The software requires co-verification and iteration of the logic hardware, possibly the IP selected and the software/firmware. This activity is now performed in high-level languages, which are typically many orders of abstraction above the mathematics and physics level issues of the manufacturing process. As a result, there are many traps for the creation of high-level SoC systems that are physically realizable and yieldable.

The biggest challenges facing cost-effective yield in new SOC designs aren’t necessarily the lithographic process or the actual wafer fab. More important is that the designs are being created at high levels of abstraction without regard for the realities of having sub-wavelength active transistors that need to be manufactured in high volume. The systems designers have been hiding behind the “comfort” of the ESL and high-level EDA tools, and have lost touch with the devices that make up the functions. As a result, there is little regard or respect for the concept of a single chip with billions of devices on it, all of which have to work as planned.

Engineers at the conferences say a lot of the issues are due to the commercial EDA vendors making SoC tools having spent literally decades away from the semiconductor manufacturing and device R&D floor, and creating solutions that produce algorithmically and mathematically valid solutions that also are physically unrealistic and which cannot be implemented. As the vendors do not have a good feel for the validity of solution, so go the solutions from their tools not being valid from an engineering perspective. An example of this gap in understanding is the creation of hardware logic solutions with firmware control, which return a fatal error rate in the 1 part per millions region. Given an optimistic perspective that these errors occur in the 1 part per 100 million range, a 1 billion-plus transistor device would then have more than 10 fatal errors in the design.

The knowledge base of creation, integration and verification will need to be re-unified to address this issue. Only then can the industry reverse the point tool segregation of the problem that has been promoted by the EDA industry for the past 20 years so that modern SoC design once again will not be the domain of just a few semiconductor companies.

By Ed Sperling

Let the acquisitions begin. And for good reason: The beginning of a buying spree means the downturn has bottomed out and values of companies will rise in the near future. The buying is only really good when the values are still near the bottom.

Mentor Graphics is paying $13 million for LogicVision, which makes built-in self-test that can be embedded into SoCs. BIST has been around for years. It first appeared in the military in the Minuteman Missile. Since then, it has become almost standard in avionics and computer systems, and has been adapted to include various different types of semiconductors, including programmable BIST.

Synopsys, meanwhile, is acquiring MIPS Technologies‘ analog business group for $22 million in cash. Who said analog was an art rather than a science? 

Another signal of a recovery is the push into new markets. Consider ARM, which has largely kept its focus on embedded processors. Semicast predicts that ARM will become the leading 32-bit microcontroller architecture in 2011. That could be the start of an interesting shakeup in the MCU market, which has been relatively stable for years. The bulk of the market is still in 8-bit and 16-bit MCUs, but ARM hasn’t never been even mentioned in the same sentence as MCUs. Rivals include STMicro, another relative newcomer in this space, and Microchip, which has been the market leader.

For the most part, the EDA industry was so quiet you could hear a pin drop. That might have something to do with the fact that it’s quiet period for many of them. Earnings will begin filtering out this month and we’ll finally be able to see who’s been doing well and who hasn’t. And that could tell us, of course, who will be hiring and where they’ll be coming from. But don’t expect stellar results anywhere.

Case in point: Virage Logic reported a loss of $26.3 million for the quarter, and a loss of $28.9 million for the past two quarters. Translation: Almost all of that hit came in the first quarter of 2009 due to a restructuring charge, with the remainder of the hit at a time when companies pulled back all development of new chips. Revenues for Q1 were $11 million vs. $14.7 million for the same period in 2009. Given the outlook from foundries such as TSMC, the IP licensing and royalties should begin climbing in the very near future.

More good news: Microsoft rolled out Windows 7. Given the less-than-spectacular reviews for Vista, this could help boost sales of computers in a very big way this fall—once all the antitrust disputes are solved.

By Ed Sperling

The market for EDA and IP was down in Q4 of 2008. That should come as no surprise to anyone.

Nevertheless, there were a couple of bright spots even in that bleak picture. Statistics compiled by the EDA Consortium show IP sales were up 7.6 percent, which is a reflection of increased complexity in making SoCs at 65nm and 45nm, as well as better tools and standards for integrating that IP.

IP is about a $1 billion market, according to EDAC Chairman Wally Rhines. Within that sector, ARM is by far the largest single provider of IP and posted most of the gains, he said. Other beneficiaries include MIPS, Virage Logic, Denali, the IP divisions of Mentor Graphics and Synopsys, and a number of smaller players.

Other bright spots:

·      Parasitic extraction, up 10%

·      Process simulation, up 18%

·      Mixed Signal, up 39%

·      Services, up 25%, although much of that is due to eliminating contractors and taking the work in-house.

Most of the growth follows the trends in system-level design, with the greatest growth showing up in the areas of most pain. Since those numbers were recorded, however, there also are glimmers of life in other parts of the industry.

“What we’re seeing is a bounceback from desperation in the fourth quarter to a point now where there is a need for finished goods,” Rhines said. “The February [Semiconductor Industry Association] numbers were negative. In March, there were signs of a bounceback. But the semi industry and electronics tend to sort out early and prices readjust. EDA is one level removed from semiconductors, which makes it harder to read anything into the numbers.”

The total EDA industry was down 17.7%. But industry sources say at least part of that was skewed by Cadence’s change in the way it recognizes revenue, from up-front recognition to recording revenue as it is received. Taking Cadence out of the picture, the industry declined about 8%. That’s still severe, but at least it’s a single-digit decline.

Still, the tools industry is hardly on solid ground. More than half of semiconductor companies are rated “B” or worse. If a number of semiconductor companies go out of business, the overall effect on the EDA industry would be profound.

On a global basis, Europe’s decline was in the single digits while the rest of the world showed double-digit declines. Europe is very system-oriented, but some of its chip makers have stumbled badly in the downturn. 

More designs by fewer companies puts renewed value in the EDA world, according to Ray Bingham, managing director of General Atlantic, a private equity firm. Bingham, the former CEO of Cadence Design Systems, talks about what is changing in technology and globalization.